diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -1262,6 +1262,7 @@ case TargetOpcode::LIFETIME_START: case TargetOpcode::LIFETIME_END: case TargetOpcode::PSEUDO_PROBE: + case TargetOpcode::COMPILER_BARRIER: return true; } } diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1510,6 +1510,10 @@ SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg); + /// A convenience function for creating TargetOpCode::COMPILER_BARRIER nodes. + SDValue getCompilerBarrier(const SDLoc &DL, AtomicOrdering Ordering, + SDValue Chain); + /// Get the specified node if it's already available, or else return NULL. SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef Ops, const SDNodeFlags Flags); diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -209,6 +209,11 @@ HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) +// This is a fence with the singlethread scope. It has a single operand, which +// is the ordering requested. This instruction has `mayLoad` and `mayStore`, so +// that memory operations are not moved around it. +HANDLE_TARGET_OPCODE(COMPILER_BARRIER) + /// The following generic opcodes are not supposed to appear after ISel. /// This is something we might want to relax, but for now, this is convenient /// to produce diagnostics. diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -1293,6 +1293,13 @@ let AsmString = ""; let hasSideEffects = true; } +def COMPILER_BARRIER : StandardPseudoInstruction { + let OutOperandList = (outs); + let InOperandList = (ins i32imm:$ordering); + let AsmString = ""; + let hasSideEffects = true; + let Size = 0; +} // Generic opcodes used in GlobalISel. include "llvm/Target/GenericOpcodes.td" diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -874,6 +874,16 @@ OutStreamer->AddBlankLine(); } +static void emitCompilerBarrierComment(const MachineInstr *MI, AsmPrinter &AP) { + auto Ordering = static_cast(MI->getOperand(0).getImm()); + + SmallString<128> Str; + raw_svector_ostream OS(Str); + OS << " Compiler Barrier: " << toIRString(Ordering); + + AP.OutStreamer->emitRawComment(OS.str()); +} + static void emitKill(const MachineInstr *MI, AsmPrinter &AP) { std::string Str; raw_string_ostream OS(Str); @@ -1243,6 +1253,9 @@ case TargetOpcode::PSEUDO_PROBE: emitPseudoProbe(MI); break; + case TargetOpcode::COMPILER_BARRIER: + emitCompilerBarrierComment(&MI, *this); + break; default: emitInstruction(&MI); if (CanDoExtraAnalysis) { diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp --- a/llvm/lib/CodeGen/PatchableFunction.cpp +++ b/llvm/lib/CodeGen/PatchableFunction.cpp @@ -50,6 +50,7 @@ case TargetOpcode::GC_LABEL: case TargetOpcode::DBG_VALUE: case TargetOpcode::DBG_LABEL: + case TargetOpcode::COMPILER_BARRIER: return true; } } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3004,6 +3004,15 @@ Results.push_back(Res.getValue(1)); break; } + case ISD::ATOMIC_FENCE: { + if (Node->getConstantOperandVal(2) == SyncScope::SingleThread) { + SDValue Chain = Node->getOperand(0); + auto Ordering = + static_cast(Node->getConstantOperandVal(1)); + Results.push_back(DAG.getCompilerBarrier(dl, Ordering, Chain)); + } + break; + } case ISD::DYNAMIC_STACKALLOC: ExpandDYNAMIC_STACKALLOC(Node, Results); break; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -8290,6 +8290,15 @@ return SDValue(Result, 0); } +SDValue SelectionDAG::getCompilerBarrier(const SDLoc &DL, + AtomicOrdering Ordering, + SDValue Chain) { + SDValue OrderingVal = getTargetConstant((uint64_t)Ordering, DL, MVT::i32); + SDNode *Result = getMachineNode(TargetOpcode::COMPILER_BARRIER, DL, + MVT::Other, {OrderingVal, Chain}); + return SDValue(Result, 0); +} + /// getNodeIfExists - Get the specified node if it's already available, or /// else return NULL. SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td --- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td @@ -13,9 +13,8 @@ //===---------------------------------- // Atomic fences //===---------------------------------- -let AddedComplexity = 15, Size = 0 in -def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering), - [(atomic_fence timm:$ordering, 0)]>, Sched<[]>; +let AddedComplexity = 15 in +def : Pat<(atomic_fence (timm:$ordering), 0), (COMPILER_BARRIER i32:$ordering)>; def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>; def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -276,12 +276,6 @@ } } - if (Opcode == AArch64::CompilerBarrier) { - O << '\t' << MAI.getCommentString() << " COMPILER BARRIER"; - printAnnotation(O, Annot); - return; - } - if (Opcode == AArch64::SPACE) { O << '\t' << MAI.getCommentString() << " SPACE " << MI->getOperand(1).getImm(); diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -604,9 +604,7 @@ return; } - if (MI.getOpcode() == AArch64::CompilerBarrier || - MI.getOpcode() == AArch64::SPACE) { - // CompilerBarrier just prevents the compiler from reordering accesses, and + if (MI.getOpcode() == AArch64::SPACE) { // SPACE just increases basic block size, in both cases no actual code. return; } diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -6398,10 +6398,4 @@ NoItinerary, []>, Sched<[]>; } -def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, - [(atomic_fence timm:$ordering, 0)]> { - let hasSideEffects = 1; - let Size = 0; - let AsmString = "@ COMPILER BARRIER"; - let hasNoSchedulingInfo = 1; -} +def : Pat<(atomic_fence (timm:$ordering), 0), (COMPILER_BARRIER i32:$ordering)>; diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td --- a/llvm/lib/Target/ARM/ARMScheduleA57.td +++ b/llvm/lib/Target/ARM/ARMScheduleA57.td @@ -119,8 +119,7 @@ "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$", "(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE", "(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG", - "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier", - "t__brkdiv0")>; + "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "t__brkdiv0")>; def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>; @@ -1495,4 +1494,3 @@ def : ReadAdvance; } // SchedModel = CortexA57Model - diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp --- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp +++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp @@ -486,6 +486,7 @@ case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: case TargetOpcode::DBG_VALUE: + case TargetOpcode::COMPILER_BARRIER: return 0; case TargetOpcode::INLINEASM: case TargetOpcode::INLINEASM_BR: { @@ -571,4 +572,3 @@ } } // end of namespace llvm - diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -294,6 +294,7 @@ case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: case TargetOpcode::DBG_VALUE: + case TargetOpcode::COMPILER_BARRIER: return 0; case TargetOpcode::INLINEASM: case TargetOpcode::INLINEASM_BR: { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -894,4 +894,4 @@ } } return None; -} \ No newline at end of file +} diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -489,6 +489,7 @@ case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: case TargetOpcode::DBG_VALUE: + case TargetOpcode::COMPILER_BARRIER: return 0; // These values are determined based on RISCVExpandAtomicPseudoInsts, // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -286,6 +286,8 @@ let ParserMatchClass = ImmXLenAsmOperand<"", "LI">; } +def xlentimm_nonzero : TImmLeaf; + // Standalone (codegen-only) immleaf patterns. def simm32 : ImmLeaf(Imm);}]>; def simm32hi20 : ImmLeaf(Imm);}]>; @@ -1119,6 +1121,8 @@ // Refer to Table A.6 in the version 2.3 draft of the RISC-V Instruction Set // Manual: Volume I. +def : Pat<(atomic_fence (timm:$ordering), 0), (COMPILER_BARRIER i32:$ordering)>; + // fence acquire -> fence r, rw def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>; // fence release -> fence rw, w diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -642,7 +642,6 @@ PROBED_ALLOCA, // Memory barriers. - MEMBARRIER, MFENCE, // Get a random integer and indicate whether it is valid in CF. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -28648,8 +28648,8 @@ return emitLockedStackOp(DAG, Subtarget, Chain, dl); } - // MEMBARRIER is a compiler barrier; it codegens to a no-op. - return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); + // COMPILER_BARRIER codegens to a 0-byte instruction. + return DAG.getCompilerBarrier(dl, FenceOrdering, Op.getOperand(0)); } static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget &Subtarget, @@ -29193,8 +29193,9 @@ return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), DAG.getUNDEF(VT), NewChain); } - // MEMBARRIER is a compiler barrier; it codegens to a no-op. - SDValue NewChain = DAG.getNode(X86ISD::MEMBARRIER, DL, MVT::Other, Chain); + + // COMPILER_BARRIER is a compiler barrier; it codegens to a no-op. + SDValue NewChain = DAG.getCompilerBarrier(DL, AN->getOrdering(), Chain); assert(!N->hasAnyUseOfValue(0)); // NOTE: The getUNDEF is needed to give something for the unused result 0. return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), @@ -30959,7 +30960,6 @@ NODE_NAME_CASE(VASTART_SAVE_XMM_REGS) NODE_NAME_CASE(VAARG_64) NODE_NAME_CASE(WIN_ALLOCA) - NODE_NAME_CASE(MEMBARRIER) NODE_NAME_CASE(MFENCE) NODE_NAME_CASE(SEG_ALLOCA) NODE_NAME_CASE(PROBED_ALLOCA) diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -647,11 +647,6 @@ Requires<[Not64BitMode]>, OpSize32, LOCK, Sched<[WriteALURMW]>; -let hasSideEffects = 1 in -def Int_MemBarrier : I<0, Pseudo, (outs), (ins), - "#MEMBARRIER", - [(X86MemBarrier)]>, Sched<[WriteLoad]>; - // RegOpc corresponds to the mr version of the instruction // ImmOpc corresponds to the mi version of the instruction // ImmOpc8 corresponds to the mi8 version of the instruction diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -146,6 +146,7 @@ case TargetOpcode::COPY: case TargetOpcode::INSERT_SUBREG: case TargetOpcode::SUBREG_TO_REG: + case TargetOpcode::COMPILER_BARRIER: return true; // On x86 it is believed that imul is constant time w.r.t. the loaded data. diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -122,7 +122,7 @@ def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; -def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; +def SDT_X86MFENCE : SDTypeProfile<0, 0, []>; def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>; @@ -132,9 +132,7 @@ SDTCisVT<2, v2i64>, SDTCisPtrTy<3>]>; -def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, - [SDNPHasChain,SDNPSideEffect]>; -def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, +def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MFENCE, [SDNPHasChain]>; diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -2387,11 +2387,6 @@ case TargetOpcode::DBG_VALUE: llvm_unreachable("Should be handled target independently"); - // Emit nothing here but a comment if we can. - case X86::Int_MemBarrier: - OutStreamer->emitRawComment("MEMBARRIER"); - return; - case X86::EH_RETURN: case X86::EH_RETURN64: { // Lower these as normal, but add some comments. diff --git a/llvm/test/CodeGen/AArch64/fence-singlethread.ll b/llvm/test/CodeGen/AArch64/fence-singlethread.ll --- a/llvm/test/CodeGen/AArch64/fence-singlethread.ll +++ b/llvm/test/CodeGen/AArch64/fence-singlethread.ll @@ -8,12 +8,12 @@ define void @fence_singlethread() { ; LINUX-LABEL: fence_singlethread: ; LINUX-NOT: dmb -; LINUX: // COMPILER BARRIER +; LINUX: // Compiler Barrier: seq_cst ; LINUX-NOT: dmb ; IOS-LABEL: fence_singlethread: ; IOS-NOT: dmb -; IOS: ; COMPILER BARRIER +; IOS: ; Compiler Barrier: seq_cst ; IOS-NOT: dmb fence syncscope("singlethread") seq_cst diff --git a/llvm/test/CodeGen/ARM/fence-singlethread.ll b/llvm/test/CodeGen/ARM/fence-singlethread.ll --- a/llvm/test/CodeGen/ARM/fence-singlethread.ll +++ b/llvm/test/CodeGen/ARM/fence-singlethread.ll @@ -8,7 +8,7 @@ define void @fence_singlethread() { ; CHECK-LABEL: fence_singlethread: ; CHECK-NOT: dmb -; CHECK: @ COMPILER BARRIER +; CHECK: @ Compiler Barrier: seq_cst ; CHECK-NOT: dmb fence syncscope("singlethread") seq_cst diff --git a/llvm/test/CodeGen/RISCV/atomic-fence.ll b/llvm/test/CodeGen/RISCV/atomic-fence.ll --- a/llvm/test/CodeGen/RISCV/atomic-fence.ll +++ b/llvm/test/CodeGen/RISCV/atomic-fence.ll @@ -63,3 +63,60 @@ fence seq_cst ret void } + +define void @fence_st_acquire() nounwind { +; RV32I-LABEL: fence_st_acquire: +; RV32I: # %bb.0: +; RV32I-NEXT: fence r, rw +; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_st_acquire: +; RV64I: # %bb.0: +; RV64I-NEXT: fence r, rw +; RV64I-NEXT: ret +; RV641-EMPTY: + fence syncscope("singlethread") acquire + ret void +} + +define void @fence_st_release() nounwind { +; RV32I-LABEL: fence_st_release: +; RV32I: # %bb.0: +; RV32I-NEXT: fence rw, w +; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_st_release: +; RV64I: # %bb.0: +; RV64I-NEXT: fence rw, w +; RV64I-NEXT: ret + fence syncscope("singlethread") release + ret void +} + +define void @fence_st_acq_rel() nounwind { +; RV32I-LABEL: fence_st_acq_rel: +; RV32I: # %bb.0: +; RV32I-NEXT: fence.tso +; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_st_acq_rel: +; RV64I: # %bb.0: +; RV64I-NEXT: fence.tso +; RV64I-NEXT: ret + fence syncscope("singlethread") acq_rel + ret void +} + +define void @fence_st_seq_cst() nounwind { +; RV32I-LABEL: fence_st_seq_cst: +; RV32I: # %bb.0: +; RV32I-NEXT: fence rw, rw +; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_st_seq_cst: +; RV64I: # %bb.0: +; RV64I-NEXT: fence rw, rw +; RV64I-NEXT: ret + fence syncscope("singlethread") seq_cst + ret void +} diff --git a/llvm/test/CodeGen/X86/atomic-idempotent.ll b/llvm/test/CodeGen/X86/atomic-idempotent.ll --- a/llvm/test/CodeGen/X86/atomic-idempotent.ll +++ b/llvm/test/CodeGen/X86/atomic-idempotent.ll @@ -342,17 +342,19 @@ define void @or32_nouse_monotonic(i32* %p) { ; X64-LABEL: or32_nouse_monotonic: ; X64: # %bb.0: -; X64-NEXT: #MEMBARRIER +; X64-NEXT: # Compiler Barrier: monotonic ; X64-NEXT: retq ; ; X86-GENERIC-LABEL: or32_nouse_monotonic: ; X86-GENERIC: # %bb.0: -; X86-GENERIC-NEXT: #MEMBARRIER +; X86-GENERIC-NEXT: # Compiler Barrier: monotonic ; X86-GENERIC-NEXT: retl ; ; X86-ATOM-LABEL: or32_nouse_monotonic: ; X86-ATOM: # %bb.0: -; X86-ATOM-NEXT: #MEMBARRIER +; X86-ATOM-NEXT: # Compiler Barrier: monotonic +; X86-ATOM-NEXT: nop +; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop @@ -368,17 +370,19 @@ define void @or32_nouse_acquire(i32* %p) { ; X64-LABEL: or32_nouse_acquire: ; X64: # %bb.0: -; X64-NEXT: #MEMBARRIER +; X64-NEXT: # Compiler Barrier: acquire ; X64-NEXT: retq ; ; X86-GENERIC-LABEL: or32_nouse_acquire: ; X86-GENERIC: # %bb.0: -; X86-GENERIC-NEXT: #MEMBARRIER +; X86-GENERIC-NEXT: # Compiler Barrier: acquire ; X86-GENERIC-NEXT: retl ; ; X86-ATOM-LABEL: or32_nouse_acquire: ; X86-ATOM: # %bb.0: -; X86-ATOM-NEXT: #MEMBARRIER +; X86-ATOM-NEXT: # Compiler Barrier: acquire +; X86-ATOM-NEXT: nop +; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop @@ -393,17 +397,19 @@ define void @or32_nouse_release(i32* %p) { ; X64-LABEL: or32_nouse_release: ; X64: # %bb.0: -; X64-NEXT: #MEMBARRIER +; X64-NEXT: # Compiler Barrier: release ; X64-NEXT: retq ; ; X86-GENERIC-LABEL: or32_nouse_release: ; X86-GENERIC: # %bb.0: -; X86-GENERIC-NEXT: #MEMBARRIER +; X86-GENERIC-NEXT: # Compiler Barrier: release ; X86-GENERIC-NEXT: retl ; ; X86-ATOM-LABEL: or32_nouse_release: ; X86-ATOM: # %bb.0: -; X86-ATOM-NEXT: #MEMBARRIER +; X86-ATOM-NEXT: # Compiler Barrier: release +; X86-ATOM-NEXT: nop +; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop @@ -418,17 +424,19 @@ define void @or32_nouse_acq_rel(i32* %p) { ; X64-LABEL: or32_nouse_acq_rel: ; X64: # %bb.0: -; X64-NEXT: #MEMBARRIER +; X64-NEXT: # Compiler Barrier: acq_rel ; X64-NEXT: retq ; ; X86-GENERIC-LABEL: or32_nouse_acq_rel: ; X86-GENERIC: # %bb.0: -; X86-GENERIC-NEXT: #MEMBARRIER +; X86-GENERIC-NEXT: # Compiler Barrier: acq_rel ; X86-GENERIC-NEXT: retl ; ; X86-ATOM-LABEL: or32_nouse_acq_rel: ; X86-ATOM: # %bb.0: -; X86-ATOM-NEXT: #MEMBARRIER +; X86-ATOM-NEXT: # Compiler Barrier: acq_rel +; X86-ATOM-NEXT: nop +; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop ; X86-ATOM-NEXT: nop diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll --- a/llvm/test/CodeGen/X86/atomic-unordered.ll +++ b/llvm/test/CodeGen/X86/atomic-unordered.ll @@ -2343,7 +2343,7 @@ ; CHECK-LABEL: nofold_fence_acquire: ; CHECK: # %bb.0: ; CHECK-NEXT: movq (%rdi), %rax -; CHECK-NEXT: #MEMBARRIER +; CHECK-NEXT: # Compiler Barrier: acquire ; CHECK-NEXT: addq $15, %rax ; CHECK-NEXT: retq %v = load atomic i64, i64* %p unordered, align 8 @@ -2357,7 +2357,7 @@ ; CHECK-LABEL: nofold_stfence: ; CHECK: # %bb.0: ; CHECK-NEXT: movq (%rdi), %rax -; CHECK-NEXT: #MEMBARRIER +; CHECK-NEXT: # Compiler Barrier: seq_cst ; CHECK-NEXT: addq $15, %rax ; CHECK-NEXT: retq %v = load atomic i64, i64* %p unordered, align 8 diff --git a/llvm/test/CodeGen/X86/barrier-sse.ll b/llvm/test/CodeGen/X86/barrier-sse.ll --- a/llvm/test/CodeGen/X86/barrier-sse.ll +++ b/llvm/test/CodeGen/X86/barrier-sse.ll @@ -1,14 +1,15 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s define void @test() { +; CHECK-LABEL: test fence acquire - ; CHECK: #MEMBARRIER + ; CHECK: ## Compiler Barrier: acquire fence release - ; CHECK: #MEMBARRIER + ; CHECK: ## Compiler Barrier: release fence acq_rel - ; CHECK: #MEMBARRIER + ; CHECK: ## Compiler Barrier: acq_rel ret void } diff --git a/llvm/test/CodeGen/X86/implicit-null-check.ll b/llvm/test/CodeGen/X86/implicit-null-check.ll --- a/llvm/test/CodeGen/X86/implicit-null-check.ll +++ b/llvm/test/CodeGen/X86/implicit-null-check.ll @@ -441,7 +441,7 @@ ; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: je LBB16_1 ; CHECK-NEXT: ## %bb.2: ## %not_null -; CHECK-NEXT: ##MEMBARRIER +; CHECK-NEXT: ## Compiler Barrier: acquire ; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: retq ; CHECK-NEXT: LBB16_1: ## %is_null