diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -1466,6 +1466,8 @@
       Register DupReg = Dup->getOperand(Idx).getReg();
       MRI->replaceRegWith(Reg, DupReg);
       MRI->clearKillFlags(DupReg);
+      // clear Dup dead flag if any, we will reuse it soon.
+      const_cast<MachineInstr *>(Dup)->getOperand(Idx).setIsDead(false);
     }
 
     MI->eraseFromParent();
diff --git a/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN:   -verify-machineinstrs %s -o - | FileCheck %s
+---
+name: deadFlagAfterCSE
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: deadFlagAfterCSE
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $x3, $x4
+  ; CHECK:   [[COPY:%[0-9]+]]:g8rc = COPY $x3
+  ; CHECK:   [[COPY1:%[0-9]+]]:g8rc = COPY $x4
+  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADD8 [[COPY]], [[COPY1]]
+  ; CHECK:   [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[ADD8_]], 100
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADD8_]], %bb.0, %5, %bb.1
+  ; CHECK:   STDX [[PHI]], [[ADDI8_]], [[ADD8_]]
+  ; CHECK:   [[ADDI8_1:%[0-9]+]]:g8rc = nuw ADDI8 [[PHI]], 1
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.2:
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm
+  bb.0:
+    liveins: $x3, $x4
+    %0:g8rc = COPY $x3
+    %1:g8rc = COPY $x4
+    %2:g8rc_and_g8rc_nox0 = ADD8 %0, %1
+    dead %3:g8rc_and_g8rc_nox0 = ADDI8 %2, 100
+    B %bb.1
+
+  bb.1:
+    %4:g8rc_and_g8rc_nox0 = PHI %2, %bb.0, %6, %bb.1
+    %5:g8rc_and_g8rc_nox0 = ADDI8 %2, 100
+    STDX %4, %5, %2
+    %6:g8rc = nuw ADDI8 %4, 1
+    B %bb.1
+
+  bb.2:
+    BLR8 implicit $lr8, implicit $rm
+...
+