diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9413,6 +9413,8 @@ bool refineIndexType(MaskedScatterSDNode *MSC, SDValue &Index, bool Scaled, SelectionDAG &DAG) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if(Index.getNumOperands() == 0) + return false; SDValue Op = Index.getOperand(0); if (Index.getOpcode() == ISD::ZERO_EXTEND) { diff --git a/llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll b/llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll @@ -0,0 +1,48 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s + +define void @main(<48 x float*> %elemBasePtr.) +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmovq %rcx, %xmm0 +; CHECK-NEXT: vmovq %rdx, %xmm1 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; CHECK-NEXT: vmovq %rsi, %xmm1 +; CHECK-NEXT: vmovq %rdi, %xmm2 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0] +; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; CHECK-NEXT: vmovq %r9, %xmm1 +; CHECK-NEXT: vmovq %r8, %xmm2 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0] +; CHECK-NEXT: vinserti128 $1, {{[0-9]+}}(%rsp), %ymm1, %ymm1 +; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 +; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm1 +; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm2 +; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm3 +; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm4 +; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm5 +; CHECK-NEXT: kxnorw %k0, %k0, %k1 +; CHECK-NEXT: vmovaps {{.*#+}} ymm6 = [8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1,8.435871E-1] +; CHECK-NEXT: kxnorw %k0, %k0, %k2 +; CHECK-NEXT: vscatterqps %ymm6, (,%zmm0) {%k2} +; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [1.69435993E-1,8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1] +; CHECK-NEXT: kxnorw %k0, %k0, %k2 +; CHECK-NEXT: vscatterqps %ymm0, (,%zmm5) {%k2} +; CHECK-NEXT: vmovaps {{.*#+}} ymm5 = [8.435871E-1,1.69435993E-1,8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1,8.435871E-1,1.69435993E-1] +; CHECK-NEXT: kxnorw %k0, %k0, %k2 +; CHECK-NEXT: vscatterqps %ymm5, (,%zmm4) {%k2} +; CHECK-NEXT: kxnorw %k0, %k0, %k2 +; CHECK-NEXT: vscatterqps %ymm6, (,%zmm3) {%k2} +; CHECK-NEXT: kxnorw %k0, %k0, %k2 +; CHECK-NEXT: vscatterqps %ymm0, (,%zmm2) {%k2} +; CHECK-NEXT: vscatterqps %ymm5, (,%zmm1) {%k1} +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq +{ +entry: + call void @llvm.masked.scatter.v48f32.v48p0f32(<48 x float> , <48 x float*> %elemBasePtr., i32 4, <48 x i1> ) + ret void +} + +; Function Attrs: nofree nosync nounwind willreturn writeonly +declare void @llvm.masked.scatter.v48f32.v48p0f32(<48 x float>, <48 x float*>, i32 immarg, <48 x i1>)