diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -163,6 +163,10 @@
                    : "=r"(start_reg)
                    : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
   assert(start_reg == 0 && "Cache flush syscall failed.");
+#elif defined(__riscv)
+  // Baremetal riscv don't use SBI call flushing cache, it will directly use
+  // fence.i instruction.
+  __asm __volatile("fence.i")
 #else
 #if __APPLE__
   // On Darwin, sys_icache_invalidate() provides this functionality