diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2574,6 +2574,34 @@
  def : Pat<(f64 nzFPImmAsi32:$A),
            (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
                              VSFRC)>;
+
+  // Anonymous patterns for XXEVAL
+  // AND
+  def : Pat<(v4i32 (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, 1))>;
+  def : Pat<(v4i32 (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, 6))>;
+  def : Pat<(v4i32 (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, 7))>;
+  def : Pat<(v4i32 (and v4i32:$vA, (vnot_ppc (or v4i32:$vB, v4i32:$vC)))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, 8))>;
+  def : Pat<(v4i32 (and v4i32:$vA, (vnot_ppc (xor v4i32:$vB, v4i32:$vC)))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, 9))>;
+  def : Pat<(v4i32 (and v4i32:$vA, (vnot_ppc (and v4i32:$vB, v4i32:$vC)))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, 14))>;
+  // NAND
+  def : Pat<(v4i32 (vnot_ppc (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, !sub(255, 1)))>;
+  def : Pat<(v4i32 (vnot_ppc (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, !sub(255, 6)))>;
+  def : Pat<(v4i32 (vnot_ppc (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, !sub(255, 7)))>;
+  def : Pat<(v4i32 (or (vnot_ppc v4i32:$vA), (or v4i32:$vB, v4i32:$vC))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, !sub(255, 8)))>;
+  def : Pat<(v4i32 (or (vnot_ppc v4i32:$vA), (xor v4i32:$vB, v4i32:$vC))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, !sub(255, 9)))>;
+  def : Pat<(v4i32 (or (vnot_ppc v4i32:$vA), (and v4i32:$vB, v4i32:$vC))),
+            (v4i32 (XXEVAL $vA, $vB, $vC, !sub(255, 14)))>;
 }
 
 let Predicates = [PrefixInstrs] in {
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-and-nand.ll b/llvm/test/CodeGen/PowerPC/xxeval-and-nand.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-and-nand.ll
@@ -0,0 +1,156 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_not
+; CHECK:         xxlandc v2, v2, v3
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_not(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %neg = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and = and <4 x i32> %neg, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_and
+; CHECK:         xxeval v2, v3, v2, v4, 1
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %B, %A
+  %and1 = and <4 x i32> %and, %C
+  ret <4 x i32> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_nand
+; CHECK:         xxeval v2, v2, v4, v3, 14
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %C, %B
+  %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and1 = and <4 x i32> %neg, %A
+  ret <4 x i32> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_or
+; CHECK:         xxeval v2, v2, v4, v3, 7
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %or = or <4 x i32> %C, %B
+  %and = and <4 x i32> %or, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_nor
+; CHECK:         xxeval v2, v2, v4, v3, 8
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %or = or <4 x i32> %C, %B
+  %neg = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and = and <4 x i32> %neg, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_xor
+; CHECK:         xxeval v2, v2, v4, v3, 6
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %C, %B
+  %and = and <4 x i32> %xor, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_eqv
+; CHECK:         xxeval v2, v2, v3, v4, 9
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg = xor <4 x i32> %xor, %C
+  %and = and <4 x i32> %neg, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_nand
+; CHECK:         xxeval v2, v2, v4, v3, 241
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %C, %B
+  %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg2 = or <4 x i32> %and, %A.not
+  ret <4 x i32> %neg2
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_and
+; CHECK:         xxeval v2, v3, v2, v4, 254
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %B, %A
+  %and1 = and <4 x i32> %and, %C
+  %neg = xor <4 x i32> %and1, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %neg
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_xor
+; CHECK:         xxeval v2, v2, v4, v3, 249
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %C, %B
+  %and = and <4 x i32> %xor, %A
+  %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %neg
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_eqv
+; CHECK:         xxeval v2, v2, v4, v3, 246
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %C, %B
+  %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg1 = or <4 x i32> %xor, %A.not
+  ret <4 x i32> %neg1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_or
+; CHECK:         xxeval v2, v2, v4, v3, 248
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %or = or <4 x i32> %C, %B
+  %and = and <4 x i32> %or, %A
+  %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %neg
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_nor
+; CHECK:         xxeval v2, v2, v3, v4, 247
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %or = or <4 x i32> %A.not, %B
+  %neg1 = or <4 x i32> %or, %C
+  ret <4 x i32> %neg1
+}
+
+attributes #0 = { nounwind }