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[Intrinsics] Re-remove experimental_vector_reduce intrinsics
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Authored by dmgreen on Dec 1 2020, 10:57 AM.

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sstefan1
aemerson
nikic

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rG99eb0f16c35c: [Intrinsics] Re-remove experimental_vector_reduce intrinsics

Summary

These appear to have been re-added by rGfbfb1c790982277eaa5134c2b6aa001e97fe828d, but probably should not have been? This removes the experimental versions of the reduction intrinsics again, leaving the non experimental versions.

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Repository: rG LLVM Github Monorepo

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dmgreen created this revision.Dec 1 2020, 10:57 AM

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dmgreen requested review of this revision.Dec 1 2020, 10:57 AM

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LGTM

This revision is now accepted and ready to land.Dec 1 2020, 11:20 AM

Definitely not intentional, sorry.

Thanks. It looked like a merge conflict gone awry, but I wanted to be sure it wasn't done purposefully.

Closed by commit rG99eb0f16c35c: [Intrinsics] Re-remove experimental_vector_reduce intrinsics (authored by dmgreen). · Explain WhyDec 2 2020, 1:23 AM

This revision was automatically updated to reflect the committed changes.

dmgreen added a commit: rG99eb0f16c35c: [Intrinsics] Re-remove experimental_vector_reduce intrinsics.

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llvm/

include/

llvm/

IR/

Intrinsics.td

28 lines

Diff 308908

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 1,512 Lines • ▼ Show 20 Lines	let IntrProperties = [IntrNoMem] in {
def int_vector_reduce_umax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],		def int_vector_reduce_umax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;		[llvm_anyvector_ty]>;
def int_vector_reduce_umin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],		def int_vector_reduce_umin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;		[llvm_anyvector_ty]>;
def int_vector_reduce_fmax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],		def int_vector_reduce_fmax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;		[llvm_anyvector_ty]>;
def int_vector_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],		def int_vector_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;		[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_v2_fadd : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>,
llvm_anyvector_ty]>;
def int_experimental_vector_reduce_v2_fmul : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>,
llvm_anyvector_ty]>;
def int_experimental_vector_reduce_add : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_mul : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_and : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_or : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_xor : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_smax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_smin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_umax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_umin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_fmax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
def int_experimental_vector_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty]>;
}		}

//===----- Matrix intrinsics ---------------------------------------------===//		//===----- Matrix intrinsics ---------------------------------------------===//

def int_matrix_transpose		def int_matrix_transpose
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],		: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],		[LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
[ IntrNoSync, IntrWillReturn, IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>,		[ IntrNoSync, IntrWillReturn, IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>,
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines