diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -701,9 +701,6 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { // Keep track of regunit ranges. SmallVector, 8> RU; - // Keep track of subregister ranges. - SmallVector, 4> SRs; for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { Register Reg = Register::index2VirtReg(i); @@ -724,21 +721,15 @@ RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end))); } - if (MRI->subRegLivenessEnabled()) { - SRs.clear(); - for (const LiveInterval::SubRange &SR : LI.subranges()) { - SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end))); - } - } - // Every instruction that kills Reg corresponds to a segment range end // point. for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE; ++RI) { + SlotIndex InstrSI = RI->end; // A block index indicates an MBB edge. - if (RI->end.isBlock()) + if (InstrSI.isBlock()) continue; - MachineInstr *MI = getInstructionFromIndex(RI->end); + MachineInstr *MI = getInstructionFromIndex(InstrSI); if (!MI) continue; @@ -755,8 +746,8 @@ LiveRange::const_iterator &I = RUP.second; if (I == RURange.end()) continue; - I = RURange.advanceTo(I, RI->end); - if (I == RURange.end() || I->start >= RI->end) + I = RURange.advanceTo(I, InstrSI); + if (I == RURange.end() || I->start >= InstrSI) continue; // I is overlapping RI. goto CancelKill; @@ -775,20 +766,18 @@ // are actually never written by %2. After assignment the // flag at the read instruction is invalid. LaneBitmask DefinedLanesMask; - if (!SRs.empty()) { + if (LI.hasSubRanges()) { // Compute a mask of lanes that are defined. DefinedLanesMask = LaneBitmask::getNone(); - for (auto &SRP : SRs) { - const LiveInterval::SubRange &SR = *SRP.first; - LiveRange::const_iterator &I = SRP.second; - if (I == SR.end()) - continue; - I = SR.advanceTo(I, RI->end); - if (I == SR.end() || I->start >= RI->end) - continue; - // I is overlapping RI - DefinedLanesMask |= SR.LaneMask; - } + for (const LiveInterval::SubRange &SR : LI.subranges()) + for (const LiveRange::Segment &Segment: SR.segments) { + if (Segment.start >= InstrSI) + break; + if (Segment.end == InstrSI) { + DefinedLanesMask |= SR.LaneMask; + break; + } + } } else DefinedLanesMask = LaneBitmask::getAll(); @@ -799,6 +788,11 @@ if (MO.isUse()) { // Reading any undefined lanes? LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); + // If it is a full read, we try to retrieve the lane mask covering + // all the sub-registers from the register class. + if (MO.getSubReg() == 0) + if (const TargetRegisterClass *TRC = MRI->getRegClassOrNull(Reg)) + UseMask = TRC->getLaneMask(); if ((UseMask & ~DefinedLanesMask).any()) goto CancelKill; } else if (MO.getSubReg() == 0) { @@ -815,7 +809,7 @@ if (!IsFullWrite) { // Next segment has to be adjacent in the subregister write case. LiveRange::const_iterator N = std::next(RI); - if (N != LI.end() && N->start == RI->end) + if (N != LI.end() && N->start == InstrSI) goto CancelKill; } } diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll --- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll @@ -7303,8 +7303,7 @@ ; GCN-NOHSA-SI-NEXT: buffer_store_dword v20, off, s[12:15], 0 offset:24 ; 4-byte Folded Spill ; GCN-NOHSA-SI-NEXT: buffer_store_dword v21, off, s[12:15], 0 offset:28 ; 4-byte Folded Spill ; GCN-NOHSA-SI-NEXT: buffer_store_dword v22, off, s[12:15], 0 offset:32 ; 4-byte Folded Spill -; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(1) -; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v21, s0, v3 +; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s0, v3 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v32, 16, v5 ; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v30, s0, v5 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6 @@ -7345,7 +7344,6 @@ ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v41, v1 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v31, v1 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v33, v1 -; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, v21 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, v23 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, v1 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, v1 diff --git a/llvm/test/CodeGen/AMDGPU/regbank-reassign-wave64.mir b/llvm/test/CodeGen/AMDGPU/regbank-reassign-wave64.mir --- a/llvm/test/CodeGen/AMDGPU/regbank-reassign-wave64.mir +++ b/llvm/test/CodeGen/AMDGPU/regbank-reassign-wave64.mir @@ -22,7 +22,7 @@ # GCN: $vgpr44_vgpr45_vgpr46_vgpr47 = IMPLICIT_DEF # GCN: $vgpr2 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr5, $vcc, implicit $exec # GCN: $vgpr2 = V_CNDMASK_B32_e64 0, $vgpr0, 0, $vgpr4, killed $vcc, implicit $exec -# GCN: $sgpr0_sgpr1 = V_CMP_LT_U64_e64 $vgpr4_vgpr5, $vgpr0_vgpr1, implicit $exec +# GCN: $sgpr0_sgpr1 = V_CMP_LT_U64_e64 killed $vgpr4_vgpr5, killed $vgpr0_vgpr1, implicit $exec --- name: vgpr64_mixed_use tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir b/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir --- a/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir +++ b/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir @@ -367,7 +367,7 @@ # GCN-LABEL: vgpr_lo16_sub{{$}} # GCN: renamable $vgpr0 = V_AND_B32_e32 killed $vgpr3, killed $vgpr1, implicit $exec -# GCN: renamable $vgpr1_lo16 = COPY renamable $vgpr0_lo16 +# GCN: renamable $vgpr1_lo16 = COPY killed renamable $vgpr0_lo16 --- name: vgpr_lo16_sub tracksRegLiveness: true @@ -404,7 +404,7 @@ # GCN-LABEL: vgpr_hi16_sub{{$}} # GCN: renamable $vgpr0 = V_AND_B32_e32 killed $vgpr3, killed $vgpr1, implicit $exec -# GCN: renamable $vgpr1_hi16 = COPY renamable $vgpr0_hi16 +# GCN: renamable $vgpr1_hi16 = COPY killed renamable $vgpr0_hi16 --- name: vgpr_hi16_sub tracksRegLiveness: true @@ -441,7 +441,7 @@ # GCN-LABEL: sgpr_lo16_sub{{$}} # GCN: renamable $sgpr0 = S_AND_B32 killed renamable $sgpr14, $sgpr0, implicit-def $scc -# GCN: renamable $sgpr1_lo16 = COPY renamable $sgpr0_lo16 +# GCN: renamable $sgpr1_lo16 = COPY killed renamable $sgpr0_lo16 --- name: sgpr_lo16_sub tracksRegLiveness: true @@ -498,7 +498,7 @@ # Test that bank of subreg is considered during scavenging. # If handled incorrectly an infinite loop occurs. # GCN-LABEL: s0_vs_s15_16_17_sub1{{$}} -# GCN: S_AND_B32 renamable $sgpr13, $sgpr0, +# GCN: S_AND_B32 killed renamable $sgpr13, $sgpr0, --- name: s0_vs_s15_16_17_sub1 tracksRegLiveness: true @@ -531,7 +531,7 @@ # GCN: $vgpr40_vgpr41_vgpr42_vgpr43 = IMPLICIT_DEF # GCN: $vgpr44_vgpr45_vgpr46_vgpr47 = IMPLICIT_DEF # GCN: $vgpr0_vgpr1 = V_ADD_F64 0, $vgpr11_vgpr12, 0, killed $vgpr16_vgpr17, 0, 0, implicit $mode, implicit $exec -# GCN: $vgpr0_vgpr1 = V_ADD_F64 0, $vgpr9_vgpr10, 0, killed $vgpr14_vgpr15, 0, 0, implicit $mode, implicit $exec +# GCN: $vgpr0_vgpr1 = V_ADD_F64 0, killed $vgpr9_vgpr10, 0, killed $vgpr14_vgpr15, 0, 0, implicit $mode, implicit $exec --- name: vgpr_sub_dependence tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll --- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -17,7 +17,7 @@ ; GFX9-FLATSCR: s_mov_b32 [[SOFF1:s[0-9]+]], 4{{$}} ; GFX9-FLATSCR-DAG: scratch_store_dword off, v{{[0-9]+}}, [[SOFF1]] ; 4-byte Folded Spill ; GFX9-FLATSCR-DAG: scratch_store_dword off, v{{[0-9]+}}, [[SOFF1]] offset:{{[0-9]+}} ; 4-byte Folded Spill -; GFX9-FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x{{[0-9a-f]+}}{{$}} +; GFX9-FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x1{{[0-9a-f]+}}{{$}} ; GFX9-FLATSCR-DAG: scratch_load_dword v{{[0-9]+}}, off, [[SOFF2]] ; 4-byte Folded Reload ; GFX9-FLATSCR-DAG: scratch_load_dword v{{[0-9]+}}, off, [[SOFF2]] offset:{{[0-9]+}} ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir b/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir --- a/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir +++ b/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir @@ -19,7 +19,7 @@ ; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: renamable $sgpr0 = IMPLICIT_DEF ; CHECK: renamable $sgpr1 = IMPLICIT_DEF - ; CHECK: $sgpr104 = S_AND_B32 renamable $sgpr0, renamable $sgpr1, implicit-def $scc + ; CHECK: $sgpr104 = S_AND_B32 killed renamable $sgpr0, renamable $sgpr1, implicit-def $scc ; CHECK: KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99_sgpr100_sgpr101_sgpr102_sgpr103 ; CHECK: renamable $sgpr0_sgpr1 = IMPLICIT_DEF ; CHECK: renamable $sgpr0 = IMPLICIT_DEF @@ -27,7 +27,7 @@ ; CHECK: SI_SPILL_S64_SAVE renamable $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sp_reg :: (store 8 into %stack.0, align 4, addrspace 5) ; CHECK: KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99_sgpr100_sgpr101_sgpr102_sgpr103 ; CHECK: renamable $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load 8 from %stack.0, align 4, addrspace 5) - ; CHECK: $sgpr105 = S_AND_B32 renamable $sgpr1, renamable $sgpr1, implicit-def $scc + ; CHECK: $sgpr105 = S_AND_B32 killed renamable $sgpr1, renamable $sgpr1, implicit-def $scc ; CHECK: S_NOP 0, implicit $sgpr104, implicit $sgpr105 %0:sreg_64 = COPY $sgpr0_sgpr1 %0.sub0:sreg_64 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/splitkit.mir b/llvm/test/CodeGen/AMDGPU/splitkit.mir --- a/llvm/test/CodeGen/AMDGPU/splitkit.mir +++ b/llvm/test/CodeGen/AMDGPU/splitkit.mir @@ -39,11 +39,11 @@ # CHECK: S_NOP 0 # CHECK: S_NOP 0, implicit renamable [[REG0]] # CHECK: S_NOP 0, implicit renamable [[REG1]] -# CHECK: $sgpr0 = COPY renamable [[REG0]] +# CHECK: $sgpr0 = COPY killed renamable [[REG0]] # CHECK: $sgpr2 = COPY renamable [[REG1]] # CHECK: S_NOP # CHECK: S_NOP 0, implicit renamable $sgpr0 -# CHECK: S_NOP 0, implicit renamable $sgpr2 +# CHECK: S_NOP 0, implicit killed renamable $sgpr2 name: func1 tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/AMDGPU/subreg_interference.mir b/llvm/test/CodeGen/AMDGPU/subreg_interference.mir --- a/llvm/test/CodeGen/AMDGPU/subreg_interference.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg_interference.mir @@ -16,8 +16,8 @@ # CHECK: S_NOP 0, implicit-def renamable $sgpr3 # CHECK: S_NOP 0, implicit-def renamable $sgpr1 # CHECK: S_NOP 0, implicit-def renamable $sgpr2 -# CHECK: S_NOP 0, implicit renamable $sgpr0, implicit renamable $sgpr3 -# CHECK: S_NOP 0, implicit renamable $sgpr1, implicit renamable $sgpr2 +# CHECK: S_NOP 0, implicit killed renamable $sgpr0, implicit renamable $sgpr3 +# CHECK: S_NOP 0, implicit killed renamable $sgpr1, implicit renamable $sgpr2 name: func0 body: | bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir b/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir --- a/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir @@ -40,7 +40,7 @@ ; CHECK: $sgpr4 = COPY $sgpr95 ; CHECK: $vgpr0 = COPY renamable $vgpr40 ; CHECK: $vgpr1 = COPY renamable $vgpr41 - ; CHECK: $vgpr2 = COPY renamable $vgpr42 + ; CHECK: $vgpr2 = COPY killed renamable $vgpr42 ; CHECK: $vgpr3 = KILL undef renamable $vgpr3 ; CHECK: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @bar, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit killed $vgpr3, implicit-def $vgpr0 ; CHECK: ADJCALLSTACKDOWN 0, 4, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr95 diff --git a/llvm/test/CodeGen/PowerPC/subreg-killed.mir b/llvm/test/CodeGen/PowerPC/subreg-killed.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/subreg-killed.mir @@ -0,0 +1,134 @@ +# RUN: llc -mcpu=pwr10 -O3 -ppc-track-subreg-liveness -verify-machineinstrs \ +# RUN: -mtriple=powerpc64le-unknown-linux-gnu -run-pass=greedy,virtregrewriter \ +# RUN: -o - %s | FileCheck %s + +# CHECK-LABEL: test +# CHECK: KILL_PAIR killed +# CHECK-NEXT: COPY killed +# CHECK-NEXT: KILL_PAIR killed +# CHECK-NEXT: COPY killed +# CHECK-NEXT: BUILD_UACC killed +# CHECK-NEXT: XXMTACC killed +# CHECK-NEXT: SPILL_ACC killed + +--- | + declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) + + declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) + + declare void @foo() + + define void @test(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) { + %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4) + tail call void @foo() + %2 = bitcast i8* %ptr to <512 x i1>* + store <512 x i1> %1, <512 x i1>* %2, align 64 + ret void + } + +... +--- +name: test +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +registers: + - { id: 0, class: vrrc, preferred-register: '' } + - { id: 1, class: vrrc, preferred-register: '' } + - { id: 2, class: vrrc, preferred-register: '' } + - { id: 3, class: vrrc, preferred-register: '' } + - { id: 4, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 5, class: vsrprc_with_sub_64_in_vfrc, preferred-register: '' } + - { id: 6, class: vsrprc, preferred-register: '' } + - { id: 7, class: vsrprc_with_sub_64_in_vfrc, preferred-register: '' } + - { id: 8, class: vsrprc_with_sub_64_in_vfrc, preferred-register: '$vsrp17' } + - { id: 9, class: uaccrc, preferred-register: '' } + - { id: 10, class: uaccrc, preferred-register: '' } + - { id: 11, class: vsrprc_with_sub_64_in_vfrc, preferred-register: '' } + - { id: 12, class: vsrprc, preferred-register: '' } + - { id: 13, class: vsrprc_with_sub_64_in_vfrc, preferred-register: '' } + - { id: 14, class: vsrprc_with_sub_64_in_vfrc, preferred-register: '$vsrp18' } + - { id: 15, class: uaccrc, preferred-register: '' } + - { id: 16, class: accrc, preferred-register: '' } + - { id: 17, class: accrc, preferred-register: '' } + - { id: 18, class: accrc, preferred-register: '' } + - { id: 19, class: vsrc, preferred-register: '' } + - { id: 20, class: vsrc, preferred-register: '' } + - { id: 21, class: vsrprc, preferred-register: '' } + - { id: 22, class: vsrc, preferred-register: '' } + - { id: 23, class: vsrc, preferred-register: '' } + - { id: 24, class: accrc, preferred-register: '%25' } + - { id: 25, class: accrc, preferred-register: '%24' } + - { id: 26, class: accrc, preferred-register: '%25' } + - { id: 27, class: accrc, preferred-register: '%25' } + - { id: 28, class: accrc, preferred-register: '%27' } +liveins: + - { reg: '$v2', virtual-reg: '%0' } + - { reg: '$v3', virtual-reg: '%1' } + - { reg: '$v4', virtual-reg: '%2' } + - { reg: '$v5', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 16 + adjustsStack: false + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: + - { id: 0, type: default, offset: 96, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: '', type: spill-slot, offset: 0, size: 64, alignment: 16, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0 (%ir-block.0): + liveins: $v2, $v3, $v4, $v5 + + undef %14.sub_vsx1:vsrprc_with_sub_64_in_vfrc = COPY $v5 + %14.sub_vsx0:vsrprc_with_sub_64_in_vfrc = COPY $v4 + undef %8.sub_vsx1:vsrprc_with_sub_64_in_vfrc = COPY $v3 + %8.sub_vsx0:vsrprc_with_sub_64_in_vfrc = COPY $v2 + %4:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.0 :: (load 8 from %fixed-stack.0, align 16) + %8:vsrprc_with_sub_64_in_vfrc = KILL_PAIR %8 + undef %15.sub_pair0:uaccrc = COPY %8 + %14:vsrprc_with_sub_64_in_vfrc = KILL_PAIR %14 + %15.sub_pair1:uaccrc = COPY %14 + %28:accrc = BUILD_UACC %15 + %28:accrc = XXMTACC %28 + SPILL_ACC %28, 0, %stack.0 :: (store 64 into %stack.0, align 16) + ADJCALLSTACKDOWN 32, 0, implicit-def dead $r1, implicit $r1 + BL8_NOTOC @foo, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1 + %25:accrc = RESTORE_ACC 0, %stack.0 :: (load 64 from %stack.0, align 16) + %25:accrc = XXMFACC %25 + STXV %25.sub_vsx0, 48, %4 :: (store 16 into %ir.2 + 48) + STXV %25.sub_vsx1, 32, %4 :: (store 16 into %ir.2 + 32, align 32) + STXV %25.sub_pair1_then_sub_vsx0, 16, %4 :: (store 16 into %ir.2 + 16) + undef %26.sub_pair1_then_sub_vsx1:accrc = COPY %25.sub_pair1_then_sub_vsx1 + STXVX %26.sub_pair1_then_sub_vsx1, $zero8, %4 :: (store 16 into %ir.2, align 64) + BLR8 implicit $lr8, implicit $rm + +...