diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -418,6 +418,9 @@
 def FeatureCSRE : SubtargetFeature<"csre", "HasCSRE",
     "true", "Enable Call Stack Recorder Extension">;
 
+def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
+    "true", "Enable extra register in the Statistical Profiling Extension">;
+
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension">;
 
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -161,6 +161,8 @@
                        AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
 def HasCSRE          : Predicate<"Subtarget->hasCSRE()">,
                        AssemblerPredicate<(all_of FeatureCSRE), "csre">;
+def HasSPE_EEF       : Predicate<"Subtarget->hasSPE_EEF()">,
+                       AssemblerPredicate<(all_of FeatureSPE_EEF), "spe-eef">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -186,6 +186,7 @@
   bool HasTRBE = false;
   bool HasBRBE = false;
   bool HasCSRE = false;
+  bool HasSPE_EEF = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1609,6 +1609,10 @@
 def : RWSysReg<"CSRPTR_EL2",        0b10, 0b100, 0b1000, 0b0000, 0b001>;
 }
 
+// Statistical Profiling Extension system register
+let Requires = [{ {AArch64::FeatureSPE_EEF} }] in
+def : RWSysReg<"PMSNEVFR_EL1",      0b11, 0b000, 0b1001, 0b1001, 0b001>;
+
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcAppleA7} }] in
diff --git a/llvm/test/MC/AArch64/spe.s b/llvm/test/MC/AArch64/spe.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/spe.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s
+
+msr PMSNEVFR_EL1, x0
+mrs x1, PMSNEVFR_EL1
+// CHECK: msr     PMSNEVFR_EL1, x0        // encoding: [0x20,0x99,0x18,0xd5]
+// CHECK: mrs     x1, PMSNEVFR_EL1        // encoding: [0x21,0x99,0x38,0xd5]