diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1030,7 +1030,7 @@ /// Returns the physical register number of sub-register "Index" /// for physical register RegNo. Return zero if the sub-register does not /// exist. - inline Register getSubReg(MCRegister Reg, unsigned Idx) const { + inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const { return static_cast(this)->getSubReg(Reg, Idx); } }; diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp --- a/llvm/lib/CodeGen/CalcSpillWeights.cpp +++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp @@ -64,7 +64,7 @@ return Sub == HSub ? HReg : Register(); const TargetRegisterClass *rc = MRI.getRegClass(Reg); - Register CopiedPReg = (HSub ? TRI.getSubReg(HReg, HSub) : HReg); + MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); if (rc->contains(CopiedPReg)) return CopiedPReg; diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -950,7 +950,7 @@ } // Handle subregister index. - MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register()); + MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); MO.setIsRenamable(true); // Note: We leave the subreg number around a little longer in case of defs. // This is so that the register freeing logic in allocateInstruction can still diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -538,8 +538,8 @@ } // Now check that Dst matches DstReg. - if (Register::isPhysicalRegister(DstReg)) { - if (!Register::isPhysicalRegister(Dst)) + if (DstReg.isPhysical()) { + if (!Dst.isPhysical()) return false; assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); // DstSub could be set for a physreg from INSERT_SUBREG. @@ -549,7 +549,7 @@ if (!SrcSub) return DstReg == Dst; // This is a partial register copy. Check that the parts match. - return TRI.getSubReg(DstReg, SrcSub) == Dst; + return Register(TRI.getSubReg(DstReg, SrcSub)) == Dst; } else { // DstReg is virtual. if (DstReg != Dst) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -840,9 +840,10 @@ // FIXME: Flat scratch does not have to be limited to a dword per store. for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) { - Register SubReg = NumSubRegs == 1 - ? Register(ValueReg) - : getSubReg(ValueReg, getSubRegFromChannel(i)); + Register SubReg = + NumSubRegs == 1 + ? ValueReg + : Register(getSubReg(ValueReg, getSubRegFromChannel(i))); unsigned SOffsetRegState = 0; unsigned SrcDstRegState = getDefRegState(!IsStore); @@ -968,9 +969,10 @@ // Backup EXEC if (OnlyExecLo) { - SavedExecReg = NumSubRegs == 1 - ? SuperReg - : getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]); + SavedExecReg = + NumSubRegs == 1 + ? SuperReg + : Register(getSubReg(SuperReg, SplitParts[FirstPart + ExecLane])); } else { // If src/dst is an odd size it is possible subreg0 is not aligned. for (; ExecLane < (NumSubRegs - 1); ++ExecLane) { @@ -1037,9 +1039,9 @@ .addImm(ExecLane + 1); } BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), - NumSubRegs == 1 - ? SavedExecReg - : getSubReg(SuperReg, SplitParts[FirstPart + ExecLane])) + NumSubRegs == 1 ? SavedExecReg + : Register(getSubReg( + SuperReg, SplitParts[FirstPart + ExecLane]))) .addReg(VGPR, RegState::Kill) .addImm(ExecLane); } @@ -1081,8 +1083,9 @@ if (SpillToVGPR) { for (unsigned i = 0, e = NumSubRegs; i < e; ++i) { - Register SubReg = - NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]); + Register SubReg = NumSubRegs == 1 + ? SuperReg + : Register(getSubReg(SuperReg, SplitParts[i])); SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; bool UseKill = IsKill && i == NumSubRegs - 1; @@ -1135,8 +1138,9 @@ for (unsigned i = Offset * PerVGPR, e = std::min((Offset + 1) * PerVGPR, NumSubRegs); i < e; ++i) { - Register SubReg = - NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]); + Register SubReg = NumSubRegs == 1 + ? SuperReg + : Register(getSubReg(SuperReg, SplitParts[i])); MachineInstrBuilder WriteLane = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), TmpVGPR) @@ -1199,8 +1203,9 @@ if (SpillToVGPR) { for (unsigned i = 0, e = NumSubRegs; i < e; ++i) { - Register SubReg = - NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]); + Register SubReg = NumSubRegs == 1 + ? SuperReg + : Register(getSubReg(SuperReg, SplitParts[i])); SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; auto MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg) @@ -1226,8 +1231,9 @@ for (unsigned i = Offset * PerVGPR, e = std::min((Offset + 1) * PerVGPR, NumSubRegs); i < e; ++i) { - Register SubReg = - NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]); + Register SubReg = NumSubRegs == 1 + ? SuperReg + : Register(getSubReg(SuperReg, SplitParts[i])); bool LastSubReg = (i + 1 == e); auto MIB = diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -285,7 +285,7 @@ return false; case 'y': // Print a VFP single precision register as indexed double. if (MI->getOperand(OpNum).isReg()) { - Register Reg = MI->getOperand(OpNum).getReg(); + MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); // Find the 'd' register that has this 's' register as a sub-register, // and determine the lane number. diff --git a/llvm/lib/Target/Hexagon/BitTracker.h b/llvm/lib/Target/Hexagon/BitTracker.h --- a/llvm/lib/Target/Hexagon/BitTracker.h +++ b/llvm/lib/Target/Hexagon/BitTracker.h @@ -485,7 +485,7 @@ llvm_unreachable("Unimplemented composeWithSubRegIndex"); } // Return the size in bits of the physical register Reg. - virtual uint16_t getPhysRegBitWidth(Register Reg) const; + virtual uint16_t getPhysRegBitWidth(MCRegister Reg) const; const TargetRegisterInfo &TRI; MachineRegisterInfo &MRI; diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -340,8 +340,8 @@ return TRI.getRegSizeInBits(VC); } assert(RR.Reg.isPhysical()); - Register PhysR = - (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); + MCRegister PhysR = + (RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub); return getPhysRegBitWidth(PhysR); } @@ -711,8 +711,7 @@ return BitMask(0, W-1); } -uint16_t BT::MachineEvaluator::getPhysRegBitWidth(Register Reg) const { - assert(Reg.isPhysical()); +uint16_t BT::MachineEvaluator::getPhysRegBitWidth(MCRegister Reg) const { const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg); return TRI.getRegSizeInBits(PC); } diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.h b/llvm/lib/Target/Hexagon/HexagonBitTracker.h --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.h +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.h @@ -38,7 +38,7 @@ BitTracker::BitMask mask(Register Reg, unsigned Sub) const override; - uint16_t getPhysRegBitWidth(Register Reg) const override; + uint16_t getPhysRegBitWidth(MCRegister Reg) const override; const TargetRegisterClass &composeWithSubRegIndex( const TargetRegisterClass &RC, unsigned Idx) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -110,9 +110,7 @@ llvm_unreachable("Unexpected register/subregister"); } -uint16_t HexagonEvaluator::getPhysRegBitWidth(Register Reg) const { - assert(Reg.isPhysical()); - +uint16_t HexagonEvaluator::getPhysRegBitWidth(MCRegister Reg) const { using namespace Hexagon; const auto &HST = MF.getSubtarget(); if (HST.useHVXOps()) { diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -582,17 +582,16 @@ using namespace Hexagon; if (SO.isReg()) { - Register PhysR; + MCRegister PhysR; RegisterRef RS = SO; if (RS.Reg.isVirtual()) { const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg); assert(VC->begin() != VC->end() && "Empty register class"); PhysR = *VC->begin(); } else { - assert(Register::isPhysicalRegister(RS.Reg)); PhysR = RS.Reg; } - Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); + MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); switch (TRI->getRegSizeInBits(*RC)) { case 32: diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp --- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp @@ -733,10 +733,10 @@ assert(I->getNumOperands() == 5 && "Atomics min|max|umin|umax use an additional register"); - Register Scratch2 = I->getOperand(4).getReg(); + MCRegister Scratch2 = I->getOperand(4).getReg().asMCReg(); // On Mips64 result of slt is GPR32. - Register Scratch2_32 = + MCRegister Scratch2_32 = (Size == 8) ? STI->getRegisterInfo()->getSubReg(Scratch2, Mips::sub_32) : Scratch2;