diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst --- a/clang/docs/ClangCommandLineReference.rst +++ b/clang/docs/ClangCommandLineReference.rst @@ -3169,8 +3169,6 @@ .. option:: -mpower9-vector, -mno-power9-vector -.. option:: -mqpx, -mno-qpx - .. option:: -msecure-plt .. option:: -mspe, -mno-spe diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2639,8 +2639,6 @@ def mno_mfcrf : Flag<["-"], "mno-mfcrf">, Alias; def mpopcntd : Flag<["-"], "mpopcntd">, Group; def mno_popcntd : Flag<["-"], "mno-popcntd">, Group; -def mqpx : Flag<["-"], "mqpx">, Group; -def mno_qpx : Flag<["-"], "mno-qpx">, Group; def mcrbits : Flag<["-"], "mcrbits">, Group; def mno_crbits : Flag<["-"], "mno-crbits">, Group; def minvariant_function_descriptors : diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -2360,12 +2360,6 @@ unsigned ASTContext::getOpenMPDefaultSimdAlign(QualType T) const { unsigned SimdAlign = getTargetInfo().getSimdDefaultAlign(); - // Target ppc64 with QPX: simd default alignment for pointer to double is 32. - if ((getTargetInfo().getTriple().getArch() == llvm::Triple::ppc64 || - getTargetInfo().getTriple().getArch() == llvm::Triple::ppc64le) && - getTargetInfo().getABI() == "elfv1-qpx" && - T->isSpecificBuiltinType(BuiltinType::Double)) - SimdAlign = 256; return SimdAlign; } diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -438,7 +438,7 @@ // PPC64 Linux-specific ABI options. bool setABI(const std::string &Name) override { - if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { + if (Name == "elfv1" || Name == "elfv2") { ABI = Name; return true; } diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -4885,42 +4885,12 @@ private: static const unsigned GPRBits = 64; ABIKind Kind; - bool HasQPX; bool IsSoftFloatABI; - // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and - // will be passed in a QPX register. - bool IsQPXVectorTy(const Type *Ty) const { - if (!HasQPX) - return false; - - if (const VectorType *VT = Ty->getAs()) { - unsigned NumElements = VT->getNumElements(); - if (NumElements == 1) - return false; - - if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) { - if (getContext().getTypeSize(Ty) <= 256) - return true; - } else if (VT->getElementType()-> - isSpecificBuiltinType(BuiltinType::Float)) { - if (getContext().getTypeSize(Ty) <= 128) - return true; - } - } - - return false; - } - - bool IsQPXVectorTy(QualType Ty) const { - return IsQPXVectorTy(Ty.getTypePtr()); - } - public: - PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX, + PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool SoftFloatABI) - : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX), - IsSoftFloatABI(SoftFloatABI) {} + : SwiftABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {} bool isPromotableTypeForABI(QualType Ty) const; CharUnits getParamTypeAlignment(QualType Ty) const; @@ -4948,8 +4918,7 @@ const Type *T = isSingleElementStruct(I.type, getContext()); if (T) { const BuiltinType *BT = T->getAs(); - if (IsQPXVectorTy(T) || - (T->isVectorType() && getContext().getTypeSize(T) == 128) || + if ((T->isVectorType() && getContext().getTypeSize(T) == 128) || (BT && BT->isFloatingPoint())) { QualType QT(T, 0); I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT)); @@ -4977,10 +4946,10 @@ public: PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT, - PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX, + PPC64_SVR4_ABIInfo::ABIKind Kind, bool SoftFloatABI) - : TargetCodeGenInfo(std::make_unique( - CGT, Kind, HasQPX, SoftFloatABI)) {} + : TargetCodeGenInfo( + std::make_unique(CGT, Kind, SoftFloatABI)) {} int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { // This is recovered from gcc output. @@ -5045,12 +5014,7 @@ // Only vector types of size 16 bytes need alignment (larger types are // passed via reference, smaller types are not aligned). - if (IsQPXVectorTy(Ty)) { - if (getContext().getTypeSize(Ty) > 128) - return CharUnits::fromQuantity(32); - - return CharUnits::fromQuantity(16); - } else if (Ty->isVectorType()) { + if (Ty->isVectorType()) { return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8); } else if (Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(Ty) == @@ -5067,8 +5031,7 @@ const Type *EltType = isSingleElementStruct(Ty, getContext()); if (EltType) { const BuiltinType *BT = EltType->getAs(); - if (IsQPXVectorTy(EltType) || (EltType->isVectorType() && - getContext().getTypeSize(EltType) == 128) || + if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) || (BT && BT->isFloatingPoint())) AlignAsType = EltType; } @@ -5081,20 +5044,13 @@ AlignAsType = Base; // With special case aggregates, only vector base types need alignment. - if (AlignAsType && IsQPXVectorTy(AlignAsType)) { - if (getContext().getTypeSize(AlignAsType) > 128) - return CharUnits::fromQuantity(32); - - return CharUnits::fromQuantity(16); - } else if (AlignAsType) { + if (AlignAsType) { return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8); } // Otherwise, we only need alignment for any aggregate type that // has an alignment requirement of >= 16 bytes. if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) { - if (HasQPX && getContext().getTypeAlign(Ty) >= 256) - return CharUnits::fromQuantity(32); return CharUnits::fromQuantity(16); } @@ -5218,7 +5174,7 @@ } } if (const VectorType *VT = Ty->getAs()) { - if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty)) + if (getContext().getTypeSize(VT) == 128) return true; } return false; @@ -5247,7 +5203,7 @@ // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes) // or via reference (larger than 16 bytes). - if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) { + if (Ty->isVectorType()) { uint64_t Size = getContext().getTypeSize(Ty); if (Size > 128) return getNaturalAlignIndirect(Ty, /*ByVal=*/false); @@ -5323,7 +5279,7 @@ // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes) // or via reference (larger than 16 bytes). - if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) { + if (RetTy->isVectorType()) { uint64_t Size = getContext().getTypeSize(RetTy); if (Size > 128) return getNaturalAlignIndirect(RetTy); @@ -10963,23 +10919,21 @@ PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1; if (getTarget().getABI() == "elfv2") Kind = PPC64_SVR4_ABIInfo::ELFv2; - bool HasQPX = getTarget().getABI() == "elfv1-qpx"; bool IsSoftFloat = CodeGenOpts.FloatABI == "soft"; - return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX, - IsSoftFloat)); + return SetCGInfo( + new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, IsSoftFloat)); } return SetCGInfo(new PPC64TargetCodeGenInfo(Types)); case llvm::Triple::ppc64le: { assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!"); PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2; - if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx") + if (getTarget().getABI() == "elfv1") Kind = PPC64_SVR4_ABIInfo::ELFv1; - bool HasQPX = getTarget().getABI() == "elfv1-qpx"; bool IsSoftFloat = CodeGenOpts.FloatABI == "soft"; - return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX, - IsSoftFloat)); + return SetCGInfo( + new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, IsSoftFloat)); } case llvm::Triple::nvptx: diff --git a/clang/test/CodeGen/ppc64-elf-abi.c b/clang/test/CodeGen/ppc64-elf-abi.c --- a/clang/test/CodeGen/ppc64-elf-abi.c +++ b/clang/test/CodeGen/ppc64-elf-abi.c @@ -7,8 +7,6 @@ // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: -target-abi elfv1 | FileCheck %s --check-prefix=CHECK-ELFv1 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s \ -// RUN: -target-abi elfv1-qpx | FileCheck %s --check-prefix=CHECK-ELFv1 -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: -target-abi elfv2 | FileCheck %s --check-prefix=CHECK-ELFv2 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: | FileCheck %s --check-prefix=CHECK-ELFv2 diff --git a/clang/test/CodeGen/ppc64-qpx-vector.c b/clang/test/CodeGen/ppc64-qpx-vector.c deleted file mode 100644 --- a/clang/test/CodeGen/ppc64-qpx-vector.c +++ /dev/null @@ -1,29 +0,0 @@ -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=ALL -check-prefix=NORMAL -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - -target-abi elfv1-qpx %s | FileCheck %s -check-prefix=ALL -check-prefix=QPX - -typedef float v4sf __attribute__((vector_size(16))); -typedef double v4df __attribute__((vector_size(32))); - -struct ssf { v4sf v; }; -struct sdf { v4df v; }; - -struct ssf2 { v4sf v[2]; }; -struct sdf2 { v4df v[2]; }; - -v4sf foo1(struct ssf a, v4sf b, struct ssf2 c) { - return a.v + b; -} - -// ALL-LABEL: define <4 x float> @foo1(<4 x float> inreg %a.coerce, <4 x float> %b, [2 x i128] %c.coerce) -// ALL: ret <4 x float> - -v4df foo2(struct sdf a, v4df b, struct sdf2 c) { - return a.v + b; -} - -// QPX-LABEL: define <4 x double> @foo2(<4 x double> inreg %a.coerce, <4 x double> %b, [2 x i256] %c.coerce) -// QPX: ret <4 x double> - -// NORMAL-LABEL: define void @foo2(<4 x double>* noalias sret(<4 x double>) align 32 %agg.result, [2 x i128] %a.coerce, <4 x double>* %0, [4 x i128] %c.coerce) -// NORMAL: ret void - diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -941,9 +941,6 @@ // RUN: %clang %s -### -o %t.o 2>&1 \ // RUN: --target=powerpc64-linux-gnu -mabi=elfv1 \ // RUN: | FileCheck --check-prefix=CHECK-PPC64-ELFv1 %s -// RUN: %clang %s -### -o %t.o 2>&1 \ -// RUN: --target=powerpc64-linux-gnu -mabi=elfv1-qpx \ -// RUN: | FileCheck --check-prefix=CHECK-PPC64-ELFv1 %s // CHECK-PPC64-ELFv1: "{{.*}}ld{{(.exe)?}}" // CHECK-PPC64-ELFv1: "-m" "elf64ppc" // CHECK-PPC64-ELFv1: "-dynamic-linker" "{{.*}}/lib{{(64)?}}/ld64.so.1" diff --git a/clang/test/Driver/ppc-features.cpp b/clang/test/Driver/ppc-features.cpp --- a/clang/test/Driver/ppc-features.cpp +++ b/clang/test/Driver/ppc-features.cpp @@ -69,12 +69,6 @@ // RUN: %clang -### -c -target powerpc64-unknown-linux-gnu %s -maltivec -mno-altivec 2>&1 | FileCheck --check-prefix=NO_ALTIVEC %s // NO_ALTIVEC: "-target-feature" "-altivec" -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-qpx -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOQPX %s -// CHECK-NOQPX: "-target-feature" "-qpx" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-qpx -mqpx -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-QPX %s -// CHECK-QPX-NOT: "-target-feature" "-qpx" - // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-mfcrf -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOMFCRF %s // CHECK-NOMFCRF: "-target-feature" "-mfocrf" diff --git a/clang/test/OpenMP/simd_metadata.c b/clang/test/OpenMP/simd_metadata.c --- a/clang/test/OpenMP/simd_metadata.c +++ b/clang/test/OpenMP/simd_metadata.c @@ -5,7 +5,6 @@ // RUN: %clang_cc1 -fopenmp -triple i386-unknown-unknown -target-feature +avx -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=X86-AVX // RUN: %clang_cc1 -fopenmp -triple i386-unknown-unknown -target-feature +avx512f -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=X86-AVX512 // RUN: %clang_cc1 -fopenmp -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=PPC -// RUN: %clang_cc1 -fopenmp -triple powerpc64-unknown-unknown -target-abi elfv1-qpx -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=PPC-QPX // RUN: %clang_cc1 -fopenmp-simd -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=X86 // RUN: %clang_cc1 -fopenmp-simd -triple x86_64-unknown-unknown -target-feature +avx -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=X86-AVX @@ -14,7 +13,6 @@ // RUN: %clang_cc1 -fopenmp-simd -triple i386-unknown-unknown -target-feature +avx -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=X86-AVX // RUN: %clang_cc1 -fopenmp-simd -triple i386-unknown-unknown -target-feature +avx512f -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=X86-AVX512 // RUN: %clang_cc1 -fopenmp-simd -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=PPC -// RUN: %clang_cc1 -fopenmp-simd -triple powerpc64-unknown-unknown -target-abi elfv1-qpx -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=PPC-QPX void h1(float *c, float *a, double b[], int size) { @@ -28,14 +26,12 @@ // X86-AVX-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 32) ] // X86-AVX512-NEXT:call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 64) ] // PPC-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 16) ] - // PPC-QPX-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 16) ] // CHECK-NEXT: load // X86-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 16) ] // X86-AVX-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 32) ] // X86-AVX512-NEXT:call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 64) ] // PPC-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 16) ] - // PPC-QPX-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 32) ] for (int i = 0; i < size; ++i) { c[i] = a[i] * a[i] + b[i] * b[t]; ++t; @@ -50,14 +46,12 @@ // X86-AVX-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 32) ] // X86-AVX512-NEXT:call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 64) ] // PPC-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 16) ] - // PPC-QPX-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 16) ] // CHECK-NEXT: load // X86-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 16) ] // X86-AVX-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 32) ] // X86-AVX512-NEXT:call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 64) ] // PPC-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 16) ] - // PPC-QPX-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 32) ] for (int i = 0; i < size; ++i) { c[i] = a[i] * a[i] + b[i] * b[t]; ++t; @@ -72,14 +66,12 @@ // X86-AVX-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 32) ] // X86-AVX512-NEXT:call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 64) ] // PPC-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 16) ] - // PPC-QPX-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[PTR5:%.*]], {{i64|i32}} 16) ] // CHECK-NEXT: load // X86-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 16) ] // X86-AVX-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 32) ] // X86-AVX512-NEXT:call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 64) ] // PPC-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 16) ] - // PPC-QPX-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[PTR6:%.*]], {{i64|i32}} 32) ] for (int i = 0; i < size; ++i) { c[i] = a[i] * a[i] + b[i] * b[t]; ++t; diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-only-for-real.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-only-for-real.ll --- a/llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-only-for-real.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-only-for-real.ll @@ -55,8 +55,8 @@ declare signext i32 @bar(i32*, i32*) #2 -attributes #0 = { nounwind "target-cpu"="a2q" "target-features"="+qpx,-altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" } +attributes #0 = { nounwind "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" } attributes #1 = { argmemonly nounwind } -attributes #2 = { "target-cpu"="a2q" "target-features"="+qpx,-altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" } +attributes #2 = { "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" } attributes #3 = { nounwind }