diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -526,26 +526,25 @@
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
+
+// The first IBM designed processor with Altivec was the PPC970 aka G5,
+// but that did not appear in any IBM systems. While VMX/Altivec was added in
+// ISA 2.03 (pwr4), the extension was optional. The first IBM processor with
+// Altivec implemented in an IBM Power system was Power6.
 def : ProcessorModel<"pwr3", G5Model,
-                  [DirectivePwr3, FeatureAltivec,
-                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
+                  [DirectivePwr3, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
                    FeatureSTFIWX, Feature64Bit]>;
 def : ProcessorModel<"pwr4", G5Model,
-                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
-                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
-                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
+                  [DirectivePwr4, FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
+                   FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 def : ProcessorModel<"pwr5", G5Model,
-                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
-                   FeatureFSqrt, FeatureFRE, FeatureFRES,
-                   FeatureFRSQRTE, FeatureFRSQRTES,
-                   FeatureSTFIWX, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                  [DirectivePwr5, FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
+                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX,
+                   Feature64Bit, FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr5x", G5Model,
-                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
-                   FeatureFSqrt, FeatureFRE, FeatureFRES,
-                   FeatureFRSQRTE, FeatureFRSQRTES,
-                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                  [DirectivePwr5x, FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
+                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX,
+                   FeatureFPRND, Feature64Bit, FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr6", G5Model,
                   [DirectivePwr6, FeatureAltivec,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
diff --git a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
--- a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
 @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }]
diff --git a/llvm/test/CodeGen/PowerPC/aix-func-align.ll b/llvm/test/CodeGen/PowerPC/aix-func-align.ll
--- a/llvm/test/CodeGen/PowerPC/aix-func-align.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-align.ll
@@ -1,9 +1,9 @@
 ; This test tries to verify if a csect containing code would have the correct alignment.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
diff --git a/llvm/test/CodeGen/PowerPC/aix-internal.ll b/llvm/test/CodeGen/PowerPC/aix-internal.ll
--- a/llvm/test/CodeGen/PowerPC/aix-internal.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-internal.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 \
 ; RUN: -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck %s
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
diff --git a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
--- a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN:     -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
 
 @foo_ptr = global void (...)* @foo
diff --git a/llvm/test/CodeGen/PowerPC/aix-return55.ll b/llvm/test/CodeGen/PowerPC/aix-return55.ll
--- a/llvm/test/CodeGen/PowerPC/aix-return55.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-return55.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
-; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
@@ -1,26 +1,26 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
@@ -1,10 +1,10 @@
 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
@@ -3,12 +3,12 @@
 ; the test in this file should be merged into aix-xcoff-data.ll with additional
 ; tests for XCOFF object files.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
-; RUN:     -mtriple powerpc-ibm-aix-xcoff  -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
-; RUN:     -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4  -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -data-sections=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -data-sections=false < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 
 @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -filetype=obj -code-model=large -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
@@ -1,12 +1,12 @@
 ; This file tests TOC entry generation and undefined symbol generation.
 
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 
-; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
+; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
 ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
diff --git a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
--- a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK
+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN:     -run-pass=prologepilog --verify-machineinstrs < %s | \
+# RUN:   FileCheck %s --check-prefixes=CHECK
 
 ---
 name:            CRMultiSave
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
--- a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
-; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN:     -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
 ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 
 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
--- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -7,7 +7,7 @@
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
diff --git a/llvm/test/CodeGen/PowerPC/pwr4-altivec.ll b/llvm/test/CodeGen/PowerPC/pwr4-altivec.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pwr4-altivec.ll
@@ -0,0 +1,183 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr4 < %s | FileCheck %s
+
+define <16 x i8> @default(<16 x i8> %0) {
+; CHECK-LABEL: default:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    std 29, -24(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 29, 7, -1
+; CHECK-NEXT:    addi 12, 4, -1
+; CHECK-NEXT:    and 7, 7, 29
+; CHECK-NEXT:    and 4, 4, 12
+; CHECK-NEXT:    lbz 29, 127(1)
+; CHECK-NEXT:    addi 0, 5, -1
+; CHECK-NEXT:    clrlwi 7, 7, 24
+; CHECK-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 30, 6, -1
+; CHECK-NEXT:    and 5, 5, 0
+; CHECK-NEXT:    and 6, 6, 30
+; CHECK-NEXT:    clrlwi 5, 5, 24
+; CHECK-NEXT:    lbz 11, 143(1)
+; CHECK-NEXT:    clrlwi 6, 6, 24
+; CHECK-NEXT:    cntlzw 5, 5
+; CHECK-NEXT:    lbz 12, 135(1)
+; CHECK-NEXT:    cntlzw 6, 6
+; CHECK-NEXT:    srwi 5, 5, 5
+; CHECK-NEXT:    srwi 6, 6, 5
+; CHECK-NEXT:    cntlzw 7, 7
+; CHECK-NEXT:    std 24, -64(1) # 8-byte Folded Spill
+; CHECK-NEXT:    xori 6, 6, 1
+; CHECK-NEXT:    xori 5, 5, 1
+; CHECK-NEXT:    std 27, -40(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 27, 9, -1
+; CHECK-NEXT:    neg 6, 6
+; CHECK-NEXT:    and 9, 9, 27
+; CHECK-NEXT:    addi 27, 29, -1
+; CHECK-NEXT:    std 28, -32(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 28, 8, -1
+; CHECK-NEXT:    and 29, 29, 27
+; CHECK-NEXT:    lbz 30, 119(1)
+; CHECK-NEXT:    and 8, 8, 28
+; CHECK-NEXT:    clrlwi 9, 9, 24
+; CHECK-NEXT:    clrlwi 8, 8, 24
+; CHECK-NEXT:    srwi 7, 7, 5
+; CHECK-NEXT:    lbz 24, 159(1)
+; CHECK-NEXT:    addi 0, 30, -1
+; CHECK-NEXT:    cntlzw 8, 8
+; CHECK-NEXT:    std 26, -48(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 26, 10, -1
+; CHECK-NEXT:    and 0, 30, 0
+; CHECK-NEXT:    and 10, 10, 26
+; CHECK-NEXT:    addi 26, 12, -1
+; CHECK-NEXT:    lbz 28, 151(1)
+; CHECK-NEXT:    and 12, 12, 26
+; CHECK-NEXT:    addi 26, 24, -1
+; CHECK-NEXT:    std 25, -56(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 25, 11, -1
+; CHECK-NEXT:    addi 30, 28, -1
+; CHECK-NEXT:    and 11, 11, 25
+; CHECK-NEXT:    and 26, 24, 26
+; CHECK-NEXT:    lbz 27, 167(1)
+; CHECK-NEXT:    and 30, 28, 30
+; CHECK-NEXT:    srwi 8, 8, 5
+; CHECK-NEXT:    lbz 25, 175(1)
+; CHECK-NEXT:    addi 28, 27, -1
+; CHECK-NEXT:    xori 8, 8, 1
+; CHECK-NEXT:    and 28, 27, 28
+; CHECK-NEXT:    clrlwi 30, 30, 24
+; CHECK-NEXT:    lbz 24, 183(1)
+; CHECK-NEXT:    addi 27, 25, -1
+; CHECK-NEXT:    neg 8, 8
+; CHECK-NEXT:    and 27, 25, 27
+; CHECK-NEXT:    addi 25, 24, -1
+; CHECK-NEXT:    stb 6, 2(3)
+; CHECK-NEXT:    and 25, 24, 25
+; CHECK-NEXT:    clrlwi 27, 27, 24
+; CHECK-NEXT:    stb 8, 4(3)
+; CHECK-NEXT:    clrlwi 25, 25, 24
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    cntlzw 6, 25
+; CHECK-NEXT:    cntlzw 9, 9
+; CHECK-NEXT:    stb 5, 1(3)
+; CHECK-NEXT:    srwi 6, 6, 5
+; CHECK-NEXT:    xori 7, 7, 1
+; CHECK-NEXT:    cntlzw 8, 30
+; CHECK-NEXT:    cntlzw 30, 27
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 9, 9, 5
+; CHECK-NEXT:    clrlwi 28, 28, 24
+; CHECK-NEXT:    neg 7, 7
+; CHECK-NEXT:    stb 7, 3(3)
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 30, 5
+; CHECK-NEXT:    xori 9, 9, 1
+; CHECK-NEXT:    cntlzw 7, 28
+; CHECK-NEXT:    stb 5, 15(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 12, 12, 24
+; CHECK-NEXT:    clrlwi 26, 26, 24
+; CHECK-NEXT:    neg 9, 9
+; CHECK-NEXT:    stb 9, 5(3)
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 7, 5
+; CHECK-NEXT:    cntlzw 9, 12
+; CHECK-NEXT:    cntlzw 12, 26
+; CHECK-NEXT:    stb 5, 14(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 6, 12, 5
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    clrlwi 10, 10, 24
+; CHECK-NEXT:    stb 5, 13(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 11, 11, 24
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 8, 5
+; CHECK-NEXT:    stb 5, 12(3)
+; CHECK-NEXT:    cntlzw 10, 10
+; CHECK-NEXT:    cntlzw 11, 11
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 10, 10, 5
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 11, 5
+; CHECK-NEXT:    stb 5, 11(3)
+; CHECK-NEXT:    xori 10, 10, 1
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 0, 0, 24
+; CHECK-NEXT:    clrlwi 29, 29, 24
+; CHECK-NEXT:    neg 10, 10
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    stb 10, 6(3)
+; CHECK-NEXT:    srwi 6, 9, 5
+; CHECK-NEXT:    cntlzw 10, 0
+; CHECK-NEXT:    cntlzw 0, 29
+; CHECK-NEXT:    stb 5, 10(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 4, 4, 24
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    stb 5, 9(3)
+; CHECK-NEXT:    srwi 6, 0, 5
+; CHECK-NEXT:    cntlzw 4, 4
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 6, 10, 5
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 4, 4, 5
+; CHECK-NEXT:    stb 5, 8(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    xori 4, 4, 1
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    neg 4, 4
+; CHECK-NEXT:    stb 5, 7(3)
+; CHECK-NEXT:    stb 4, 0(3)
+; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 24, -64(1) # 8-byte Folded Reload
+; CHECK-NEXT:    blr
+  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+  %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %4 = sext <16 x i1> %3 to <16 x i8>
+  ret <16 x i8> %4
+}
+
+define <16 x i8> @altivec_enabled(<16 x i8> %0) #0 {
+; CHECK-LABEL: altivec_enabled:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisb 3, -1
+; CHECK-NEXT:    vaddubm 3, 2, 3
+; CHECK-NEXT:    vand 2, 2, 3
+; CHECK-NEXT:    vxor 3, 3, 3
+; CHECK-NEXT:    vcmpequb 2, 2, 3
+; CHECK-NEXT:    vnot 2, 2
+; CHECK-NEXT:    blr
+  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+  %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %4 = sext <16 x i1> %3 to <16 x i8>
+  ret <16 x i8> %4
+}
+
+declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
+
+attributes #0 = { norecurse nounwind readnone "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-power8-vector,-power9-vector,-spe,-vsx" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
--- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR5
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 -mattr=+altivec < %s | FileCheck %s --check-prefixes=ANYPWR,PWR5
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR6
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR7
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR8