diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -526,26 +526,25 @@ FeatureFPRND, FeatureFPCVT, FeatureISEL, FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; + +// The first IBM designed processor with Altivec was the PPC970 aka G5, +// but that did not appear in any IBM systems. While VMX/Altivec was added in +// ISA 2.03 (pwr4), the extension was optional. The first IBM processor with +// Altivec implemented in an IBM system was Power6. def : ProcessorModel<"pwr3", G5Model, - [DirectivePwr3, FeatureAltivec, - FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, + [DirectivePwr3, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, FeatureSTFIWX, Feature64Bit]>; def : ProcessorModel<"pwr4", G5Model, - [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, - FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, - FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; + [DirectivePwr4, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, + FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; def : ProcessorModel<"pwr5", G5Model, - [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, - FeatureFSqrt, FeatureFRE, FeatureFRES, - FeatureFRSQRTE, FeatureFRSQRTES, - FeatureSTFIWX, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + [DirectivePwr5, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, + FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, + Feature64Bit, FeatureMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr5x", G5Model, - [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, - FeatureFSqrt, FeatureFRE, FeatureFRES, - FeatureFRSQRTE, FeatureFRSQRTES, - FeatureSTFIWX, FeatureFPRND, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + [DirectivePwr5x, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, + FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, + FeatureFPRND, Feature64Bit, FeatureMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr6", G5Model, [DirectivePwr6, FeatureAltivec, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, diff --git a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll --- a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll +++ b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \ ; RUN: %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \ ; RUN: %s | FileCheck %s @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] diff --git a/llvm/test/CodeGen/PowerPC/aix-func-align.ll b/llvm/test/CodeGen/PowerPC/aix-func-align.ll --- a/llvm/test/CodeGen/PowerPC/aix-func-align.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-align.ll @@ -1,9 +1,9 @@ ; This test tries to verify if a csect containing code would have the correct alignment. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ diff --git a/llvm/test/CodeGen/PowerPC/aix-internal.ll b/llvm/test/CodeGen/PowerPC/aix-internal.ll --- a/llvm/test/CodeGen/PowerPC/aix-internal.ll +++ b/llvm/test/CodeGen/PowerPC/aix-internal.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ +; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 \ ; RUN: -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck %s ; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ diff --git a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll --- a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll +++ b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -data-sections=false < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s @foo_ptr = global void (...)* @foo diff --git a/llvm/test/CodeGen/PowerPC/aix-return55.ll b/llvm/test/CodeGen/PowerPC/aix-return55.ll --- a/llvm/test/CodeGen/PowerPC/aix-return55.ll +++ b/llvm/test/CodeGen/PowerPC/aix-return55.ll @@ -1,5 +1,5 @@ -; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s -; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s +; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s +; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll @@ -1,26 +1,26 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll @@ -1,10 +1,10 @@ ; This file tests the codegen of mergeable const in AIX assembly. ; This file also tests mergeable const in XCOFF object file generation. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll @@ -3,12 +3,12 @@ ; the test in this file should be merged into aix-xcoff-data.ll with additional ; tests for XCOFF object files. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ -; RUN: -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ -; RUN: -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: -data-sections=false < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -data-sections=false < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -filetype=obj -code-model=large -o %t.o < %s ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll @@ -1,12 +1,12 @@ ; This file tests TOC entry generation and undefined symbol generation. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ +; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir --- a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir +++ b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir @@ -1,6 +1,6 @@ -# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \ -# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ -# RUN: FileCheck %s --check-prefixes=CHECK +# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \ +# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK --- name: CRMultiSave diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll --- a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \ -; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \ +; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \ ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir --- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir +++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir @@ -7,7 +7,7 @@ # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL -# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \ +# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \ # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll --- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll +++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR6 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR7 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR8 @@ -7,16 +6,6 @@ define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ugt_1_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vaddubm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequb 2, 2, 3 -; PWR5-NEXT: vnot 2, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_1_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: vspltisb 3, -1 @@ -57,15 +46,6 @@ } define <16 x i8> @ult_2_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ult_2_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vaddubm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequb 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_2_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: vspltisb 3, -1 @@ -104,31 +84,6 @@ } define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ugt_2_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI2_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI2_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_2_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI2_0@toc@ha @@ -199,32 +154,6 @@ } define <16 x i8> @ult_3_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ult_3_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI3_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI3_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 3 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_3_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI3_0@toc@ha @@ -297,32 +226,6 @@ } define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ugt_3_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 3 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_3_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI4_0@toc@ha @@ -395,31 +298,6 @@ } define <16 x i8> @ult_4_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ult_4_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI5_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI5_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vcmpgtub 2, 4, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_4_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI5_0@toc@ha @@ -490,31 +368,6 @@ } define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ugt_4_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI6_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI6_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vcmpgtub 2, 2, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_4_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI6_0@toc@ha @@ -585,32 +438,6 @@ } define <16 x i8> @ult_5_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ult_5_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI7_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI7_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_5_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI7_0@toc@ha @@ -683,32 +510,6 @@ } define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ugt_5_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI8_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI8_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_5_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI8_0@toc@ha @@ -781,32 +582,6 @@ } define <16 x i8> @ult_6_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ult_6_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI9_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI9_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 6 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_6_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI9_0@toc@ha @@ -879,32 +654,6 @@ } define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ugt_6_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI10_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI10_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 6 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_6_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI10_0@toc@ha @@ -977,32 +726,6 @@ } define <16 x i8> @ult_7_v16i8(<16 x i8> %0) { -; PWR5-LABEL: ult_7_v16i8: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 7 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_7_v16i8: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI11_0@toc@ha @@ -1075,16 +798,6 @@ } define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_1_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduhm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequh 2, 2, 3 -; PWR5-NEXT: vnot 2, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_1_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: vspltisb 3, -1 @@ -1125,15 +838,6 @@ } define <8 x i16> @ult_2_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_2_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduhm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_2_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: vspltisb 3, -1 @@ -1172,36 +876,6 @@ } define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_2_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PWR5-NEXT: vspltish 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PWR5-NEXT: vsrh 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsubuhm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrh 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vadduhm 2, 3, 2 -; PWR5-NEXT: vspltish 3, 4 -; PWR5-NEXT: vsrh 3, 2, 3 -; PWR5-NEXT: vadduhm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 15 -; PWR5-NEXT: vxor 4, 4, 4 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: vmladduhm 2, 2, 3, 4 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_2_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI14_0@toc@ha @@ -1282,37 +956,6 @@ } define <8 x i16> @ult_3_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_3_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI15_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI15_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 3 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_3_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI15_0@toc@ha @@ -1395,37 +1038,6 @@ } define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_3_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_3_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI16_0@toc@ha @@ -1508,36 +1120,6 @@ } define <8 x i16> @ult_4_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_4_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI17_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI17_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 5, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_4_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI17_0@toc@ha @@ -1618,36 +1200,6 @@ } define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_4_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI18_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_4_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI18_0@toc@ha @@ -1728,37 +1280,6 @@ } define <8 x i16> @ult_5_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_5_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 5 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_5_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI19_0@toc@ha @@ -1841,37 +1362,6 @@ } define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_5_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI20_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI20_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 5 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_5_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI20_0@toc@ha @@ -1954,37 +1444,6 @@ } define <8 x i16> @ult_6_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_6_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 6 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_6_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI21_0@toc@ha @@ -2067,37 +1526,6 @@ } define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_6_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI22_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI22_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 6 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_6_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI22_0@toc@ha @@ -2180,37 +1608,6 @@ } define <8 x i16> @ult_7_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_7_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI23_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 7 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_7_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI23_0@toc@ha @@ -2293,37 +1690,6 @@ } define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_7_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 7 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_7_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI24_0@toc@ha @@ -2406,36 +1772,6 @@ } define <8 x i16> @ult_8_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_8_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI25_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI25_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_8_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI25_0@toc@ha @@ -2516,36 +1852,6 @@ } define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_8_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI26_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI26_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_8_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI26_0@toc@ha @@ -2626,37 +1932,6 @@ } define <8 x i16> @ult_9_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_9_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI27_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI27_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 9 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_9_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI27_0@toc@ha @@ -2739,37 +2014,6 @@ } define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_9_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI28_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI28_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 9 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_9_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI28_0@toc@ha @@ -2852,37 +2096,6 @@ } define <8 x i16> @ult_10_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_10_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI29_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 10 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_10_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI29_0@toc@ha @@ -2965,37 +2178,6 @@ } define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_10_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI30_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI30_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 10 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_10_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI30_0@toc@ha @@ -3078,37 +2260,6 @@ } define <8 x i16> @ult_11_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_11_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI31_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI31_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 11 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_11_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI31_0@toc@ha @@ -3191,37 +2342,6 @@ } define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_11_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI32_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI32_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 11 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_11_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI32_0@toc@ha @@ -3304,37 +2424,6 @@ } define <8 x i16> @ult_12_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_12_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI33_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI33_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 12 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_12_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI33_0@toc@ha @@ -3417,37 +2506,6 @@ } define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_12_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI34_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI34_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 12 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_12_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI34_0@toc@ha @@ -3530,37 +2588,6 @@ } define <8 x i16> @ult_13_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_13_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI35_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI35_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 13 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_13_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI35_0@toc@ha @@ -3643,37 +2670,6 @@ } define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_13_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI36_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI36_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 13 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_13_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI36_0@toc@ha @@ -3756,37 +2752,6 @@ } define <8 x i16> @ult_14_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_14_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI37_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI37_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 14 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_14_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI37_0@toc@ha @@ -3869,37 +2834,6 @@ } define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ugt_14_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI38_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI38_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 14 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_14_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI38_0@toc@ha @@ -3982,37 +2916,6 @@ } define <8 x i16> @ult_15_v8i16(<8 x i16> %0) { -; PWR5-LABEL: ult_15_v8i16: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI39_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI39_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 15 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_15_v8i16: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI39_0@toc@ha @@ -4095,16 +2998,6 @@ } define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_1_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduwm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequw 2, 2, 3 -; PWR5-NEXT: vnot 2, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_1_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: vspltisb 3, -1 @@ -4145,15 +3038,6 @@ } define <4 x i32> @ult_2_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_2_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduwm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_2_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: vspltisb 3, -1 @@ -4192,42 +3076,6 @@ } define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_2_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI42_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI42_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 1, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 0 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_2_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI42_0@toc@ha @@ -4320,43 +3168,6 @@ } define <4 x i32> @ult_3_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_3_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI43_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI43_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI43_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_3_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI43_0@toc@ha @@ -4451,43 +3262,6 @@ } define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_3_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI44_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI44_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI44_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_3_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI44_0@toc@ha @@ -4582,42 +3356,6 @@ } define <4 x i32> @ult_4_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_4_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI45_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI45_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 4, 0 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 5, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_4_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI45_0@toc@ha @@ -4710,42 +3448,6 @@ } define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_4_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI46_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI46_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 4, 0 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_4_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI46_0@toc@ha @@ -4838,43 +3540,6 @@ } define <4 x i32> @ult_5_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_5_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI47_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI47_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_5_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI47_0@toc@ha @@ -4969,43 +3634,6 @@ } define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_5_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI48_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI48_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_5_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI48_0@toc@ha @@ -5100,43 +3728,6 @@ } define <4 x i32> @ult_6_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_6_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI49_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI49_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI49_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 6 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_6_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI49_0@toc@ha @@ -5231,43 +3822,6 @@ } define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_6_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI50_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI50_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI50_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 6 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_6_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI50_0@toc@ha @@ -5362,43 +3916,6 @@ } define <4 x i32> @ult_7_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_7_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI51_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI51_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_7_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI51_0@toc@ha @@ -5493,43 +4010,6 @@ } define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_7_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI52_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI52_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI52_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_7_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI52_0@toc@ha @@ -5624,43 +4104,6 @@ } define <4 x i32> @ult_8_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_8_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI53_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI53_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI53_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_8_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI53_0@toc@ha @@ -5755,43 +4198,6 @@ } define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_8_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI54_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI54_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI54_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_8_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI54_0@toc@ha @@ -5886,43 +4292,6 @@ } define <4 x i32> @ult_9_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_9_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI55_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI55_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI55_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_9_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI55_0@toc@ha @@ -6017,43 +4386,6 @@ } define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_9_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI56_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI56_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_9_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI56_0@toc@ha @@ -6148,43 +4480,6 @@ } define <4 x i32> @ult_10_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_10_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI57_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI57_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI57_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_10_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI57_0@toc@ha @@ -6279,43 +4574,6 @@ } define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_10_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI58_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI58_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_10_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI58_0@toc@ha @@ -6410,43 +4668,6 @@ } define <4 x i32> @ult_11_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_11_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI59_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI59_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_11_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI59_0@toc@ha @@ -6541,43 +4762,6 @@ } define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_11_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI60_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI60_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI60_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_11_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI60_0@toc@ha @@ -6672,42 +4856,6 @@ } define <4 x i32> @ult_12_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_12_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI61_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI61_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 5, 3, 3 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_12_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI61_0@toc@ha @@ -6800,42 +4948,6 @@ } define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_12_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI62_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI62_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI62_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 5, 3, 3 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_12_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI62_0@toc@ha @@ -6928,43 +5040,6 @@ } define <4 x i32> @ult_13_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_13_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI63_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI63_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_13_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI63_0@toc@ha @@ -7059,43 +5134,6 @@ } define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_13_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI64_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI64_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_13_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI64_0@toc@ha @@ -7190,43 +5228,6 @@ } define <4 x i32> @ult_14_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_14_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI65_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI65_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI65_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_14_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI65_0@toc@ha @@ -7321,43 +5322,6 @@ } define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_14_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI66_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI66_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_14_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI66_0@toc@ha @@ -7452,43 +5416,6 @@ } define <4 x i32> @ult_15_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_15_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI67_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI67_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI67_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_15_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI67_0@toc@ha @@ -7583,43 +5510,6 @@ } define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_15_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI68_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI68_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_15_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI68_0@toc@ha @@ -7714,44 +5604,6 @@ } define <4 x i32> @ult_16_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_16_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI69_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI69_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_16_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI69_0@toc@ha @@ -7850,44 +5702,6 @@ } define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_16_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI70_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI70_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI70_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_16_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI70_0@toc@ha @@ -7986,43 +5800,6 @@ } define <4 x i32> @ult_17_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_17_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI71_0@toc@l -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI71_1@toc@l -; PWR5-NEXT: vspltisw 1, 2 -; PWR5-NEXT: vsrw 5, 2, 4 -; PWR5-NEXT: vand 5, 5, 0 -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 5 -; PWR5-NEXT: vand 5, 2, 0 -; PWR5-NEXT: vsrw 2, 2, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, 4 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 5, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vadduwm 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 5, 0 -; PWR5-NEXT: vmulouh 5, 2, 5 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vsubuwm 3, 4, 0 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_17_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI71_0@toc@ha @@ -8121,43 +5898,6 @@ } define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_17_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI72_0@toc@l -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI72_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI72_1@toc@l -; PWR5-NEXT: vspltisw 1, 2 -; PWR5-NEXT: vsrw 5, 2, 4 -; PWR5-NEXT: vand 5, 5, 0 -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 5 -; PWR5-NEXT: vand 5, 2, 0 -; PWR5-NEXT: vsrw 2, 2, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, 4 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 5, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vadduwm 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 5, 0 -; PWR5-NEXT: vmulouh 5, 2, 5 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vsubuwm 3, 4, 0 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_17_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI72_0@toc@ha @@ -8256,44 +5996,6 @@ } define <4 x i32> @ult_18_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_18_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI73_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI73_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI73_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_18_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI73_0@toc@ha @@ -8392,44 +6094,6 @@ } define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_18_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI74_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI74_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI74_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_18_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI74_0@toc@ha @@ -8528,44 +6192,6 @@ } define <4 x i32> @ult_19_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_19_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI75_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI75_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI75_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_19_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI75_0@toc@ha @@ -8666,44 +6292,6 @@ } define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_19_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI76_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI76_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_19_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI76_0@toc@ha @@ -8804,44 +6392,6 @@ } define <4 x i32> @ult_20_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_20_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI77_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI77_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_20_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI77_0@toc@ha @@ -8940,44 +6490,6 @@ } define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_20_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI78_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI78_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_20_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI78_0@toc@ha @@ -9076,44 +6588,6 @@ } define <4 x i32> @ult_21_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_21_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI79_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_21_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI79_0@toc@ha @@ -9214,44 +6688,6 @@ } define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_21_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI80_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI80_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI80_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_21_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI80_0@toc@ha @@ -9352,44 +6788,6 @@ } define <4 x i32> @ult_22_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_22_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI81_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI81_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_22_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI81_0@toc@ha @@ -9488,44 +6886,6 @@ } define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_22_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI82_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI82_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI82_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_22_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI82_0@toc@ha @@ -9624,44 +6984,6 @@ } define <4 x i32> @ult_23_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_23_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI83_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI83_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI83_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_23_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI83_0@toc@ha @@ -9762,44 +7084,6 @@ } define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_23_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI84_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI84_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI84_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_23_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI84_0@toc@ha @@ -9900,42 +7184,6 @@ } define <4 x i32> @ult_24_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_24_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI85_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI85_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_24_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI85_0@toc@ha @@ -10030,42 +7278,6 @@ } define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_24_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_24_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI86_0@toc@ha @@ -10160,44 +7372,6 @@ } define <4 x i32> @ult_25_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_25_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI87_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI87_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_25_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI87_0@toc@ha @@ -10298,44 +7472,6 @@ } define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_25_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI88_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI88_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_25_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI88_0@toc@ha @@ -10436,44 +7572,6 @@ } define <4 x i32> @ult_26_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_26_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_26_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI89_0@toc@ha @@ -10572,44 +7670,6 @@ } define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_26_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI90_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI90_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_26_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI90_0@toc@ha @@ -10708,44 +7768,6 @@ } define <4 x i32> @ult_27_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_27_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_27_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI91_0@toc@ha @@ -10846,44 +7868,6 @@ } define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_27_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI92_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI92_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_27_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI92_0@toc@ha @@ -10984,44 +7968,6 @@ } define <4 x i32> @ult_28_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_28_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI93_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI93_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_28_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI93_0@toc@ha @@ -11120,44 +8066,6 @@ } define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_28_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_28_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI94_0@toc@ha @@ -11256,44 +8164,6 @@ } define <4 x i32> @ult_29_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_29_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI95_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI95_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI95_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_29_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI95_0@toc@ha @@ -11394,44 +8264,6 @@ } define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_29_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI96_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI96_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_29_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI96_0@toc@ha @@ -11532,44 +8364,6 @@ } define <4 x i32> @ult_30_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_30_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI97_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_30_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI97_0@toc@ha @@ -11668,44 +8462,6 @@ } define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ugt_30_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI98_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI98_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_30_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI98_0@toc@ha @@ -11804,44 +8560,6 @@ } define <4 x i32> @ult_31_v4i32(<4 x i32> %0) { -; PWR5-LABEL: ult_31_v4i32: -; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI99_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI99_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI99_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_31_v4i32: ; PWR6: # %bb.0: ; PWR6-NEXT: addis 3, 2, .LCPI99_0@toc@ha @@ -11942,18 +8660,6 @@ } define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_1_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: addi 5, 3, -1 -; PWR5-NEXT: and 3, 3, 5 -; PWR5-NEXT: addi 5, 4, -1 -; PWR5-NEXT: subfic 3, 3, 0 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: and 4, 4, 5 -; PWR5-NEXT: subfic 4, 4, 0 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_1_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: addi 5, 3, -1 @@ -12010,18 +8716,6 @@ } define <2 x i64> @ult_2_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_2_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: addi 5, 3, -1 -; PWR5-NEXT: and 3, 3, 5 -; PWR5-NEXT: addi 5, 4, -1 -; PWR5-NEXT: addic 3, 3, -1 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: and 4, 4, 5 -; PWR5-NEXT: addic 4, 4, -1 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_2_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: addi 5, 3, -1 @@ -12077,51 +8771,6 @@ } define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_2_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 2 -; PWR5-NEXT: subfic 3, 3, 2 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 2 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_2_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -12211,51 +8860,6 @@ } define <2 x i64> @ult_3_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_3_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 3 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_3_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -12345,51 +8949,6 @@ } define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_3_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 3 -; PWR5-NEXT: subfic 3, 3, 3 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 3 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_3_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -12479,51 +9038,6 @@ } define <2 x i64> @ult_4_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_4_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 4 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_4_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -12613,51 +9127,6 @@ } define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_4_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 4 -; PWR5-NEXT: subfic 3, 3, 4 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 4 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_4_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -12747,51 +9216,6 @@ } define <2 x i64> @ult_5_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_5_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 5 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_5_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -12881,51 +9305,6 @@ } define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_5_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 5 -; PWR5-NEXT: subfic 3, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 5 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_5_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13015,51 +9394,6 @@ } define <2 x i64> @ult_6_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_6_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 6 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_6_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13149,51 +9483,6 @@ } define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_6_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 6 -; PWR5-NEXT: subfic 3, 3, 6 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 6 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_6_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13283,51 +9572,6 @@ } define <2 x i64> @ult_7_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_7_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 7 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_7_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13417,51 +9661,6 @@ } define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_7_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 7 -; PWR5-NEXT: subfic 3, 3, 7 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 7 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_7_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13551,51 +9750,6 @@ } define <2 x i64> @ult_8_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_8_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 8 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_8_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13685,51 +9839,6 @@ } define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_8_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 8 -; PWR5-NEXT: subfic 3, 3, 8 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 8 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_8_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13819,51 +9928,6 @@ } define <2 x i64> @ult_9_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_9_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 9 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_9_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -13953,51 +10017,6 @@ } define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_9_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 9 -; PWR5-NEXT: subfic 3, 3, 9 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 9 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_9_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14087,51 +10106,6 @@ } define <2 x i64> @ult_10_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_10_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 10 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_10_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14221,51 +10195,6 @@ } define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_10_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 10 -; PWR5-NEXT: subfic 3, 3, 10 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 10 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_10_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14355,51 +10284,6 @@ } define <2 x i64> @ult_11_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_11_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 11 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_11_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14489,51 +10373,6 @@ } define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_11_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 11 -; PWR5-NEXT: subfic 3, 3, 11 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 11 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_11_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14623,51 +10462,6 @@ } define <2 x i64> @ult_12_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_12_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 12 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_12_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14757,51 +10551,6 @@ } define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_12_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 12 -; PWR5-NEXT: subfic 3, 3, 12 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 12 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_12_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -14891,51 +10640,6 @@ } define <2 x i64> @ult_13_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_13_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 13 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_13_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15025,51 +10729,6 @@ } define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_13_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 13 -; PWR5-NEXT: subfic 3, 3, 13 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 13 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_13_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15159,51 +10818,6 @@ } define <2 x i64> @ult_14_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_14_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 14 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_14_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15293,51 +10907,6 @@ } define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_14_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 14 -; PWR5-NEXT: subfic 3, 3, 14 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 14 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_14_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15427,51 +10996,6 @@ } define <2 x i64> @ult_15_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_15_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 15 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_15_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15561,51 +11085,6 @@ } define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_15_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 15 -; PWR5-NEXT: subfic 3, 3, 15 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 15 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_15_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15695,51 +11174,6 @@ } define <2 x i64> @ult_16_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_16_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 16 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_16_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15829,51 +11263,6 @@ } define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_16_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 16 -; PWR5-NEXT: subfic 3, 3, 16 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 16 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_16_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -15963,51 +11352,6 @@ } define <2 x i64> @ult_17_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_17_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 17 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_17_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16097,51 +11441,6 @@ } define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_17_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 17 -; PWR5-NEXT: subfic 3, 3, 17 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 17 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_17_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16231,51 +11530,6 @@ } define <2 x i64> @ult_18_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_18_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 18 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_18_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16365,51 +11619,6 @@ } define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_18_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 18 -; PWR5-NEXT: subfic 3, 3, 18 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 18 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_18_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16499,51 +11708,6 @@ } define <2 x i64> @ult_19_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_19_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 19 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_19_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16633,51 +11797,6 @@ } define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_19_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 19 -; PWR5-NEXT: subfic 3, 3, 19 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 19 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_19_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16767,51 +11886,6 @@ } define <2 x i64> @ult_20_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_20_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 20 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_20_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -16901,51 +11975,6 @@ } define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_20_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 20 -; PWR5-NEXT: subfic 3, 3, 20 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 20 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_20_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17035,51 +12064,6 @@ } define <2 x i64> @ult_21_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_21_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 21 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_21_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17169,51 +12153,6 @@ } define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_21_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 21 -; PWR5-NEXT: subfic 3, 3, 21 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 21 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_21_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17303,51 +12242,6 @@ } define <2 x i64> @ult_22_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_22_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 22 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_22_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17437,51 +12331,6 @@ } define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_22_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 22 -; PWR5-NEXT: subfic 3, 3, 22 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 22 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_22_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17571,51 +12420,6 @@ } define <2 x i64> @ult_23_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_23_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 23 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_23_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17705,51 +12509,6 @@ } define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_23_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 23 -; PWR5-NEXT: subfic 3, 3, 23 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 23 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_23_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17839,51 +12598,6 @@ } define <2 x i64> @ult_24_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_24_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 24 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_24_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -17973,51 +12687,6 @@ } define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_24_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 24 -; PWR5-NEXT: subfic 3, 3, 24 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 24 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_24_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18107,51 +12776,6 @@ } define <2 x i64> @ult_25_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_25_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 25 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_25_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18241,51 +12865,6 @@ } define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_25_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 25 -; PWR5-NEXT: subfic 3, 3, 25 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 25 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_25_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18375,51 +12954,6 @@ } define <2 x i64> @ult_26_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_26_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 26 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_26_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18509,51 +13043,6 @@ } define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_26_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 26 -; PWR5-NEXT: subfic 3, 3, 26 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 26 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_26_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18643,51 +13132,6 @@ } define <2 x i64> @ult_27_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_27_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 27 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_27_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18777,51 +13221,6 @@ } define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_27_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 27 -; PWR5-NEXT: subfic 3, 3, 27 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 27 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_27_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -18911,51 +13310,6 @@ } define <2 x i64> @ult_28_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_28_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 28 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_28_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19045,51 +13399,6 @@ } define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_28_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 28 -; PWR5-NEXT: subfic 3, 3, 28 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 28 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_28_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19179,51 +13488,6 @@ } define <2 x i64> @ult_29_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_29_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 29 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_29_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19313,51 +13577,6 @@ } define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_29_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 29 -; PWR5-NEXT: subfic 3, 3, 29 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 29 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_29_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19447,51 +13666,6 @@ } define <2 x i64> @ult_30_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_30_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 30 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_30_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19581,51 +13755,6 @@ } define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_30_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 30 -; PWR5-NEXT: subfic 3, 3, 30 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 30 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_30_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19715,51 +13844,6 @@ } define <2 x i64> @ult_31_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_31_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 31 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_31_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19849,51 +13933,6 @@ } define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_31_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 31 -; PWR5-NEXT: subfic 3, 3, 31 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 31 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_31_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -19983,51 +14022,6 @@ } define <2 x i64> @ult_32_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_32_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 32 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_32_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20117,51 +14111,6 @@ } define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_32_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 32 -; PWR5-NEXT: subfic 3, 3, 32 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 32 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_32_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20251,51 +14200,6 @@ } define <2 x i64> @ult_33_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_33_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 33 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_33_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20385,51 +14289,6 @@ } define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_33_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 33 -; PWR5-NEXT: subfic 3, 3, 33 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 33 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_33_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20519,51 +14378,6 @@ } define <2 x i64> @ult_34_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_34_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 34 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_34_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20653,51 +14467,6 @@ } define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_34_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 34 -; PWR5-NEXT: subfic 3, 3, 34 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 34 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_34_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20787,51 +14556,6 @@ } define <2 x i64> @ult_35_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_35_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 35 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_35_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -20921,51 +14645,6 @@ } define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_35_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 35 -; PWR5-NEXT: subfic 3, 3, 35 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 35 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_35_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21055,51 +14734,6 @@ } define <2 x i64> @ult_36_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_36_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 36 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_36_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21189,51 +14823,6 @@ } define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_36_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 36 -; PWR5-NEXT: subfic 3, 3, 36 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 36 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_36_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21323,51 +14912,6 @@ } define <2 x i64> @ult_37_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_37_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 37 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_37_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21457,51 +15001,6 @@ } define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_37_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 37 -; PWR5-NEXT: subfic 3, 3, 37 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 37 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_37_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21591,51 +15090,6 @@ } define <2 x i64> @ult_38_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_38_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 38 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_38_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21725,51 +15179,6 @@ } define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_38_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 38 -; PWR5-NEXT: subfic 3, 3, 38 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 38 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_38_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21859,51 +15268,6 @@ } define <2 x i64> @ult_39_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_39_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 39 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_39_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -21993,51 +15357,6 @@ } define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_39_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 39 -; PWR5-NEXT: subfic 3, 3, 39 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 39 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_39_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22127,51 +15446,6 @@ } define <2 x i64> @ult_40_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_40_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 40 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_40_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22261,51 +15535,6 @@ } define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_40_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 40 -; PWR5-NEXT: subfic 3, 3, 40 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 40 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_40_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22395,51 +15624,6 @@ } define <2 x i64> @ult_41_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_41_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 41 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_41_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22529,51 +15713,6 @@ } define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_41_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 41 -; PWR5-NEXT: subfic 3, 3, 41 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 41 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_41_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22663,51 +15802,6 @@ } define <2 x i64> @ult_42_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_42_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 42 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_42_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22797,51 +15891,6 @@ } define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_42_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 42 -; PWR5-NEXT: subfic 3, 3, 42 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 42 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_42_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -22931,51 +15980,6 @@ } define <2 x i64> @ult_43_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_43_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 43 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_43_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23065,51 +16069,6 @@ } define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_43_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 43 -; PWR5-NEXT: subfic 3, 3, 43 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 43 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_43_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23199,51 +16158,6 @@ } define <2 x i64> @ult_44_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_44_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 44 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_44_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23333,51 +16247,6 @@ } define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_44_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 44 -; PWR5-NEXT: subfic 3, 3, 44 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 44 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_44_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23467,51 +16336,6 @@ } define <2 x i64> @ult_45_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_45_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 45 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_45_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23601,51 +16425,6 @@ } define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_45_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 45 -; PWR5-NEXT: subfic 3, 3, 45 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 45 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_45_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23735,51 +16514,6 @@ } define <2 x i64> @ult_46_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_46_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 46 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_46_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -23869,51 +16603,6 @@ } define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_46_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 46 -; PWR5-NEXT: subfic 3, 3, 46 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 46 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_46_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24003,51 +16692,6 @@ } define <2 x i64> @ult_47_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_47_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 47 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_47_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24137,51 +16781,6 @@ } define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_47_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 47 -; PWR5-NEXT: subfic 3, 3, 47 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 47 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_47_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24271,51 +16870,6 @@ } define <2 x i64> @ult_48_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_48_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 48 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_48_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24405,51 +16959,6 @@ } define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_48_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 48 -; PWR5-NEXT: subfic 3, 3, 48 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 48 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_48_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24539,51 +17048,6 @@ } define <2 x i64> @ult_49_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_49_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 49 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_49_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24673,51 +17137,6 @@ } define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_49_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 49 -; PWR5-NEXT: subfic 3, 3, 49 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 49 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_49_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24807,51 +17226,6 @@ } define <2 x i64> @ult_50_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_50_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 50 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_50_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -24941,51 +17315,6 @@ } define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_50_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 50 -; PWR5-NEXT: subfic 3, 3, 50 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 50 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_50_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25075,51 +17404,6 @@ } define <2 x i64> @ult_51_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_51_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 51 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_51_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25209,51 +17493,6 @@ } define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_51_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 51 -; PWR5-NEXT: subfic 3, 3, 51 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 51 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_51_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25343,51 +17582,6 @@ } define <2 x i64> @ult_52_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_52_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 52 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_52_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25477,51 +17671,6 @@ } define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_52_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 52 -; PWR5-NEXT: subfic 3, 3, 52 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 52 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_52_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25611,51 +17760,6 @@ } define <2 x i64> @ult_53_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_53_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 53 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_53_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25745,51 +17849,6 @@ } define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_53_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 53 -; PWR5-NEXT: subfic 3, 3, 53 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 53 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_53_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -25879,51 +17938,6 @@ } define <2 x i64> @ult_54_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_54_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 54 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_54_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26013,51 +18027,6 @@ } define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_54_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 54 -; PWR5-NEXT: subfic 3, 3, 54 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 54 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_54_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26147,51 +18116,6 @@ } define <2 x i64> @ult_55_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_55_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 55 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_55_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26281,51 +18205,6 @@ } define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_55_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 55 -; PWR5-NEXT: subfic 3, 3, 55 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 55 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_55_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26415,51 +18294,6 @@ } define <2 x i64> @ult_56_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_56_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_56_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26549,51 +18383,6 @@ } define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_56_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 56 -; PWR5-NEXT: subfic 3, 3, 56 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 56 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_56_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26683,51 +18472,6 @@ } define <2 x i64> @ult_57_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_57_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 57 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_57_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26817,51 +18561,6 @@ } define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_57_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 57 -; PWR5-NEXT: subfic 3, 3, 57 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 57 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_57_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -26951,51 +18650,6 @@ } define <2 x i64> @ult_58_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_58_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 58 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_58_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27085,51 +18739,6 @@ } define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_58_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 58 -; PWR5-NEXT: subfic 3, 3, 58 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 58 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_58_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27219,51 +18828,6 @@ } define <2 x i64> @ult_59_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_59_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 59 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_59_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27353,51 +18917,6 @@ } define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_59_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 59 -; PWR5-NEXT: subfic 3, 3, 59 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 59 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_59_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27487,51 +19006,6 @@ } define <2 x i64> @ult_60_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_60_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 60 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_60_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27621,51 +19095,6 @@ } define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_60_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 60 -; PWR5-NEXT: subfic 3, 3, 60 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 60 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_60_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27755,51 +19184,6 @@ } define <2 x i64> @ult_61_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_61_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 61 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_61_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -27889,51 +19273,6 @@ } define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_61_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 61 -; PWR5-NEXT: subfic 3, 3, 61 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 61 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_61_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -28023,51 +19362,6 @@ } define <2 x i64> @ult_62_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_62_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 62 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_62_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -28157,51 +19451,6 @@ } define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ugt_62_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 62 -; PWR5-NEXT: subfic 3, 3, 62 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 62 -; PWR5-NEXT: subfe 4, 5, 5 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ugt_62_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845 @@ -28291,51 +19540,6 @@ } define <2 x i64> @ult_63_v2i64(<2 x i64> %0) { -; PWR5-LABEL: ult_63_v2i64: -; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 63 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 -; PWR5-NEXT: blr -; ; PWR6-LABEL: ult_63_v2i64: ; PWR6: # %bb.0: ; PWR6-NEXT: lis 5, 21845