Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5052,10 +5052,11 @@
     return CharUnits::fromQuantity(16);
   } else if (Ty->isVectorType()) {
     return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
-  } else if (Ty->isRealFloatingType() && getContext().getTypeSize(Ty) == 128) {
-    // IEEE 128-bit floating numbers are also stored in vector registers.
-    // And both IEEE quad-precision and IBM extended double (ppc_fp128) should
-    // be quad-word aligned.
+  } else if (Ty->isRealFloatingType() &&
+             &getContext().getFloatTypeSemantics(Ty) ==
+                 &llvm::APFloat::IEEEquad()) {
+    // IEEE 128-bit floating numbers are also stored in vector registers, which
+    // are quad-word aligned.
     return CharUnits::fromQuantity(16);
   }
 
Index: clang/test/CodeGen/ppc64le-varargs-f128.c
===================================================================
--- clang/test/CodeGen/ppc64le-varargs-f128.c
+++ clang/test/CodeGen/ppc64le-varargs-f128.c
@@ -34,11 +34,9 @@
 
 // IBM-LABEL: define ppc_fp128 @long_double(i32 signext %n, ...)
 // IBM: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IBM: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
-// IBM: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
-// IBM: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IBM: %[[P3:[0-9a-zA-Z_.]+]] = load i8*, i8** %{{[0-9a-zA-Z_.]+}}, align 8
 // IBM: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to ppc_fp128*
-// IBM: %{{[0-9a-zA-Z_.]+}} = load ppc_fp128, ppc_fp128* %[[P4]], align 16
+// IBM: %{{[0-9a-zA-Z_.]+}} = load ppc_fp128, ppc_fp128* %[[P4]], align 8
 // IBM: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 long double long_double(int n, ...) {
   va_list ap;