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[SVE][CodeGen] Add DAG combines for s/zext_masked_gather

Authored by kmclaughlin on Nov 27 2020, 7:19 AM.



This patch adds the following DAGCombines, which apply if isVectorLoadExtDesirable() returns true:

  • fold (and (masked_gather x)) -> (zext_masked_gather x)
  • fold (sext_inreg (masked_gather x)) -> (sext_masked_gather x)

LowerMGATHER has also been updated to fetch the LoadExtType associated with the
gather and also use this value to determine the correct masked gather opcode to use.

Diff Detail

Event Timeline

kmclaughlin created this revision.Nov 27 2020, 7:19 AM

Added an option to disable the existing combines in AArch64ISelLowering for s/zext_masked_gathers (performSignExtendInRegCombine & performSVEAndCombine)

The option (-aarch64-enable-mgather-combine) has been added to the RUN lines of the SVE masked gather tests added in D91092, ensuring the combines added in this patch are being tested.

It probably makes more sense to add -aarch64-enable-mgather-combine=0 in D91092, so that in this patch you can clearly see benefits of the change added in DAGCombiner.

  • Moved the addition of the -aarch64-enable-mgather-combine option to D91092 in order to more clearly demonstrate the value added by the combines in this patch.
sdesmalen added inline comments.Nov 30 2020, 9:48 AM

nit: s/ResNeedsExtend/ResNeedsSignExtend/ ?


nit: s/getExtendedGatherOpcode/getSignExtendedGatherOpcode/


Can you add a similar test with zero-extend?

kmclaughlin marked 3 inline comments as done.
  • Renamed ResNeedsExtend -> ResNeedsSignExtend
  • Added a test to sve-masked-gather-legalize.ll for a zero-extended gather load with multiple uses
sdesmalen accepted this revision.Dec 8 2020, 6:32 AM


This revision is now accepted and ready to land.Dec 8 2020, 6:32 AM