diff --git a/lld/test/ELF/riscv-branch.s b/lld/test/ELF/riscv-branch.s --- a/lld/test/ELF/riscv-branch.s +++ b/lld/test/ELF/riscv-branch.s @@ -5,17 +5,21 @@ # RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32 # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64 -# RUN: llvm-objdump -d %t.rv32 | FileCheck %s -# RUN: llvm-objdump -d %t.rv64 | FileCheck %s -# CHECK: 63 02 00 00 beqz zero, 4 -# CHECK: e3 1e 00 fe bnez zero, -4 +# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32 +# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64 +# CHECK-32: 63 02 00 00 beqz zero, 0x110b8 +# CHECK-32: e3 1e 00 fe bnez zero, 0x110b4 +# CHECK-64: 63 02 00 00 beqz zero, 0x11124 +# CHECK-64: e3 1e 00 fe bnez zero, 0x11120 # # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits -# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s -# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s -# LIMITS: e3 0f 00 7e beqz zero, 4094 -# LIMITS-NEXT: 63 10 00 80 bnez zero, -4096 +# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s +# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s +# LIMITS-32: e3 0f 00 7e beqz zero, 0x120b2 +# LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8 +# LIMITS-64: e3 0f 00 7e beqz zero, 0x1211e +# LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s diff --git a/lld/test/ELF/riscv-jal.s b/lld/test/ELF/riscv-jal.s --- a/lld/test/ELF/riscv-jal.s +++ b/lld/test/ELF/riscv-jal.s @@ -5,17 +5,21 @@ # RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32 # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64 -# RUN: llvm-objdump -d %t.rv32 | FileCheck %s -# RUN: llvm-objdump -d %t.rv64 | FileCheck %s -# CHECK: 6f 00 40 00 j 4 -# CHECK: ef f0 df ff jal -4 +# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32 +# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64 +# CHECK-32: 6f 00 40 00 j 0x110b8 +# CHECK-32: ef f0 df ff jal 0x110b4 +# CHECK-64: 6f 00 40 00 j 0x11124 +# CHECK-64: ef f0 df ff jal 0x11120 # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits -# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s -# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s -# LIMITS: 6f f0 ff 7f j 1048574 -# LIMITS-NEXT: ef 00 00 80 jal -1048576 +# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s +# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s +# LIMITS-32: 6f f0 ff 7f j 0x1110b2 +# LIMITS-32-NEXT: ef 00 00 80 jal 0xfff110b8 +# LIMITS-64: 6f f0 ff 7f j 0x11111e +# LIMITS-64-NEXT: ef 00 00 80 jal 0xfffffffffff11124 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s diff --git a/lld/test/ELF/riscv-undefined-weak.s b/lld/test/ELF/riscv-undefined-weak.s --- a/lld/test/ELF/riscv-undefined-weak.s +++ b/lld/test/ELF/riscv-undefined-weak.s @@ -52,15 +52,14 @@ # PC-LABEL: : # PC-NEXT: auipc ra, 1048559 # PC-NEXT: jalr -368(ra) -## FIXME: llvm-objdump -d should print the address, instead of the offset. -# PC-NEXT: j -70008 +# PC-NEXT: j 0x0 ## If .dynsym exists, an undefined weak symbol is preemptible. ## We create a PLT entry and redirect the reference to it. # PLT-LABEL: : # PLT-NEXT: auipc ra, 0 # PLT-NEXT: jalr 56(ra) -# PLT-NEXT: j -70448 +# PLT-NEXT: j 0x0 branch: call target jal x0, target diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -32,6 +32,8 @@ void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); + void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFenceArg(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -102,6 +102,24 @@ MO.getExpr()->print(O, &MAI); } +void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, + unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + if (!MO.isImm()) + return printOperand(MI, OpNo, STI, O); + + if (PrintBranchImmAsAddress) { + uint64_t Target = Address + MO.getImm(); + if (!STI.hasFeature(RISCV::Feature64Bit)) + Target &= 0xffffffff; + O << formatHex(Target); + } else { + O << MO.getImm(); + } +} + void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -604,15 +604,9 @@ case RISCVOp::OPERAND_SIMM12: Ok = isInt<12>(Imm); break; - case RISCVOp::OPERAND_SIMM13_LSB0: - Ok = isShiftedInt<12, 1>(Imm); - break; case RISCVOp::OPERAND_UIMM20: Ok = isUInt<20>(Imm); break; - case RISCVOp::OPERAND_SIMM21_LSB0: - Ok = isShiftedInt<20, 1>(Imm); - break; case RISCVOp::OPERAND_UIMMLOG2XLEN: if (STI.getTargetTriple().isArch64Bit()) Ok = isUInt<6>(Imm); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -160,6 +160,7 @@ // A 13-bit signed immediate where the least significant bit is zero. def simm13_lsb0 : Operand { let ParserMatchClass = SImmAsmOperand<13, "Lsb0">; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<13>"; let MCOperandPredicate = [{ @@ -168,8 +169,7 @@ return isShiftedInt<12, 1>(Imm); return MCOp.isBareSymbolRef(); }]; - let OperandType = "OPERAND_SIMM13_LSB0"; - let OperandNamespace = "RISCVOp"; + let OperandType = "OPERAND_PCREL"; } class UImm20Operand : Operand { @@ -199,6 +199,7 @@ // A 21-bit signed immediate where the least significant bit is zero. def simm21_lsb0_jal : Operand { let ParserMatchClass = Simm21Lsb0JALAsmOperand; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<21>"; let MCOperandPredicate = [{ @@ -207,8 +208,7 @@ return isShiftedInt<20, 1>(Imm); return MCOp.isBareSymbolRef(); }]; - let OperandType = "OPERAND_SIMM21_LSB0"; - let OperandNamespace = "RISCVOp"; + let OperandType = "OPERAND_PCREL"; } def BareSymbol : AsmOperandClass { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -140,6 +140,7 @@ def simm9_lsb0 : Operand, ImmLeaf(Imm);}]> { let ParserMatchClass = SImmAsmOperand<9, "Lsb0">; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<9>"; let MCOperandPredicate = [{ @@ -149,6 +150,7 @@ return MCOp.isBareSymbolRef(); }]; + let OperandType = "OPERAND_PCREL"; } // A 9-bit unsigned immediate where the least significant three bits are zero. @@ -200,6 +202,7 @@ def simm12_lsb0 : Operand, ImmLeaf(Imm);}]> { let ParserMatchClass = SImmAsmOperand<12, "Lsb0">; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<12>"; let MCOperandPredicate = [{ @@ -208,6 +211,7 @@ return isShiftedInt<11, 1>(Imm); return MCOp.isBareSymbolRef(); }]; + let OperandType = "OPERAND_PCREL"; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -132,9 +132,7 @@ OPERAND_UIMM5, OPERAND_UIMM12, OPERAND_SIMM12, - OPERAND_SIMM13_LSB0, OPERAND_UIMM20, - OPERAND_SIMM21_LSB0, OPERAND_UIMMLOG2XLEN, OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN }; diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll --- a/llvm/test/CodeGen/RISCV/compress.ll +++ b/llvm/test/CodeGen/RISCV/compress.ll @@ -50,34 +50,34 @@ define i32 @select(i32 %a, i32 *%b) #0 { ; RV32IC-LABEL: