diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -743,251 +743,6 @@
   return false;
 }
 
-// Predict the number of instructions that would be generated by calling
-// selectI64Imm(N).
-static unsigned selectI64ImmInstrCountDirect(int64_t Imm) {
-  // Assume no remaining bits.
-  unsigned Remainder = 0;
-  // Assume no shift required.
-  unsigned Shift = 0;
-
-  // If it can't be represented as a 32 bit value.
-  if (!isInt<32>(Imm)) {
-    Shift = countTrailingZeros<uint64_t>(Imm);
-    int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
-
-    // If the shifted value fits 32 bits.
-    if (isInt<32>(ImmSh)) {
-      // Go with the shifted value.
-      Imm = ImmSh;
-    } else {
-      // Still stuck with a 64 bit value.
-      Remainder = Imm;
-      Shift = 32;
-      Imm >>= 32;
-    }
-  }
-
-  // Intermediate operand.
-  unsigned Result = 0;
-
-  // Handle first 32 bits.
-  unsigned Lo = Imm & 0xFFFF;
-
-  // Simple value.
-  if (isInt<16>(Imm)) {
-    // Just the Lo bits.
-    ++Result;
-  } else if (Lo) {
-    // Handle the Hi bits and Lo bits.
-    Result += 2;
-  } else {
-    // Just the Hi bits.
-    ++Result;
-  }
-
-  // If no shift, we're done.
-  if (!Shift) return Result;
-
-  // If Hi word == Lo word,
-  // we can use rldimi to insert the Lo word into Hi word.
-  if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
-    ++Result;
-    return Result;
-  }
-
-  // Shift for next step if the upper 32-bits were not zero.
-  if (Imm)
-    ++Result;
-
-  // Add in the last bits as required.
-  if ((Remainder >> 16) & 0xFFFF)
-    ++Result;
-  if (Remainder & 0xFFFF)
-    ++Result;
-
-  return Result;
-}
-
-static uint64_t Rot64(uint64_t Imm, unsigned R) {
-  return (Imm << R) | (Imm >> (64 - R));
-}
-
-static unsigned selectI64ImmInstrCount(int64_t Imm) {
-  unsigned Count = selectI64ImmInstrCountDirect(Imm);
-
-  // If the instruction count is 1 or 2, we do not need further analysis
-  // since rotate + load constant requires at least 2 instructions.
-  if (Count <= 2)
-    return Count;
-
-  for (unsigned r = 1; r < 63; ++r) {
-    uint64_t RImm = Rot64(Imm, r);
-    unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
-    Count = std::min(Count, RCount);
-
-    // See comments in selectI64Imm for an explanation of the logic below.
-    unsigned LS = findLastSet(RImm);
-    if (LS != r-1)
-      continue;
-
-    uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
-    uint64_t RImmWithOnes = RImm | OnesMask;
-
-    RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
-    Count = std::min(Count, RCount);
-  }
-
-  return Count;
-}
-
-// Select a 64-bit constant. For cost-modeling purposes, selectI64ImmInstrCount
-// (above) needs to be kept in sync with this function.
-static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
-                                  int64_t Imm) {
-  // Assume no remaining bits.
-  unsigned Remainder = 0;
-  // Assume no shift required.
-  unsigned Shift = 0;
-
-  // If it can't be represented as a 32 bit value.
-  if (!isInt<32>(Imm)) {
-    Shift = countTrailingZeros<uint64_t>(Imm);
-    int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
-
-    // If the shifted value fits 32 bits.
-    if (isInt<32>(ImmSh)) {
-      // Go with the shifted value.
-      Imm = ImmSh;
-    } else {
-      // Still stuck with a 64 bit value.
-      Remainder = Imm;
-      Shift = 32;
-      Imm >>= 32;
-    }
-  }
-
-  // Intermediate operand.
-  SDNode *Result;
-
-  // Handle first 32 bits.
-  unsigned Lo = Imm & 0xFFFF;
-  unsigned Hi = (Imm >> 16) & 0xFFFF;
-
-  auto getI32Imm = [CurDAG, dl](unsigned Imm) {
-      return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
-  };
-
-  // Simple value.
-  if (isInt<16>(Imm)) {
-    uint64_t SextImm = SignExtend64(Lo, 16);
-    SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
-    // Just the Lo bits.
-    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
-  } else if (Lo) {
-    // Handle the Hi bits.
-    unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
-    Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
-    // And Lo bits.
-    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
-                                    SDValue(Result, 0), getI32Imm(Lo));
-  } else {
-    // Just the Hi bits.
-    Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
-  }
-
-  // If no shift, we're done.
-  if (!Shift) return Result;
-
-  // If Hi word == Lo word,
-  // we can use rldimi to insert the Lo word into Hi word.
-  if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
-    SDValue Ops[] =
-      { SDValue(Result, 0), SDValue(Result, 0), getI32Imm(Shift), getI32Imm(0)};
-    return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
-  }
-
-  // Shift for next step if the upper 32-bits were not zero.
-  if (Imm) {
-    Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
-                                    SDValue(Result, 0),
-                                    getI32Imm(Shift),
-                                    getI32Imm(63 - Shift));
-  }
-
-  // Add in the last bits as required.
-  if ((Hi = (Remainder >> 16) & 0xFFFF)) {
-    Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
-                                    SDValue(Result, 0), getI32Imm(Hi));
-  }
-  if ((Lo = Remainder & 0xFFFF)) {
-    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
-                                    SDValue(Result, 0), getI32Imm(Lo));
-  }
-
-  return Result;
-}
-
-static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl,
-                            int64_t Imm) {
-  unsigned Count = selectI64ImmInstrCountDirect(Imm);
-
-  // If the instruction count is 1 or 2, we do not need further analysis
-  // since rotate + load constant requires at least 2 instructions.
-  if (Count <= 2)
-    return selectI64ImmDirect(CurDAG, dl, Imm);
-
-  unsigned RMin = 0;
-
-  int64_t MatImm;
-  unsigned MaskEnd;
-
-  for (unsigned r = 1; r < 63; ++r) {
-    uint64_t RImm = Rot64(Imm, r);
-    unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
-    if (RCount < Count) {
-      Count = RCount;
-      RMin = r;
-      MatImm = RImm;
-      MaskEnd = 63;
-    }
-
-    // If the immediate to generate has many trailing zeros, it might be
-    // worthwhile to generate a rotated value with too many leading ones
-    // (because that's free with li/lis's sign-extension semantics), and then
-    // mask them off after rotation.
-
-    unsigned LS = findLastSet(RImm);
-    // We're adding (63-LS) higher-order ones, and we expect to mask them off
-    // after performing the inverse rotation by (64-r). So we need that:
-    //   63-LS == 64-r => LS == r-1
-    if (LS != r-1)
-      continue;
-
-    uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
-    uint64_t RImmWithOnes = RImm | OnesMask;
-
-    RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
-    if (RCount < Count) {
-      Count = RCount;
-      RMin = r;
-      MatImm = RImmWithOnes;
-      MaskEnd = LS;
-    }
-  }
-
-  if (!RMin)
-    return selectI64ImmDirect(CurDAG, dl, Imm);
-
-  auto getI32Imm = [CurDAG, dl](unsigned Imm) {
-      return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
-  };
-
-  SDValue Val = SDValue(selectI64ImmDirect(CurDAG, dl, MatImm), 0);
-  return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
-                                getI32Imm(64 - RMin), getI32Imm(MaskEnd));
-}
-
 static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
   unsigned MaxTruncation = 0;
   // Cannot use range-based for loop here as we need the actual use (i.e. we
@@ -1044,6 +799,273 @@
   return MaxTruncation;
 }
 
+// For any 32 < Num < 64, check if the Imm contains at least Num consecutive
+// zeros and return the number of bits by the left of these consecutive zeros.
+static int findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
+  unsigned HiTZ = countTrailingZeros<uint32_t>(Hi_32(Imm));
+  unsigned LoLZ = countLeadingZeros<uint32_t>(Lo_32(Imm));
+  if ((HiTZ + LoLZ) >= Num)
+    return (32 + HiTZ);
+  return 0;
+}
+
+// Direct materialization of 64-bit constants by enumerated patterns.
+static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
+                                  uint64_t Imm, unsigned &InstCnt) {
+  unsigned TZ = countTrailingZeros<uint64_t>(Imm);
+  unsigned LZ = countLeadingZeros<uint64_t>(Imm);
+  unsigned TO = countTrailingOnes<uint64_t>(Imm);
+  unsigned LO = countLeadingOnes<uint64_t>(Imm);
+  // Count of ones follwing the leading zeros.
+  unsigned FO = countLeadingOnes<uint64_t>(Imm << LZ);
+  unsigned Hi32 = Hi_32(Imm);
+  unsigned Lo32 = Lo_32(Imm);
+  SDNode *Result = nullptr;
+  unsigned Shift = 0;
+
+  auto getI32Imm = [CurDAG, dl](unsigned Imm) {
+    return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
+  };
+
+  // Following patterns use 1 instructions to materialize the Imm.
+  InstCnt = 1;
+  // 1-1) Patterns : {zeros}{15-bit valve}
+  //                 {ones}{15-bit valve}
+  if (isInt<16>(Imm)) {
+    SDValue SDImm = CurDAG->getTargetConstant(Imm, dl, MVT::i64);
+    return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
+  }
+  // 1-2) Patterns : {zeros}{15-bit valve}{16 zeros}
+  //                 {ones}{15-bit valve}{16 zeros}
+  if (TZ > 15 && (LZ > 32 || LO > 32))
+    return CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64,
+                                  getI32Imm((Imm >> 16) & 0xffff));
+
+  // Following patterns use 2 instructions to materialize the Imm.
+  InstCnt = 2;
+  // 2-1) Patterns : {zeros}{31-bit value}
+  //                 {ones}{31-bit value}
+  if (isInt<32>(Imm)) {
+    uint64_t ImmHi16 = (Imm >> 16) & 0xffff;
+    unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
+    Result = CurDAG->getMachineNode(Opcode, dl, MVT::i64, getI32Imm(ImmHi16));
+    return CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(Imm & 0xffff));
+  }
+  // 2-2) Patterns : {zeros}{ones}{15-bit value}{zeros}
+  //                 {zeros}{15-bit value}{zeros}
+  //                 {zeros}{ones}{15-bit value}
+  //                 {ones}{15-bit value}{zeros}
+  // We can take advantage of LI's sign-extension semantics to generate leading
+  // ones, and then use RLDIC to mask off the ones in both sides after rotation.
+  if ((LZ + FO + TZ) > 48) {
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
+                                    getI32Imm((Imm >> TZ) & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(TZ), getI32Imm(LZ));
+  }
+  // 2-3) Pattern : {zeros}{15-bit value}{ones}
+  // Shift right the Imm by (48 - LZ) bits to construct a negtive 16 bits value,
+  // therefore we can take advantage of LI's sign-extension semantics, and then
+  // mask them off after rotation.
+  //
+  // +--LZ--||-15-bit-||--TO--+     +-------------|--16-bit--+
+  // |00000001bbbbbbbbb1111111| ->  |00000000000001bbbbbbbbb1|
+  // +------------------------+     +------------------------+
+  // 63                      0      63                      0
+  //          Imm                   (Imm >> (48 - LZ) & 0xffff)
+  // +----sext-----|--16-bit--+     +clear-|-----------------+
+  // |11111111111111bbbbbbbbb1| ->  |00000001bbbbbbbbb1111111|
+  // +------------------------+     +------------------------+
+  // 63                      0      63                      0
+  // LI8: sext many leading zeros   RLDICL: rotate left (48 - LZ), clear left LZ
+  if ((LZ + TO) > 48) {
+    // Since the immediates with (LZ > 32) have been handled by previous
+    // patterns, here we have (LZ <= 32) to make sure we will not shift right
+    // the Imm by a negative value.
+    assert(LZ <= 32 && "Unexpected shift value.");
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
+                                    getI32Imm((Imm >> (48 - LZ) & 0xffff)));
+    return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(48 - LZ), getI32Imm(LZ));
+  }
+  // 2-4) Patterns : {zeros}{ones}{15-bit value}{ones}
+  //                 {ones}{15-bit value}{ones}
+  // We can take advantage of LI's sign-extension semantics to generate leading
+  // ones, and then use RLDICL to mask off the ones in left sides (if required)
+  // after rotation.
+  //
+  // +-LZ-FO||-15-bit-||--TO--+     +-------------|--16-bit--+
+  // |00011110bbbbbbbbb1111111| ->  |000000000011110bbbbbbbbb|
+  // +------------------------+     +------------------------+
+  // 63                      0      63                      0
+  //            Imm                    (Imm >> TO) & 0xffff
+  // +----sext-----|--16-bit--+     +LZ|---------------------+
+  // |111111111111110bbbbbbbbb| ->  |00011110bbbbbbbbb1111111|
+  // +------------------------+     +------------------------+
+  // 63                      0      63                      0
+  // LI8: sext many leading zeros   RLDICL: rotate left TO, clear left LZ
+  if ((LZ + FO + TO) > 48) {
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
+                                    getI32Imm((Imm >> TO) & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(TO), getI32Imm(LZ));
+  }
+  // 2-5) Pattern : {32 zeros}{****}{0}{15-bit value}
+  // If Hi32 is zero and the Lo16(in Lo32) can be presented as a positive 16 bit
+  // value, we can use LI for Lo16 without generating leading ones then add the
+  // Hi16(in Lo32).
+  if (LZ == 32 && ((Lo32 & 0x8000) == 0)) {
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
+                                    getI32Imm(Lo32 & 0xffff));
+    return CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(Lo32 >> 16));
+  }
+  // 2-6) Patterns : {******}{49 zeros}{******}
+  //                 {******}{49 ones}{******}
+  // If the Imm contains 49 consecutive zeros/ones, it means that a total of 15
+  // bits remain on both sides. Rotate right the Imm to construct an int<16>
+  // value, use LI for int<16> value and then use RLDICL without mask to rotate
+  // it back.
+  //
+  // 1) findContiguousZerosAtLeast(Imm, 49)
+  // +------|--zeros-|------+     +---ones--||---15 bit--+
+  // |bbbbbb0000000000aaaaaa| ->  |0000000000aaaaaabbbbbb|
+  // +----------------------+     +----------------------+
+  // 63                    0      63                    0
+  //
+  // 2) findContiguousZerosAtLeast(~Imm, 49)
+  // +------|--ones--|------+     +---ones--||---15 bit--+
+  // |bbbbbb1111111111aaaaaa| ->  |1111111111aaaaaabbbbbb|
+  // +----------------------+     +----------------------+
+  // 63                    0      63                    0
+  if ((Shift = findContiguousZerosAtLeast(Imm, 49)) ||
+      (Shift = findContiguousZerosAtLeast(~Imm, 49))) {
+    uint64_t RotImm = (Imm >> Shift) | (Imm << (64 - Shift));
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
+                                    getI32Imm(RotImm & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(Shift), getI32Imm(0));
+  }
+
+  // Following patterns use 3 instructions to materialize the Imm.
+  InstCnt = 3;
+  // 3-1) Patterns : {zeros}{ones}{31-bit value}{zeros}
+  //                 {zeros}{31-bit value}{zeros}
+  //                 {zeros}{ones}{31-bit value}
+  //                 {ones}{31-bit value}{zeros}
+  // We can take advantage of LIS's sign-extension semantics to generate leading
+  // ones, add the remaining bits with ORI, and then use RLDIC to mask off the
+  // ones in both sides after rotation.
+  if ((LZ + FO + TZ) > 32) {
+    uint64_t ImmHi16 = (Imm >> (TZ + 16)) & 0xffff;
+    unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
+    Result = CurDAG->getMachineNode(Opcode, dl, MVT::i64, getI32Imm(ImmHi16));
+    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                    getI32Imm((Imm >> TZ) & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(TZ), getI32Imm(LZ));
+  }
+  // 3-2) Pattern : {zeros}{31-bit value}{ones}
+  // Shift right the Imm by (32 - LZ) bits to construct a negtive 32 bits value,
+  // therefore we can take advantage of LIS's sign-extension semantics, add
+  // the remaining bits with ORI, and then mask them off after rotation.
+  // This is similar to Pattern 2-3, please refer to the diagram there.
+  if ((LZ + TO) > 32) {
+    // Since the immediates with (LZ > 32) have been handled by previous
+    // patterns, here we have (LZ <= 32) to make sure we will not shift right
+    // the Imm by a negative value.
+    assert(LZ <= 32 && "Unexpected shift value.");
+    Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64,
+                                    getI32Imm((Imm >> (48 - LZ)) & 0xffff));
+    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                    getI32Imm((Imm >> (32 - LZ)) & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(32 - LZ), getI32Imm(LZ));
+  }
+  // 3-3) Patterns : {zeros}{ones}{31-bit value}{ones}
+  //                 {ones}{31-bit value}{ones}
+  // We can take advantage of LIS's sign-extension semantics to generate leading
+  // ones, add the remaining bits with ORI, and then use RLDICL to mask off the
+  // ones in left sides (if required) after rotation.
+  // This is similar to Pattern 2-4, please refer to the diagram there.
+  if ((LZ + FO + TO) > 32) {
+    Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64,
+                                    getI32Imm((Imm >> (TO + 16)) & 0xffff));
+    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                    getI32Imm((Imm >> TO) & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(TO), getI32Imm(LZ));
+  }
+  // 3-4) Patterns : High word == Low word
+  if (Hi32 == Lo32) {
+    // Handle the first 32 bits.
+    uint64_t ImmHi16 = (Lo32 >> 16) & 0xffff;
+    unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
+    Result = CurDAG->getMachineNode(Opcode, dl, MVT::i64, getI32Imm(ImmHi16));
+    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                    getI32Imm(Lo32 & 0xffff));
+    // Use rldimi to insert the Low word into High word.
+    SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(32),
+                     getI32Imm(0)};
+    return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
+  }
+  // 3-5) Patterns : {******}{33 zeros}{******}
+  //                 {******}{33 ones}{******}
+  // If the Imm contains 33 consecutive zeros/ones, it means that a total of 31
+  // bits remain on both sides. Rotate right the Imm to construct an int<32>
+  // value, use LIS + ORI for int<32> value and then use RLDICL without mask to
+  // rotate it back.
+  // This is similar to Pattern 2-6, please refer to the diagram there.
+  if ((Shift = findContiguousZerosAtLeast(Imm, 33)) ||
+      (Shift = findContiguousZerosAtLeast(~Imm, 33))) {
+    uint64_t RotImm = (Imm >> Shift) | (Imm << (64 - Shift));
+    uint64_t ImmHi16 = (RotImm >> 16) & 0xffff;
+    unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
+    Result = CurDAG->getMachineNode(Opcode, dl, MVT::i64, getI32Imm(ImmHi16));
+    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                    getI32Imm(RotImm & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(Shift), getI32Imm(0));
+  }
+
+  InstCnt = 0;
+  return nullptr;
+}
+
+static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm,
+                            unsigned *InstCnt = nullptr) {
+  unsigned InstCntDirect = 0;
+  // No more than 3 instructions is used if we can select the i64 immediate
+  // directly.
+  SDNode *Result = selectI64ImmDirect(CurDAG, dl, Imm, InstCntDirect);
+  if (Result) {
+    if (InstCnt)
+      *InstCnt = InstCntDirect;
+    return Result;
+  }
+  auto getI32Imm = [CurDAG, dl](unsigned Imm) {
+    return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
+  };
+  // Handle the upper 32 bit value.
+  Result =
+      selectI64ImmDirect(CurDAG, dl, Imm & 0xffffffff00000000, InstCntDirect);
+  // Add in the last bits as required.
+  if (uint32_t Hi16 = (Lo_32(Imm) >> 16) & 0xffff) {
+    Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
+                                    SDValue(Result, 0), getI32Imm(Hi16));
+    ++InstCntDirect;
+  }
+  if (uint32_t Lo16 = Lo_32(Imm) & 0xffff) {
+    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
+                                    getI32Imm(Lo16));
+    ++InstCntDirect;
+  }
+  if (InstCnt)
+    *InstCnt = InstCntDirect;
+  return Result;
+}
+
 // Select a 64-bit constant.
 static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
   SDLoc dl(N);
@@ -2092,11 +2114,14 @@
 
       unsigned NumAndInsts = (unsigned) NeedsRotate +
                              (unsigned) (bool) Res;
+      unsigned NumOfSelectInsts = 0;
+      selectI64Imm(CurDAG, dl, Mask, &NumOfSelectInsts);
+      assert(NumOfSelectInsts > 0 && "Failed to select an i64 constant.");
       if (Use32BitInsts)
         NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
                        (unsigned) (ANDIMask != 0 && ANDISMask != 0);
       else
-        NumAndInsts += selectI64ImmInstrCount(Mask) + /* and */ 1;
+        NumAndInsts += NumOfSelectInsts + /* and */ 1;
 
       unsigned NumRLInsts = 0;
       bool FirstBG = true;
@@ -2320,12 +2345,14 @@
           Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
                           ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
       } else {
-        if (InstCnt) *InstCnt += selectI64ImmInstrCount(Mask) + /* and */ 1;
-
-        SDValue MaskVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
-        Res =
-          SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
-                                         ExtendToInt64(Res, dl), MaskVal), 0);
+        unsigned NumOfSelectInsts = 0;
+        SDValue MaskVal =
+            SDValue(selectI64Imm(CurDAG, dl, Mask, &NumOfSelectInsts), 0);
+        Res = SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
+                                             ExtendToInt64(Res, dl), MaskVal),
+                      0);
+        if (InstCnt)
+          *InstCnt += NumOfSelectInsts + /* and */ 1;
       }
     }
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -241,7 +241,7 @@
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT: renamable $x3 = LI8 1
-; 64BIT: renamable $x5 = RLDICR killed renamable $x3, 31, 32
+; 64BIT: renamable $x5 = RLDIC killed renamable $x3, 31, 32
 ; 64BIT: $x3 = LI8 1
 ; 64BIT: $x4 = LI8 1
 ; 64BIT: $x6 = LIS8 32768
diff --git a/llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll b/llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll
--- a/llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll
+++ b/llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll
@@ -11,8 +11,8 @@
 ; CHECK-LABEL: @bar
 ; CHECK-DAG: li [[REG1:[0-9]+]], 1023
 ; CHECK-DAG: li [[REG2:[0-9]+]], {{1$}}
-; CHECK-DAG: sldi 3, [[REG1]], 52
-; CHECK-DAG: sldi 4, [[REG2]], 62
+; CHECK-DAG: rldic 3, [[REG1]], 52, 2
+; CHECK-DAG: rldic 4, [[REG2]], 62, 1
 ; CHECK: bl xxx
 ; CHECK: blr
 }
diff --git a/llvm/test/CodeGen/PowerPC/bperm.ll b/llvm/test/CodeGen/PowerPC/bperm.ll
--- a/llvm/test/CodeGen/PowerPC/bperm.ll
+++ b/llvm/test/CodeGen/PowerPC/bperm.ll
@@ -47,7 +47,7 @@
 ; CHECK-LABEL: @test1
 ; CHECK-DAG: li [[REG1:[0-9]+]], 11375
 ; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 56
-; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
+; CHECK-DAG: rldic [[REG2:[0-9]+]], [[REG1]], 19, 31
 ; CHECK: and 3, [[REG3]], [[REG2]]
 ; CHECK: blr
 }
@@ -59,10 +59,10 @@
   ret i64 %and
 
 ; CHECK-LABEL: @test2
-; CHECK-DAG: lis [[REG1:[0-9]+]], 474
+; CHECK-DAG: lis [[REG1:[0-9]+]], 7
 ; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 58
-; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648
-; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
+; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 26681
+; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 38, 7
 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
 ; CHECK: and 3, [[REG5]], [[REG4]]
 ; CHECK: blr
@@ -78,7 +78,7 @@
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 170
 ; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 34
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861
-; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
+; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 34, 6
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
@@ -105,7 +105,7 @@
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 3703
 ; CHECK-DAG: rotldi [[REG4:[0-9]+]], 4, 12
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951
-; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
+; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 19, 17
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
@@ -150,7 +150,7 @@
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 4
 ; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 63
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527
-; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
+; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 19, 26
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
@@ -165,12 +165,12 @@
   ret i64 %or4
 
 ; CHECK-LABEL: @test9
-; CHECK-DAG: lis [[REG1:[0-9]+]], 1440
+; CHECK-DAG: lis [[REG1:[0-9]+]], 360
 ; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62
 ; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50
-; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
+; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 1
 ; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0
-; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
+; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 34, 5
 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
 ; CHECK: and 3, [[REG6]], [[REG4]]
 ; CHECK: blr
@@ -190,9 +190,9 @@
 ; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 25
 ; CHECK-DAG: rotldi [[REG7:[0-9]+]], 3, 37
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183
-; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017
-; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25
-; CHECK-DAG: sldi [[REG5:[0-9]+]], [[REG3]], 37
+; CHECK-DAG: li [[REG3:[0-9]+]], -15519
+; CHECK-DAG: rldic [[REG4:[0-9]+]], [[REG2]], 25, 22
+; CHECK-DAG: rldic [[REG5:[0-9]+]], [[REG3]], 37, 10
 ; CHECK-DAG: and [[REG8:[0-9]+]], [[REG6]], [[REG4]]
 ; CHECK-DAG: and [[REG9:[0-9]+]], [[REG7]], [[REG5]]
 ; CHECK: or 3, [[REG9]], [[REG8]]
diff --git a/llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll b/llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll
--- a/llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll
+++ b/llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll
@@ -38,10 +38,9 @@
 define i32 @pattern3(i1 %cond, i32 %x) {
 ; CHECK-LABEL: pattern3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    andi. 3, 3, 1
-; CHECK-NEXT:    oris 3, 5, 65535
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    rldic 3, 5, 0, 32
 ; CHECK-NEXT:    iselgt 3, 0, 3
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -54,10 +53,10 @@
 define i32 @pattern4(i1 %cond, i32 %x) {
 ; CHECK-LABEL: pattern4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    andi. 3, 3, 1
-; CHECK-NEXT:    oris 3, 5, 65535
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    rldic 3, 5, 0, 32
+; CHECK-NEXT:    li 5, 0
 ; CHECK-NEXT:    iselgt 3, 3, 5
 ; CHECK-NEXT:    or 3, 4, 3
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/constants-i64.ll b/llvm/test/CodeGen/PowerPC/constants-i64.ll
--- a/llvm/test/CodeGen/PowerPC/constants-i64.ll
+++ b/llvm/test/CodeGen/PowerPC/constants-i64.ll
@@ -7,8 +7,8 @@
 define i64 @cn1() #0 {
 ; CHECK-LABEL: cn1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, -1
-; CHECK-NEXT:    rldicr 3, 3, 48, 63
+; CHECK-NEXT:    li 3, -1
+; CHECK-NEXT:    rldic 3, 3, 0, 16
 ; CHECK-NEXT:    blr
 entry:
   ret i64 281474976710655
@@ -19,8 +19,8 @@
 define i64 @cnb() #0 {
 ; CHECK-LABEL: cnb:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, -81
-; CHECK-NEXT:    rldicr 3, 3, 48, 63
+; CHECK-NEXT:    li 3, -81
+; CHECK-NEXT:    rldic 3, 3, 0, 16
 ; CHECK-NEXT:    blr
 entry:
   ret i64 281474976710575
@@ -32,7 +32,7 @@
 ; CHECK-LABEL: f2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, -1
-; CHECK-NEXT:    sldi 3, 3, 36
+; CHECK-NEXT:    rldic 3, 3, 36, 0
 ; CHECK-NEXT:    blr
 entry:
   ret i64 -68719476736
@@ -44,7 +44,7 @@
 ; CHECK-LABEL: f2a:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, -337
-; CHECK-NEXT:    sldi 3, 3, 30
+; CHECK-NEXT:    rldic 3, 3, 30, 0
 ; CHECK-NEXT:    blr
 entry:
   ret i64 -361850994688
@@ -55,8 +55,8 @@
 define i64 @f2n(i64 %x) #0 {
 ; CHECK-LABEL: f2n:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, -4096
-; CHECK-NEXT:    rldicr 3, 3, 36, 63
+; CHECK-NEXT:    li 3, -1
+; CHECK-NEXT:    rldic 3, 3, 0, 28
 ; CHECK-NEXT:    blr
 entry:
   ret i64 68719476735
@@ -67,8 +67,8 @@
 define i64 @f3(i64 %x) #0 {
 ; CHECK-LABEL: f3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, -32768
-; CHECK-NEXT:    rldicr 3, 3, 33, 63
+; CHECK-NEXT:    li 3, -1
+; CHECK-NEXT:    rldic 3, 3, 0, 31
 ; CHECK-NEXT:    blr
 entry:
   ret i64 8589934591
@@ -81,7 +81,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 3, -5121
 ; CHECK-NEXT:    ori 3, 3, 65534
-; CHECK-NEXT:    rldicr 3, 3, 22, 63
+; CHECK-NEXT:    rotldi 3, 3, 22
 ; CHECK-NEXT:    blr
 entry:
   ret i64 -1407374887747585
@@ -91,9 +91,8 @@
 define i64 @uint32_1() #0 {
 ; CHECK-LABEL: uint32_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, 232
-; CHECK-NEXT:    ori 3, 3, 30023
-; CHECK-NEXT:    sldi 3, 3, 8
+; CHECK-NEXT:    li 3, 18176
+; CHECK-NEXT:    oris 3, 3, 59509
 ; CHECK-NEXT:    blr
 entry:
   ret i64 3900000000
@@ -103,9 +102,8 @@
 define i32 @uint32_1_i32() #0 {
 ; CHECK-LABEL: uint32_1_i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, 232
-; CHECK-NEXT:    ori 3, 3, 30023
-; CHECK-NEXT:    sldi 3, 3, 8
+; CHECK-NEXT:    li 3, 18176
+; CHECK-NEXT:    oris 3, 3, 59509
 ; CHECK-NEXT:    blr
 entry:
   ret i32 -394967296
@@ -115,9 +113,8 @@
 define i64 @uint32_2() #0 {
 ; CHECK-LABEL: uint32_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    oris 3, 3, 65535
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    li 3, -1
+; CHECK-NEXT:    rldic 3, 3, 0, 32
 ; CHECK-NEXT:    blr
 entry:
   ret i64 4294967295
@@ -127,9 +124,8 @@
 define i32 @uint32_2_i32() #0 {
 ; CHECK-LABEL: uint32_2_i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    oris 3, 3, 65535
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    li 3, -1
+; CHECK-NEXT:    rldic 3, 3, 0, 32
 ; CHECK-NEXT:    blr
 entry:
   ret i32 -1
@@ -140,7 +136,7 @@
 ; CHECK-LABEL: uint32_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    sldi 3, 3, 31
+; CHECK-NEXT:    rldic 3, 3, 31, 32
 ; CHECK-NEXT:    blr
 entry:
   ret i64 2147483648
@@ -150,10 +146,9 @@
 define i64 @uint32_4() #0 {
 ; CHECK-LABEL: uint32_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 29
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 3752
-; CHECK-NEXT:    ori 3, 3, 57376
+; CHECK-NEXT:    lis 3, -6027
+; CHECK-NEXT:    ori 3, 3, 18177
+; CHECK-NEXT:    rldic 3, 3, 5, 27
 ; CHECK-NEXT:    blr
 entry:
   ret i64 124800000032
@@ -163,10 +158,8 @@
 define i64 @cn_ones_1() #0 {
 ; CHECK-LABEL: cn_ones_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 2
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 28543
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    li 3, -25633
+; CHECK-NEXT:    rldicl 3, 3, 18, 30
 ; CHECK-NEXT:    blr
 entry:
   ret i64 10460594175
@@ -176,10 +169,9 @@
 define i64 @cn_ones_2() #0 {
 ; CHECK-LABEL: cn_ones_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 2
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 28521
-; CHECK-NEXT:    ori 3, 3, 32767
+; CHECK-NEXT:    lis 3, -25638
+; CHECK-NEXT:    ori 3, 3, 24575
+; CHECK-NEXT:    rldicl 3, 3, 2, 30
 ; CHECK-NEXT:    blr
 entry:
   ret i64 10459119615
@@ -190,7 +182,7 @@
 ; CHECK-LABEL: imm1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, 8465
-; CHECK-NEXT:    sldi 3, 3, 28
+; CHECK-NEXT:    rldic 3, 3, 28, 22
 ; CHECK-NEXT:    blr
 entry:
   ret i64 2272306135040 ;0x21110000000
@@ -199,9 +191,8 @@
 define i64 @imm2() #0 {
 ; CHECK-LABEL: imm2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    oris 3, 3, 65535
-; CHECK-NEXT:    ori 3, 3, 8465
+; CHECK-NEXT:    li 3, -28536
+; CHECK-NEXT:    rldicl 3, 3, 1, 32
 ; CHECK-NEXT:    blr
 entry:
   ret i64 4294910225 ;0xFFFF2111
@@ -210,9 +201,8 @@
 define i64 @imm3() #0 {
 ; CHECK-LABEL: imm3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    oris 3, 3, 65535
-; CHECK-NEXT:    ori 3, 3, 33041
+; CHECK-NEXT:    li 3, -32495
+; CHECK-NEXT:    rldic 3, 3, 0, 32
 ; CHECK-NEXT:    blr
 entry:
   ret i64 4294934801 ;0xFFFF8111
@@ -233,7 +223,7 @@
 ; CHECK-LABEL: imm5:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, 28685
-; CHECK-NEXT:    rldicr 3, 3, 52, 63
+; CHECK-NEXT:    rotldi 3, 3, 52
 ; CHECK-NEXT:    blr
 entry:
   ret i64 58546795155816455 ;0xd0000000000007
@@ -244,7 +234,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 3, -1
 ; CHECK-NEXT:    ori 3, 3, 28674
-; CHECK-NEXT:    rldicr 3, 3, 52, 63
+; CHECK-NEXT:    rotldi 3, 3, 52
 ; CHECK-NEXT:    blr
 entry:
   ret i64 13510798882111479 ;0x2ffffffffffff7
@@ -253,9 +243,8 @@
 define i64 @imm7() #0 {
 ; CHECK-LABEL: imm7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    ori 3, 3, 61713
-; CHECK-NEXT:    sldi 3, 3, 28
+; CHECK-NEXT:    li 3, -3823
+; CHECK-NEXT:    rldic 3, 3, 28, 20
 ; CHECK-NEXT:    blr
 entry:
   ret i64 16565957296128 ;0xf1110000000
@@ -264,9 +253,8 @@
 define i64 @imm8() #0 {
 ; CHECK-LABEL: imm8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, 15
-; CHECK-NEXT:    ori 3, 3, 57617
-; CHECK-NEXT:    sldi 3, 3, 22
+; CHECK-NEXT:    li 3, -7919
+; CHECK-NEXT:    rldic 3, 3, 22, 22
 ; CHECK-NEXT:    blr
 entry:
   ret i64 4364831817728 ;0x3f844400000
@@ -277,7 +265,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 3, -1
 ; CHECK-NEXT:    ori 3, 3, 28674
-; CHECK-NEXT:    rldicr 3, 3, 52, 63
+; CHECK-NEXT:    rotldi 3, 3, 52
 ; CHECK-NEXT:    blr
 entry:
   ret i64 13510798882111479 ;0x2ffffffffffff7
@@ -286,9 +274,8 @@
 define i64 @imm10() #0 {
 ; CHECK-LABEL: imm10:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    ori 3, 3, 61713
-; CHECK-NEXT:    sldi 3, 3, 28
+; CHECK-NEXT:    li 3, -3823
+; CHECK-NEXT:    rldic 3, 3, 28, 20
 ; CHECK-NEXT:    blr
 entry:
   ret i64 16565957296128 ;0xf1110000000
@@ -297,9 +284,8 @@
 define i64 @imm11() #0 {
 ; CHECK-LABEL: imm11:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, 15
-; CHECK-NEXT:    ori 3, 3, 57617
-; CHECK-NEXT:    sldi 3, 3, 22
+; CHECK-NEXT:    li 3, -7919
+; CHECK-NEXT:    rldic 3, 3, 22, 22
 ; CHECK-NEXT:    blr
 entry:
   ret i64 4364831817728 ;0x3f844400000
@@ -308,10 +294,9 @@
 define i64 @imm12() #0 {
 ; CHECK-LABEL: imm12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 4094
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 16324
-; CHECK-NEXT:    ori 3, 3, 4096
+; CHECK-NEXT:    lis 3, -29
+; CHECK-NEXT:    ori 3, 3, 64577
+; CHECK-NEXT:    rldic 3, 3, 12, 20
 ; CHECK-NEXT:    blr
 entry:
   ret i64 17584665923584 ;0xffe3fc41000
@@ -320,10 +305,8 @@
 define i64 @imm13() #0 {
 ; CHECK-LABEL: imm13:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 19
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 56895
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    li 3, -24847
+; CHECK-NEXT:    rldicl 3, 3, 21, 27
 ; CHECK-NEXT:    blr
 entry:
   ret i64 85333114879 ;0x13de3fffff
@@ -332,10 +315,8 @@
 define i64 @imm13_2() #0 {
 ; CHECK-LABEL: imm13_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 51
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 56895
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    li 3, -12424
+; CHECK-NEXT:    rldicl 3, 3, 22, 26
 ; CHECK-NEXT:    blr
 entry:
   ret i64 222772068351 ;0x33de3fffff
@@ -344,10 +325,8 @@
 define i64 @imm14() #0 {
 ; CHECK-LABEL: imm14:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 254
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 4383
-; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    li 3, -3960
+; CHECK-NEXT:    rldicl 3, 3, 21, 24
 ; CHECK-NEXT:    blr
 entry:
   ret i64 1091209003007 ;0xfe111fffff
@@ -357,7 +336,7 @@
 ; CHECK-LABEL: imm15:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, -8065
-; CHECK-NEXT:    sldi 3, 3, 24
+; CHECK-NEXT:    rldic 3, 3, 24, 0
 ; CHECK-NEXT:    blr
 entry:
   ret i64 -135308247040
@@ -366,9 +345,9 @@
 define i64 @imm16() #0 {
 ; CHECK-LABEL: imm16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, -16392
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    oris 3, 3, 57217
+; CHECK-NEXT:    lis 3, -16392
+; CHECK-NEXT:    ori 3, 3, 57217
+; CHECK-NEXT:    rldic 3, 3, 16, 0
 ; CHECK-NEXT:    blr
 entry:
   ret i64 -70399354142720
@@ -377,9 +356,9 @@
 define i64 @imm17() #0 {
 ; CHECK-LABEL: imm17:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, 158
-; CHECK-NEXT:    sldi 3, 3, 32
-; CHECK-NEXT:    ori 3, 3, 40689
+; CHECK-NEXT:    lis 3, 20344
+; CHECK-NEXT:    ori 3, 3, 32847
+; CHECK-NEXT:    rotldi 3, 3, 49
 ; CHECK-NEXT:    blr
 entry:
   ret i64 44473046320324337 ;0x9e000000009ef1
@@ -388,8 +367,8 @@
 define i64 @imm18() #0 {
 ; CHECK-LABEL: imm18:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 3, 2
-; CHECK-NEXT:    sldi 3, 3, 32
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    rldic 3, 3, 33, 30
 ; CHECK-NEXT:    oris 3, 3, 39436
 ; CHECK-NEXT:    ori 3, 3, 61633
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/f128-fma.ll b/llvm/test/CodeGen/PowerPC/f128-fma.ll
--- a/llvm/test/CodeGen/PowerPC/f128-fma.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-fma.ll
@@ -227,7 +227,7 @@
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r5, 1
 ; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    sldi r5, r5, 63
+; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
 ; CHECK-P8-NEXT:    xor r4, r4, r5
 ; CHECK-P8-NEXT:    std r4, 8(r28)
 ; CHECK-P8-NEXT:    addi r1, r1, 64
@@ -289,7 +289,7 @@
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r5, 1
 ; CHECK-P8-NEXT:    std r3, 0(r30)
-; CHECK-P8-NEXT:    sldi r5, r5, 63
+; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
 ; CHECK-P8-NEXT:    xor r4, r4, r5
 ; CHECK-P8-NEXT:    std r4, 8(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 64
@@ -474,7 +474,7 @@
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r5, 1
 ; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    sldi r5, r5, 63
+; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
 ; CHECK-P8-NEXT:    xor r4, r4, r5
 ; CHECK-P8-NEXT:    std r4, 8(r28)
 ; CHECK-P8-NEXT:    addi r1, r1, 64
@@ -536,7 +536,7 @@
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r5, 1
 ; CHECK-P8-NEXT:    std r3, 0(r30)
-; CHECK-P8-NEXT:    sldi r5, r5, 63
+; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
 ; CHECK-P8-NEXT:    xor r4, r4, r5
 ; CHECK-P8-NEXT:    std r4, 8(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 64
diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
--- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
@@ -18,7 +18,7 @@
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r3, 1
 ; CHECK-P8-NEXT:    ori r3, r3, 5
-; CHECK-P8-NEXT:    sldi r4, r3, 46
+; CHECK-P8-NEXT:    rldic r4, r3, 46, 1
 ; CHECK-P8-NEXT:    li r3, 0
 ; CHECK-P8-NEXT:    blr
   entry:
@@ -47,7 +47,7 @@
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    lis r5, 1
 ; CHECK-P8-NEXT:    ori r5, r5, 5
-; CHECK-P8-NEXT:    sldi r6, r5, 46
+; CHECK-P8-NEXT:    rldic r6, r5, 46, 1
 ; CHECK-P8-NEXT:    li r5, 0
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll b/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
@@ -22,9 +22,9 @@
 ; CHECK-NEXT:    paddi r3, 0, .L.str@PCREL, 1
 ; CHECK-NEXT:    bl printf@notoc
 ; CHECK-NEXT:    ld r4, 104(r1)
-; CHECK-NEXT:    lis r3, 16403
-; CHECK-NEXT:    ori r3, r3, 62914
-; CHECK-NEXT:    sldi r3, r3, 32
+; CHECK-NEXT:    lis r3, 8201
+; CHECK-NEXT:    ori r3, r3, 64225
+; CHECK-NEXT:    rldic r3, r3, 33, 1
 ; CHECK-NEXT:    oris r3, r3, 36700
 ; CHECK-NEXT:    ori r3, r3, 10486
 ; CHECK-NEXT:    std r3, 0(r4)
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
--- a/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
@@ -158,7 +158,7 @@
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    li r9, 1
-; CHECK-P8-NEXT:    sldi r9, r9, 63
+; CHECK-P8-NEXT:    rldic r9, r9, 63, 0
 ; CHECK-P8-NEXT:    xor r8, r8, r9
 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
@@ -191,7 +191,7 @@
 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r5, 1
-; CHECK-P8-NEXT:    sldi r5, r5, 63
+; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
 ; CHECK-P8-NEXT:    xor r4, r4, r5
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
@@ -222,7 +222,7 @@
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    li r9, 1
-; CHECK-P8-NEXT:    sldi r30, r9, 63
+; CHECK-P8-NEXT:    rldic r30, r9, 63, 0
 ; CHECK-P8-NEXT:    xor r8, r8, r30
 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -68,7 +68,7 @@
 ; PPC64-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; PPC64-NEXT:    li 4, 1
 ; PPC64-NEXT:    lfs 0, .LCPI2_0@toc@l(3)
-; PPC64-NEXT:    sldi 4, 4, 63
+; PPC64-NEXT:    rldic 4, 4, 63, 0
 ; PPC64-NEXT:    fsubs 2, 1, 0
 ; PPC64-NEXT:    fcmpu 0, 1, 0
 ; PPC64-NEXT:    fctidz 2, 2
@@ -150,7 +150,7 @@
 ; PPC64-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; PPC64-NEXT:    li 4, 1
 ; PPC64-NEXT:    lfs 0, .LCPI3_0@toc@l(3)
-; PPC64-NEXT:    sldi 4, 4, 63
+; PPC64-NEXT:    rldic 4, 4, 63, 0
 ; PPC64-NEXT:    fsub 2, 1, 0
 ; PPC64-NEXT:    fcmpu 0, 1, 0
 ; PPC64-NEXT:    fctidz 2, 2
@@ -161,7 +161,7 @@
 ; PPC64-NEXT:    ld 5, -16(1)
 ; PPC64-NEXT:    xor 3, 3, 4
 ; PPC64-NEXT:    li 4, 1107
-; PPC64-NEXT:    sldi 4, 4, 52
+; PPC64-NEXT:    rldic 4, 4, 52, 1
 ; PPC64-NEXT:    bc 12, 0, .LBB3_1
 ; PPC64-NEXT:    b .LBB3_2
 ; PPC64-NEXT:  .LBB3_1: # %entry
@@ -173,7 +173,7 @@
 ; PPC64-NEXT:    addis 5, 2, .LCPI3_1@toc@ha
 ; PPC64-NEXT:    std 4, -24(1)
 ; PPC64-NEXT:    li 4, 1075
-; PPC64-NEXT:    sldi 4, 4, 52
+; PPC64-NEXT:    rldic 4, 4, 52, 1
 ; PPC64-NEXT:    or 3, 3, 4
 ; PPC64-NEXT:    lfd 0, .LCPI3_1@toc@l(5)
 ; PPC64-NEXT:    std 3, -32(1)
diff --git a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
--- a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
+++ b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
@@ -45,7 +45,7 @@
 ; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]])
 ; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]]) 
 ; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
-; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63
+; PPC64-DAG: rldic [[FLIP_BIT]], [[FLIP_BIT]], 63, 0
 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
 ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
 ; PPC64-NOT: BARRIER
@@ -57,7 +57,7 @@
 ; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
 ; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
-; PPC64-P8-DAG: sldi [[FLIP_BIT:[0-9]+]], [[IMM1]], 63
+; PPC64-P8-DAG: rldic [[FLIP_BIT:[0-9]+]], [[IMM1]], 63, 0
 ; PPC64-P8-NOT: BARRIER
 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
@@ -85,8 +85,8 @@
 ; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
 ; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
 ; PPC64-NOT: BARRIER
-; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
-; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
+; PPC64-DAG: rldic [[CST_HI:[0-9]+]], [[HI_TMP]], 48, 1
+; PPC64-DAG: rldic [[CST_LO:[0-9]+]], [[LO_TMP]], 52, 0
 ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
 ; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
 ; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
@@ -98,8 +98,8 @@
 ; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
 ; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
 ; PPC64-P8-NOT: BARRIER
-; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
-; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
+; PPC64-P8-DAG: rldic [[CST_HI:[0-9]+]], [[HI_TMP]], 48, 1
+; PPC64-P8-DAG: rldic [[CST_LO:[0-9]+]], [[LO_TMP]], 52, 0
 ; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
 ; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
 ; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
--- a/llvm/test/CodeGen/PowerPC/funnel-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
@@ -227,10 +227,10 @@
 ;
 ; CHECK64-LABEL: fshl_i37:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    lis 6, -8857
+; CHECK64-NEXT:    lis 6, 28339
 ; CHECK64-NEXT:    sldi 4, 4, 27
-; CHECK64-NEXT:    ori 6, 6, 51366
-; CHECK64-NEXT:    sldi 6, 6, 32
+; CHECK64-NEXT:    ori 6, 6, 58451
+; CHECK64-NEXT:    rldic 6, 6, 33, 0
 ; CHECK64-NEXT:    oris 6, 6, 3542
 ; CHECK64-NEXT:    ori 6, 6, 31883
 ; CHECK64-NEXT:    mulhdu 6, 5, 6
@@ -540,10 +540,10 @@
 ;
 ; CHECK64-LABEL: fshr_i37:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    lis 6, -8857
+; CHECK64-NEXT:    lis 6, 28339
 ; CHECK64-NEXT:    sldi 4, 4, 27
-; CHECK64-NEXT:    ori 6, 6, 51366
-; CHECK64-NEXT:    sldi 6, 6, 32
+; CHECK64-NEXT:    ori 6, 6, 58451
+; CHECK64-NEXT:    rldic 6, 6, 33, 0
 ; CHECK64-NEXT:    oris 6, 6, 3542
 ; CHECK64-NEXT:    ori 6, 6, 31883
 ; CHECK64-NEXT:    mulhdu 6, 5, 6
diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
--- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -127,14 +127,14 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ldx 4, 0, 3
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    sldi 5, 5, 32
+; CHECK-NEXT:    rldic 5, 5, 32, 31
 ; CHECK-NEXT:    cmpld 4, 5
 ; CHECK-NEXT:    bne 0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1: # %loadbb1
-; CHECK-NEXT:    li 4, 3
+; CHECK-NEXT:    lis 4, -32768
 ; CHECK-NEXT:    ld 3, 8(3)
-; CHECK-NEXT:    sldi 4, 4, 32
-; CHECK-NEXT:    ori 4, 4, 2
+; CHECK-NEXT:    ori 4, 4, 1
+; CHECK-NEXT:    rldic 4, 4, 1, 30
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    beq 0, .LBB6_3
diff --git a/llvm/test/CodeGen/PowerPC/negctr.ll b/llvm/test/CodeGen/PowerPC/negctr.ll
--- a/llvm/test/CodeGen/PowerPC/negctr.ll
+++ b/llvm/test/CodeGen/PowerPC/negctr.ll
@@ -15,10 +15,9 @@
   br i1 %exitcond, label %for.end, label %for.body
 
 ; CHECK: @main
-; CHECK: li [[REG:[0-9]+]], 0
-; CHECK: oris [[REG2:[0-9]+]], [[REG]], 65535
-; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
-; CHECK: mtctr [[REG3]]
+; CHECK: li [[REG:[0-9]+]], -1
+; CHECK: rldic [[REG2:[0-9]+]], [[REG]], 0, 32
+; CHECK: mtctr [[REG2]]
 ; CHECK: bdnz
 
 for.end:                                          ; preds = %for.body, %entry
diff --git a/llvm/test/CodeGen/PowerPC/ori_imm32.ll b/llvm/test/CodeGen/PowerPC/ori_imm32.ll
--- a/llvm/test/CodeGen/PowerPC/ori_imm32.ll
+++ b/llvm/test/CodeGen/PowerPC/ori_imm32.ll
@@ -70,7 +70,7 @@
 ; CHECK-LABEL: xori_test_b:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    sldi 4, 4, 32
+; CHECK-NEXT:    rldic 4, 4, 32, 31
 ; CHECK-NEXT:    xor 3, 3, 4
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/ori_imm64.ll b/llvm/test/CodeGen/PowerPC/ori_imm64.ll
--- a/llvm/test/CodeGen/PowerPC/ori_imm64.ll
+++ b/llvm/test/CodeGen/PowerPC/ori_imm64.ll
@@ -37,10 +37,9 @@
 define i64 @ori_test_4(i64 %a) {
 ; CHECK-LABEL: ori_test_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 4, 4112
-; CHECK-NEXT:    sldi 4, 4, 32
-; CHECK-NEXT:    oris 4, 4, 4112
-; CHECK-NEXT:    ori 4, 4, 65535
+; CHECK-NEXT:    lis 4, -32640
+; CHECK-NEXT:    ori 4, 4, 32903
+; CHECK-NEXT:    rldicl 4, 4, 13, 19
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    blr
 entry:
@@ -53,7 +52,7 @@
 ; CHECK-LABEL: test_test_5:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    sldi 5, 5, 32
+; CHECK-NEXT:    rldic 5, 5, 32, 31
 ; CHECK-NEXT:    or 5, 3, 5
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    sub 3, 3, 4
diff --git a/llvm/test/CodeGen/PowerPC/pr43976.ll b/llvm/test/CodeGen/PowerPC/pr43976.ll
--- a/llvm/test/CodeGen/PowerPC/pr43976.ll
+++ b/llvm/test/CodeGen/PowerPC/pr43976.ll
@@ -13,7 +13,7 @@
 ; CHECK-NEXT:    li r4, 1
 ; CHECK-NEXT:    lfd f0, a@toc@l(r3)
 ; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    sldi r4, r4, 63
+; CHECK-NEXT:    rldic r4, r4, 63, 0
 ; CHECK-NEXT:    lfs f1, .LCPI0_0@toc@l(r3)
 ; CHECK-NEXT:    fsub f2, f0, f1
 ; CHECK-NEXT:    fctidz f2, f2
diff --git a/llvm/test/CodeGen/PowerPC/pr45448.ll b/llvm/test/CodeGen/PowerPC/pr45448.ll
--- a/llvm/test/CodeGen/PowerPC/pr45448.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45448.ll
@@ -19,12 +19,11 @@
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_7
 ; CHECK-NEXT:  .LBB0_6: # %L1057.preheader
 ; CHECK-NEXT:  .LBB0_7: # %L670
-; CHECK-NEXT:    lis r5, 4095
+; CHECK-NEXT:    li r5, -3
 ; CHECK-NEXT:    cmpdi r3, 0
 ; CHECK-NEXT:    sradi r4, r3, 63
-; CHECK-NEXT:    ori r5, r5, 65533
+; CHECK-NEXT:    rldic r5, r5, 4, 32
 ; CHECK-NEXT:    crnot 4*cr5+gt, eq
-; CHECK-NEXT:    sldi r5, r5, 4
 ; CHECK-NEXT:    mulhdu r3, r3, r5
 ; CHECK-NEXT:    maddld r6, r4, r5, r3
 ; CHECK-NEXT:    cmpld r6, r3
diff --git a/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll b/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
--- a/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
+++ b/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
@@ -27,106 +27,107 @@
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    .cfi_offset r31, -8
 ; CHECK-NEXT:    .cfi_offset r2, -152
-; CHECK-NEXT:    lis 5, 4
+; CHECK-NEXT:    lis 5, 1
 ; CHECK-NEXT:    std 30, 704(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 29, 696(1) # 8-byte Folded Spill
-; CHECK-NEXT:    ori 6, 5, 6292
+; CHECK-NEXT:    ori 5, 5, 1573
 ; CHECK-NEXT:    std 28, 688(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 27, 680(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 26, 672(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 25, 664(1) # 8-byte Folded Spill
-; CHECK-NEXT:    ori 5, 5, 6291
 ; CHECK-NEXT:    std 14, 576(1) # 8-byte Folded Spill
+; CHECK-NEXT:    rldic 5, 5, 34, 13
 ; CHECK-NEXT:    std 15, 584(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 16, 592(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 17, 600(1) # 8-byte Folded Spill
+; CHECK-NEXT:    oris 6, 5, 13030
+; CHECK-NEXT:    oris 7, 5, 13066
+; CHECK-NEXT:    oris 8, 5, 13054
+; CHECK-NEXT:    oris 9, 5, 13042
+; CHECK-NEXT:    oris 10, 5, 13078
+; CHECK-NEXT:    oris 11, 5, 13115
+; CHECK-NEXT:    oris 12, 5, 13103
+; CHECK-NEXT:    oris 0, 5, 13091
+; CHECK-NEXT:    oris 30, 5, 13127
+; CHECK-NEXT:    oris 29, 5, 13164
+; CHECK-NEXT:    oris 28, 5, 13152
+; CHECK-NEXT:    oris 27, 5, 13139
+; CHECK-NEXT:    oris 26, 5, 13176
+; CHECK-NEXT:    ori 6, 6, 3704
+; CHECK-NEXT:    ori 7, 7, 44408
+; CHECK-NEXT:    ori 8, 8, 30840
+; CHECK-NEXT:    ori 9, 9, 17272
+; CHECK-NEXT:    ori 10, 10, 57976
+; CHECK-NEXT:    ori 11, 11, 33144
+; CHECK-NEXT:    ori 12, 12, 19576
+; CHECK-NEXT:    ori 0, 0, 6008
+; CHECK-NEXT:    ori 30, 30, 46712
+; CHECK-NEXT:    ori 29, 29, 21880
+; CHECK-NEXT:    ori 28, 28, 8312
+; CHECK-NEXT:    ori 27, 27, 60280
+; CHECK-NEXT:    ori 26, 26, 35448
 ; CHECK-NEXT:    std 18, 608(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 6
 ; CHECK-NEXT:    std 19, 616(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 20, 624(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 21, 632(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 22, 640(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 23, 648(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 24, 656(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 25, 664(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 31, 712(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 2, 568(1) # 8-byte Folded Spill
-; CHECK-NEXT:    sldi 6, 6, 32
-; CHECK-NEXT:    oris 7, 6, 13030
-; CHECK-NEXT:    oris 8, 6, 13066
-; CHECK-NEXT:    oris 9, 6, 13054
-; CHECK-NEXT:    oris 10, 6, 13042
-; CHECK-NEXT:    oris 11, 6, 13078
-; CHECK-NEXT:    oris 12, 6, 13115
-; CHECK-NEXT:    oris 0, 6, 13103
-; CHECK-NEXT:    oris 30, 6, 13091
-; CHECK-NEXT:    oris 29, 6, 13127
-; CHECK-NEXT:    oris 28, 6, 13164
-; CHECK-NEXT:    oris 27, 6, 13152
-; CHECK-NEXT:    oris 26, 6, 13139
-; CHECK-NEXT:    oris 25, 6, 13176
-; CHECK-NEXT:    ori 7, 7, 3704
-; CHECK-NEXT:    ori 8, 8, 44408
-; CHECK-NEXT:    ori 9, 9, 30840
-; CHECK-NEXT:    ori 10, 10, 17272
-; CHECK-NEXT:    ori 11, 11, 57976
-; CHECK-NEXT:    ori 12, 12, 33144
-; CHECK-NEXT:    ori 0, 0, 19576
-; CHECK-NEXT:    ori 30, 30, 6008
-; CHECK-NEXT:    ori 29, 29, 46712
-; CHECK-NEXT:    ori 28, 28, 21880
-; CHECK-NEXT:    ori 27, 27, 8312
-; CHECK-NEXT:    ori 26, 26, 60280
-; CHECK-NEXT:    ori 25, 25, 35448
-; CHECK-NEXT:    add 7, 4, 7
-; CHECK-NEXT:    sldi 5, 5, 32
-; CHECK-NEXT:    oris 5, 5, 29347
-; CHECK-NEXT:    ori 5, 5, 20088
-; CHECK-NEXT:    std 7, 384(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 8
+; CHECK-NEXT:    std 6, 384(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 7
+; CHECK-NEXT:    lis 7, 354
+; CHECK-NEXT:    std 6, 376(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 8
 ; CHECK-NEXT:    lis 8, 402
-; CHECK-NEXT:    std 7, 376(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 9
+; CHECK-NEXT:    std 6, 368(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 9
 ; CHECK-NEXT:    lis 9, 451
-; CHECK-NEXT:    std 7, 368(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 10
+; CHECK-NEXT:    std 6, 360(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 10
 ; CHECK-NEXT:    lis 10, 500
-; CHECK-NEXT:    std 7, 360(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 11
+; CHECK-NEXT:    std 6, 352(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 11
 ; CHECK-NEXT:    lis 11, 549
-; CHECK-NEXT:    std 7, 352(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 12
-; CHECK-NEXT:    std 7, 344(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 0
-; CHECK-NEXT:    std 7, 336(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 30
-; CHECK-NEXT:    std 7, 328(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 29
-; CHECK-NEXT:    std 7, 320(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 28
-; CHECK-NEXT:    std 7, 312(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 27
-; CHECK-NEXT:    std 7, 304(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 26
-; CHECK-NEXT:    std 7, 296(1) # 8-byte Folded Spill
-; CHECK-NEXT:    add 7, 4, 25
-; CHECK-NEXT:    std 7, 288(1) # 8-byte Folded Spill
-; CHECK-NEXT:    oris 7, 6, 13213
-; CHECK-NEXT:    ori 7, 7, 10616
-; CHECK-NEXT:    add 7, 4, 7
-; CHECK-NEXT:    std 7, 280(1) # 8-byte Folded Spill
-; CHECK-NEXT:    oris 7, 6, 13200
-; CHECK-NEXT:    oris 6, 6, 13188
-; CHECK-NEXT:    ori 7, 7, 62584
-; CHECK-NEXT:    ori 6, 6, 49016
-; CHECK-NEXT:    add 7, 4, 7
+; CHECK-NEXT:    std 6, 344(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 12
+; CHECK-NEXT:    std 6, 336(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 0
+; CHECK-NEXT:    std 6, 328(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 30
+; CHECK-NEXT:    std 6, 320(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 29
+; CHECK-NEXT:    std 6, 312(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 28
+; CHECK-NEXT:    std 6, 304(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 27
+; CHECK-NEXT:    std 6, 296(1) # 8-byte Folded Spill
+; CHECK-NEXT:    add 6, 4, 26
+; CHECK-NEXT:    std 6, 288(1) # 8-byte Folded Spill
+; CHECK-NEXT:    oris 6, 5, 13213
+; CHECK-NEXT:    ori 6, 6, 10616
 ; CHECK-NEXT:    add 6, 4, 6
+; CHECK-NEXT:    std 6, 280(1) # 8-byte Folded Spill
+; CHECK-NEXT:    oris 6, 5, 13200
+; CHECK-NEXT:    oris 5, 5, 13188
+; CHECK-NEXT:    ori 5, 5, 49016
+; CHECK-NEXT:    ori 6, 6, 62584
+; CHECK-NEXT:    add 5, 4, 5
+; CHECK-NEXT:    add 6, 4, 6
+; CHECK-NEXT:    std 5, 264(1) # 8-byte Folded Spill
+; CHECK-NEXT:    lis 5, 4
+; CHECK-NEXT:    std 6, 272(1) # 8-byte Folded Spill
+; CHECK-NEXT:    lis 6, 305
+; CHECK-NEXT:    ori 5, 5, 6291
+; CHECK-NEXT:    rldic 5, 5, 32, 13
+; CHECK-NEXT:    oris 5, 5, 29347
+; CHECK-NEXT:    ori 5, 5, 20088
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    lis 5, 268
 ; CHECK-NEXT:    std 4, 256(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    lis 4, 585
-; CHECK-NEXT:    std 6, 264(1) # 8-byte Folded Spill
-; CHECK-NEXT:    lis 6, 305
-; CHECK-NEXT:    std 7, 272(1) # 8-byte Folded Spill
-; CHECK-NEXT:    lis 7, 354
 ; CHECK-NEXT:    ori 4, 4, 61440
 ; CHECK-NEXT:    std 4, 560(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    lis 4, 48
diff --git a/llvm/test/CodeGen/PowerPC/sms-grp-order.ll b/llvm/test/CodeGen/PowerPC/sms-grp-order.ll
--- a/llvm/test/CodeGen/PowerPC/sms-grp-order.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-grp-order.ll
@@ -4,24 +4,24 @@
 
 define void @lame_encode_buffer_interleaved() local_unnamed_addr {
 ; CHECK-LABEL: lame_encode_buffer_interleaved:
-; CHECK:      # %bb.0:
-; CHECK-NEXT:   lha 3, 0(3)
-; CHECK-NEXT:   li 5, 1
-; CHECK-NEXT:   lhz 4, 0(0)
-; CHECK-NEXT:   sldi 5, 5, 62
-; CHECK-NEXT:   mtctr 5
-; CHECK-NEXT:   srawi 3, 3, 1
-; CHECK-NEXT:   addze 3, 3
-; CHECK-NEXT:   .p2align 4
-; CHECK-NEXT: .LBB0_1:
-; CHECK-NEXT:   extsh 4, 4
-; CHECK-NEXT:   srawi 4, 4, 1
-; CHECK-NEXT:   addze 4, 4
-; CHECK-NEXT:   bdnz .LBB0_1
-; CHECK-NEXT: # %bb.2:
-; CHECK-NEXT:   sth 4, 0(0)
-; CHECK-NEXT:   sth 3, 0(3)
-; CHECK-NEXT:   blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lha 3, 0(3)
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    lhz 4, 0(0)
+; CHECK-NEXT:    rldic 5, 5, 62, 1
+; CHECK-NEXT:    mtctr 5
+; CHECK-NEXT:    srawi 3, 3, 1
+; CHECK-NEXT:    addze 3, 3
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:    extsh 4, 4
+; CHECK-NEXT:    srawi 4, 4, 1
+; CHECK-NEXT:    addze 4, 4
+; CHECK-NEXT:    bdnz .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    sth 4, 0(0)
+; CHECK-NEXT:    sth 3, 0(3)
+; CHECK-NEXT:    blr
   br label %1
 
 1:                                                ; preds = %1, %0
diff --git a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
@@ -1289,20 +1289,20 @@
 define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
 ; P9LE-LABEL: dont_fold_srem_i64:
 ; P9LE:       # %bb.0:
-; P9LE-NEXT:    lis r4, 24749
+; P9LE-NEXT:    lis r4, 12374
 ; P9LE-NEXT:    mfvsrd r3, v3
-; P9LE-NEXT:    ori r4, r4, 47142
-; P9LE-NEXT:    sldi r4, r4, 32
+; P9LE-NEXT:    ori r4, r4, 56339
+; P9LE-NEXT:    rldic r4, r4, 33, 1
 ; P9LE-NEXT:    oris r4, r4, 58853
 ; P9LE-NEXT:    ori r4, r4, 6055
 ; P9LE-NEXT:    mulhd r4, r3, r4
 ; P9LE-NEXT:    rldicl r5, r4, 1, 63
 ; P9LE-NEXT:    sradi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
-; P9LE-NEXT:    lis r5, -19946
+; P9LE-NEXT:    lis r5, 5698
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    ori r5, r5, 17096
-; P9LE-NEXT:    sldi r5, r5, 32
+; P9LE-NEXT:    ori r5, r5, 51289
+; P9LE-NEXT:    rldic r5, r5, 35, 0
 ; P9LE-NEXT:    oris r5, r5, 22795
 ; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mfvsrld r4, v3
@@ -1315,10 +1315,10 @@
 ; P9LE-NEXT:    mulli r5, r5, 23
 ; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    mtvsrdd v3, r3, r4
-; P9LE-NEXT:    lis r4, 25653
+; P9LE-NEXT:    lis r4, 3206
 ; P9LE-NEXT:    mfvsrd r3, v2
-; P9LE-NEXT:    ori r4, r4, 15432
-; P9LE-NEXT:    sldi r4, r4, 32
+; P9LE-NEXT:    ori r4, r4, 42889
+; P9LE-NEXT:    rldic r4, r4, 35, 1
 ; P9LE-NEXT:    oris r4, r4, 1603
 ; P9LE-NEXT:    ori r4, r4, 21445
 ; P9LE-NEXT:    mulhd r4, r3, r4
@@ -1333,20 +1333,20 @@
 ;
 ; P9BE-LABEL: dont_fold_srem_i64:
 ; P9BE:       # %bb.0:
-; P9BE-NEXT:    lis r4, 24749
+; P9BE-NEXT:    lis r4, 12374
 ; P9BE-NEXT:    mfvsrld r3, v3
-; P9BE-NEXT:    ori r4, r4, 47142
-; P9BE-NEXT:    sldi r4, r4, 32
+; P9BE-NEXT:    ori r4, r4, 56339
+; P9BE-NEXT:    rldic r4, r4, 33, 1
 ; P9BE-NEXT:    oris r4, r4, 58853
 ; P9BE-NEXT:    ori r4, r4, 6055
 ; P9BE-NEXT:    mulhd r4, r3, r4
 ; P9BE-NEXT:    rldicl r5, r4, 1, 63
 ; P9BE-NEXT:    sradi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
-; P9BE-NEXT:    lis r5, -19946
-; P9BE-NEXT:    ori r5, r5, 17096
+; P9BE-NEXT:    lis r5, 5698
+; P9BE-NEXT:    ori r5, r5, 51289
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    sldi r5, r5, 32
+; P9BE-NEXT:    rldic r5, r5, 35, 0
 ; P9BE-NEXT:    oris r5, r5, 22795
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mfvsrd r4, v3
@@ -1359,10 +1359,10 @@
 ; P9BE-NEXT:    mulli r5, r5, 23
 ; P9BE-NEXT:    sub r4, r4, r5
 ; P9BE-NEXT:    mtvsrdd v3, r4, r3
-; P9BE-NEXT:    lis r4, 25653
+; P9BE-NEXT:    lis r4, 3206
 ; P9BE-NEXT:    mfvsrld r3, v2
-; P9BE-NEXT:    ori r4, r4, 15432
-; P9BE-NEXT:    sldi r4, r4, 32
+; P9BE-NEXT:    ori r4, r4, 42889
+; P9BE-NEXT:    rldic r4, r4, 35, 1
 ; P9BE-NEXT:    oris r4, r4, 1603
 ; P9BE-NEXT:    ori r4, r4, 21445
 ; P9BE-NEXT:    mulhd r4, r3, r4
@@ -1376,18 +1376,18 @@
 ;
 ; P8LE-LABEL: dont_fold_srem_i64:
 ; P8LE:       # %bb.0:
-; P8LE-NEXT:    lis r3, 24749
-; P8LE-NEXT:    lis r4, -19946
-; P8LE-NEXT:    lis r5, 25653
+; P8LE-NEXT:    lis r3, 12374
+; P8LE-NEXT:    lis r4, 5698
+; P8LE-NEXT:    lis r5, 3206
 ; P8LE-NEXT:    xxswapd vs0, v3
 ; P8LE-NEXT:    mfvsrd r6, v3
-; P8LE-NEXT:    ori r3, r3, 47142
-; P8LE-NEXT:    ori r4, r4, 17096
-; P8LE-NEXT:    ori r5, r5, 15432
+; P8LE-NEXT:    ori r3, r3, 56339
+; P8LE-NEXT:    ori r4, r4, 51289
+; P8LE-NEXT:    ori r5, r5, 42889
 ; P8LE-NEXT:    mfvsrd r7, v2
-; P8LE-NEXT:    sldi r3, r3, 32
-; P8LE-NEXT:    sldi r4, r4, 32
-; P8LE-NEXT:    sldi r5, r5, 32
+; P8LE-NEXT:    rldic r3, r3, 33, 1
+; P8LE-NEXT:    rldic r4, r4, 35, 0
+; P8LE-NEXT:    rldic r5, r5, 35, 1
 ; P8LE-NEXT:    oris r3, r3, 58853
 ; P8LE-NEXT:    oris r4, r4, 22795
 ; P8LE-NEXT:    mffprd r8, f0
@@ -1425,19 +1425,19 @@
 ;
 ; P8BE-LABEL: dont_fold_srem_i64:
 ; P8BE:       # %bb.0:
-; P8BE-NEXT:    lis r4, -19946
-; P8BE-NEXT:    lis r3, 24749
+; P8BE-NEXT:    lis r4, 5698
+; P8BE-NEXT:    lis r3, 12374
 ; P8BE-NEXT:    xxswapd vs0, v3
-; P8BE-NEXT:    lis r5, 25653
+; P8BE-NEXT:    lis r5, 3206
 ; P8BE-NEXT:    xxswapd vs1, v2
-; P8BE-NEXT:    ori r4, r4, 17096
-; P8BE-NEXT:    ori r3, r3, 47142
-; P8BE-NEXT:    ori r5, r5, 15432
+; P8BE-NEXT:    ori r4, r4, 51289
+; P8BE-NEXT:    ori r3, r3, 56339
+; P8BE-NEXT:    ori r5, r5, 42889
 ; P8BE-NEXT:    mfvsrd r6, v3
-; P8BE-NEXT:    sldi r4, r4, 32
-; P8BE-NEXT:    sldi r3, r3, 32
+; P8BE-NEXT:    rldic r4, r4, 35, 0
+; P8BE-NEXT:    rldic r3, r3, 33, 1
 ; P8BE-NEXT:    oris r4, r4, 22795
-; P8BE-NEXT:    sldi r5, r5, 32
+; P8BE-NEXT:    rldic r5, r5, 35, 1
 ; P8BE-NEXT:    oris r3, r3, 58853
 ; P8BE-NEXT:    mffprd r7, f0
 ; P8BE-NEXT:    ori r4, r4, 8549
diff --git a/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll b/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
--- a/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
+++ b/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
@@ -68,9 +68,9 @@
   ; CHECK-NEXT: stdu r1, -48(r1)
   ; CHECK-NEXT: mr r30, r3
   ; CHECK-NEXT: bl callee
-  ; CHECK-NEXT: lis r3, 16404
-  ; CHECK-NEXT: ori r3, r3, 52428
-  ; CHECK-NEXT: sldi r3, r3, 32
+  ; CHECK-NEXT: lis r3, 4101
+  ; CHECK-NEXT: ori r3, r3, 13107
+  ; CHECK-NEXT: rldic r3, r3, 34, 1
   ; CHECK-NEXT: oris r3, r3, 52428
   ; CHECK-NEXT: ori r3, r3, 52429
   ; CHECK-NEXT: std r3, 0(r30)
diff --git a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
--- a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
+++ b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
@@ -80,15 +80,16 @@
 ; CHECK-NEXT:    li r5, 3
 ; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
-; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB4_1: # %for.body
-; CHECK:         ldu r6, 8(r4)
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldu r6, 8(r4)
 ; CHECK-NEXT:    ldx r7, r4, r5
 ; CHECK-NEXT:    maddld r3, r7, r6, r3
 ; CHECK-NEXT:    bdnz .LBB4_1
 ; CHECK-NEXT:  # %bb.2: # %for.end
 ; CHECK-NEXT:    blr
+; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
 entry:
   br label %for.body
 
diff --git a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
@@ -1022,10 +1022,10 @@
 define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
 ; P9LE-LABEL: dont_fold_urem_i64:
 ; P9LE:       # %bb.0:
-; P9LE-NEXT:    lis r4, 25644
+; P9LE-NEXT:    lis r4, 1602
 ; P9LE-NEXT:    mfvsrld r3, v3
-; P9LE-NEXT:    ori r4, r4, 34192
-; P9LE-NEXT:    sldi r4, r4, 32
+; P9LE-NEXT:    ori r4, r4, 51289
+; P9LE-NEXT:    rldic r4, r4, 36, 1
 ; P9LE-NEXT:    oris r4, r4, 45590
 ; P9LE-NEXT:    ori r4, r4, 17097
 ; P9LE-NEXT:    mulhdu r4, r3, r4
@@ -1036,7 +1036,7 @@
 ; P9LE-NEXT:    rldicl r4, r4, 60, 4
 ; P9LE-NEXT:    ori r5, r5, 28749
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    sldi r5, r5, 32
+; P9LE-NEXT:    rldic r5, r5, 32, 0
 ; P9LE-NEXT:    oris r5, r5, 52170
 ; P9LE-NEXT:    ori r5, r5, 12109
 ; P9LE-NEXT:    sub r3, r3, r4
@@ -1045,11 +1045,11 @@
 ; P9LE-NEXT:    rldicl r5, r5, 52, 12
 ; P9LE-NEXT:    mulli r5, r5, 5423
 ; P9LE-NEXT:    sub r4, r4, r5
-; P9LE-NEXT:    lis r5, 25653
-; P9LE-NEXT:    ori r5, r5, 15432
+; P9LE-NEXT:    lis r5, 3206
+; P9LE-NEXT:    ori r5, r5, 42889
 ; P9LE-NEXT:    mtvsrdd v3, r4, r3
 ; P9LE-NEXT:    mfvsrd r3, v2
-; P9LE-NEXT:    sldi r5, r5, 32
+; P9LE-NEXT:    rldic r5, r5, 35, 1
 ; P9LE-NEXT:    rldicl r4, r3, 63, 1
 ; P9LE-NEXT:    oris r5, r5, 1603
 ; P9LE-NEXT:    ori r5, r5, 21445
@@ -1063,10 +1063,10 @@
 ;
 ; P9BE-LABEL: dont_fold_urem_i64:
 ; P9BE:       # %bb.0:
-; P9BE-NEXT:    lis r4, 25644
+; P9BE-NEXT:    lis r4, 1602
 ; P9BE-NEXT:    mfvsrd r3, v3
-; P9BE-NEXT:    ori r4, r4, 34192
-; P9BE-NEXT:    sldi r4, r4, 32
+; P9BE-NEXT:    ori r4, r4, 51289
+; P9BE-NEXT:    rldic r4, r4, 36, 1
 ; P9BE-NEXT:    oris r4, r4, 45590
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    mulhdu r4, r3, r4
@@ -1077,7 +1077,7 @@
 ; P9BE-NEXT:    rldicl r4, r4, 60, 4
 ; P9BE-NEXT:    ori r5, r5, 28749
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    sldi r5, r5, 32
+; P9BE-NEXT:    rldic r5, r5, 32, 0
 ; P9BE-NEXT:    oris r5, r5, 52170
 ; P9BE-NEXT:    ori r5, r5, 12109
 ; P9BE-NEXT:    sub r3, r3, r4
@@ -1086,11 +1086,11 @@
 ; P9BE-NEXT:    rldicl r5, r5, 52, 12
 ; P9BE-NEXT:    mulli r5, r5, 5423
 ; P9BE-NEXT:    sub r4, r4, r5
-; P9BE-NEXT:    lis r5, 25653
-; P9BE-NEXT:    ori r5, r5, 15432
+; P9BE-NEXT:    lis r5, 3206
+; P9BE-NEXT:    ori r5, r5, 42889
 ; P9BE-NEXT:    mtvsrdd v3, r3, r4
 ; P9BE-NEXT:    mfvsrld r3, v2
-; P9BE-NEXT:    sldi r5, r5, 32
+; P9BE-NEXT:    rldic r5, r5, 35, 1
 ; P9BE-NEXT:    rldicl r4, r3, 63, 1
 ; P9BE-NEXT:    oris r5, r5, 1603
 ; P9BE-NEXT:    ori r5, r5, 21445
@@ -1103,20 +1103,20 @@
 ;
 ; P8LE-LABEL: dont_fold_urem_i64:
 ; P8LE:       # %bb.0:
-; P8LE-NEXT:    lis r3, 25644
+; P8LE-NEXT:    lis r3, 1602
 ; P8LE-NEXT:    xxswapd vs0, v3
 ; P8LE-NEXT:    lis r4, -16037
-; P8LE-NEXT:    lis r5, 25653
+; P8LE-NEXT:    lis r5, 3206
 ; P8LE-NEXT:    mfvsrd r6, v2
-; P8LE-NEXT:    ori r3, r3, 34192
+; P8LE-NEXT:    ori r3, r3, 51289
 ; P8LE-NEXT:    ori r4, r4, 28749
-; P8LE-NEXT:    ori r5, r5, 15432
+; P8LE-NEXT:    ori r5, r5, 42889
 ; P8LE-NEXT:    mfvsrd r8, v3
-; P8LE-NEXT:    sldi r3, r3, 32
-; P8LE-NEXT:    sldi r4, r4, 32
+; P8LE-NEXT:    rldic r3, r3, 36, 1
+; P8LE-NEXT:    rldic r4, r4, 32, 0
 ; P8LE-NEXT:    oris r3, r3, 45590
 ; P8LE-NEXT:    mffprd r7, f0
-; P8LE-NEXT:    sldi r5, r5, 32
+; P8LE-NEXT:    rldic r5, r5, 35, 1
 ; P8LE-NEXT:    oris r4, r4, 52170
 ; P8LE-NEXT:    ori r3, r3, 17097
 ; P8LE-NEXT:    oris r5, r5, 1603
@@ -1149,19 +1149,19 @@
 ;
 ; P8BE-LABEL: dont_fold_urem_i64:
 ; P8BE:       # %bb.0:
-; P8BE-NEXT:    lis r3, 25644
+; P8BE-NEXT:    lis r3, 1602
 ; P8BE-NEXT:    lis r4, -16037
 ; P8BE-NEXT:    xxswapd vs0, v3
 ; P8BE-NEXT:    xxswapd vs1, v2
-; P8BE-NEXT:    lis r5, 25653
-; P8BE-NEXT:    ori r3, r3, 34192
+; P8BE-NEXT:    lis r5, 3206
+; P8BE-NEXT:    ori r3, r3, 51289
 ; P8BE-NEXT:    ori r4, r4, 28749
 ; P8BE-NEXT:    mfvsrd r6, v3
-; P8BE-NEXT:    ori r5, r5, 15432
-; P8BE-NEXT:    sldi r3, r3, 32
-; P8BE-NEXT:    sldi r4, r4, 32
+; P8BE-NEXT:    ori r5, r5, 42889
+; P8BE-NEXT:    rldic r3, r3, 36, 1
+; P8BE-NEXT:    rldic r4, r4, 32, 0
 ; P8BE-NEXT:    oris r3, r3, 45590
-; P8BE-NEXT:    sldi r5, r5, 32
+; P8BE-NEXT:    rldic r5, r5, 35, 1
 ; P8BE-NEXT:    mffprd r7, f0
 ; P8BE-NEXT:    oris r4, r4, 52170
 ; P8BE-NEXT:    ori r3, r3, 17097