[AMDGPU][MC] Corrected error position for invalid MOVREL src

[dp]

Summary

See bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSOPLiteral(const MCInst &Inst) const;
   bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
   bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector &Operands);
   bool validateIntClampSupported(const MCInst &Inst);
   bool validateMIMGAtomicDMask(const MCInst &Inst);
   bool validateMIMGGatherDMask(const MCInst &Inst);
-  bool validateMovrels(const MCInst &Inst);
+  bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
   bool validateMIMGDataSize(const MCInst &Inst);
   bool validateMIMGAddrSize(const MCInst &Inst);
   bool validateMIMGD16(const MCInst &Inst);
   bool validateMIMGDim(const MCInst &Inst);
   bool validateLdsDirect(const MCInst &Inst);
   bool validateOpSel(const MCInst &Inst);
   bool validateVccOperand(unsigned Reg) const;
   bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands);
static bool IsMovrelsSDWAOpcode(const unsigned Opcode)
   default:
     return false;
   }
 }
 
 // movrels* opcodes should only allow VGPRS as src0.
 // This is specified in .td description for vop1/vop3,
 // but sdwa is handled differently. See isSDWAOperand.
-bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) {
+bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,
+                                      const OperandVector &Operands) {
 
   const unsigned Opc = Inst.getOpcode();
   const MCInstrDesc &Desc = MII.get(Opc);
 
   if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc))
     return true;
 
   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
   assert(Src0Idx != -1);
 
+  SMLoc ErrLoc;
   const MCOperand &Src0 = Inst.getOperand(Src0Idx);
-  if (!Src0.isReg())
-    return false;
-
-  auto Reg = Src0.getReg();
+  if (Src0.isReg()) {
+    auto Reg = mc2PseudoReg(Src0.getReg());
     const MCRegisterInfo *TRI = getContext().getRegisterInfo();
-  return !isSGPR(mc2PseudoReg(Reg), TRI);
+    if (!isSGPR(Reg, TRI))
+      return true;
+    ErrLoc = getRegLoc(Reg, Operands);
+  } else {
+    ErrLoc = getConstLoc(Operands);
+  }
+
+  Error(ErrLoc, "source operand must be a VGPR");
+  return false;
 }
 
 bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
                                           const OperandVector &Operands) {
 
   const unsigned Opc = Inst.getOpcode();
 
   if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)
Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
       "invalid atomic image dmask");
     return false;
   }
   if (!validateMIMGGatherDMask(Inst)) {
     Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
       "invalid image_gather dmask: only one bit must be set");
     return false;
   }
-  if (!validateMovrels(Inst)) {
-    Error(IDLoc, "source operand must be a VGPR");
+  if (!validateMovrels(Inst, Operands)) {
     return false;
   }
   if (!validateFlatOffset(Inst, Operands)) {
     return false;
   }
   if (!validateSMEMOffset(Inst, Operands)) {
     return false;
   }
case Match_MissingFeature:
     // mnemonic is valid. A match was found but it requires
     // features which are not supported on this GPU.
     return Error(IDLoc, "operands are not valid for this GPU or mode");
 
   case Match_InvalidOperand: {
     SMLoc ErrorLoc = IDLoc;
     if (ErrorInfo != ~0ULL) {
       if (ErrorInfo >= Operands.size()) {
-        return Error(IDLoc, "too few operands for instruction");
+        return Error(getLoc(), "too few operands for instruction");
       }
       ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
       if (ErrorLoc == SMLoc())
         ErrorLoc = IDLoc;
     }
     return Error(ErrorLoc, "invalid operand for instruction");
   }
 

llvm/test/MC/AMDGPU/exp-err.s

 
 exp 0 v3, v2, v1, v0
 // GCN: :5: error: invalid operand for instruction
 
 exp , v3, v2, v1, v0
 // GCN: :5: error: unknown token in expression
 
 exp
-// GCN: :1: error: too few operands for instruction
+// GCN: :4: error: too few operands for instruction
 
 exp mrt0 s0, v0, v0, v0
 // GCN: 10: error: invalid operand for instruction
 
 exp mrt0 v0, s0, v0, v0
 // GCN: 14: error: invalid operand for instruction
 
 exp mrt0 v0, v0, s0, v0

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 // CHECK-NEXT:{{^}}                        ^
 
 //==============================================================================
 // source operand must be a VGPR
 
 v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: error: source operand must be a VGPR
 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                       ^
 
+v_movrels_b32_sdwa v0, s0
+// CHECK: error: source operand must be a VGPR
+// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s0
+// CHECK-NEXT:{{^}}                       ^
+
+v_movrels_b32_sdwa v0, shared_base
+// CHECK: error: source operand must be a VGPR
+// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, shared_base
+// CHECK-NEXT:{{^}}                       ^
+
 //==============================================================================
 // specified hardware register is not supported on this GPU
 
 s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
 // CHECK: error: specified hardware register is not supported on this GPU
 // CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
 // CHECK-NEXT:{{^}}                       ^
 
 //==============================================================================
 // too few operands for instruction
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
 // CHECK: error: too few operands for instruction
 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                                ^
 
 v_add_f32_e64 v0, v1
 // CHECK: error: too few operands for instruction
 // CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                    ^
 
 //==============================================================================
 // too large value for expcnt
 
 s_waitcnt expcnt(8)
 // CHECK: error: too large value for expcnt
 // CHECK-NEXT:{{^}}s_waitcnt expcnt(8)
 // CHECK-NEXT:{{^}}                 ^