diff --git a/lld/ELF/Arch/X86_64.cpp b/lld/ELF/Arch/X86_64.cpp
--- a/lld/ELF/Arch/X86_64.cpp
+++ b/lld/ELF/Arch/X86_64.cpp
@@ -730,7 +730,12 @@
 
 RelExpr X86_64::adjustGotPcExpr(RelType type, int64_t addend,
                                 const uint8_t *loc) const {
-  if (type != R_X86_64_GOTPCRELX && type != R_X86_64_REX_GOTPCRELX)
+  // Only R_X86_64_[REX_]GOTPCRELX can be relaxed. addend != -4 means the
+  // instruction does not load the full GOT entry, we cannot relax the
+  // relocation. E.g. movl x@GOTPCREL+4(%rip), %rax (addend=0) loads the high 32
+  // bits of the GOT entry.
+  if ((type != R_X86_64_GOTPCRELX && type != R_X86_64_REX_GOTPCRELX) ||
+      addend != -4)
     return R_GOT_PC;
   const uint8_t op = loc[-2];
   const uint8_t modRm = loc[-1];
diff --git a/lld/test/ELF/x86-64-gotpc-offset.s b/lld/test/ELF/x86-64-gotpc-offset.s
new file mode 100644
--- /dev/null
+++ b/lld/test/ELF/x86-64-gotpc-offset.s
@@ -0,0 +1,18 @@
+# REQUIRES: x86
+# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -s -d %t | FileCheck %s
+
+# CHECK:      Contents of section .got:
+# CHECK-NEXT:  2021a0 9d112000 00000000
+
+## The second instruction has an offset (addend!=-4). It is incorrect to relax
+## movl to leal.
+# CHECK:      leaq 6(%rip), %rax  # {{.*}} <foo>
+# CHECK-NEXT: movl {{.*}}(%rip), %eax  # 2021a4
+  movq foo@GOTPCREL(%rip), %rax
+  movl foo@GOTPCREL+4(%rip), %eax
+
+.globl foo
+foo:
+  nop