This ports the AArch64 SABD and USBD over to DAG Combine, where they can be used by more backends (notably MVE in a follow-up patch). The matching code has changed very little, just to handle legal operations and types differently. It selects from (ABS (SUB (EXTEND a), (EXTEND b))), producing a ubds/abdu which is zexted to the original type.
Thanks for taking a look.
What other archs have equivalent instructions?
It was MVE I was hoping to share this with, over in the ARM backend. I don't know if any other backend would find this useful too - it would be great if they did. I find it hard enough to know what ARM instructions do some of the time let along other architectures! I believe the X86 instruction (PSADBW) works quite differently, as it includes a reduction step?
Yeah - sum-of-abs-diff is a bit more complex - technically we could use ABD as a stepping stone in pattern matching it
Add comments showing both ADDS and ADDU patterns
naming consistency - combineAbsToAbd or combineABSToABD
Aye, I agree. Sorry I have not gotten back to this yet, and didn't have time over the weekend to update it. I'll try and do so soon.
I did happen to talk to someone how implemented the same thing in gcc and apparently they represent it as max(a, b) - min(a, b). Which I thought was nifty but does show how the whole thing can be commutative.
I still need to do something with D91921 before it can be used with MVE. I was working on that, but it was a bit slow going and other things had come up in the meantime. I was looking at it recently to try and improve trunc/extend lowering, but need to get some time to sort through that properly. There is also some stuff to do with the way that MVE wants to do lane interleaving that I thought might be an issue, but I'm pretty sure that will be fine.
This part can go in if we need it I think. But the MVE side won't be working well yet, and so there won't be another user other than AArch64.