Index: lldb/trunk/include/lldb/Core/ArchSpec.h =================================================================== --- lldb/trunk/include/lldb/Core/ArchSpec.h +++ lldb/trunk/include/lldb/Core/ArchSpec.h @@ -32,6 +32,23 @@ class ArchSpec { public: + enum MIPSSubType + { + eMIPSSubType_unknown, + eMIPSSubType_mips32, + eMIPSSubType_mips32r2, + eMIPSSubType_mips32r6, + eMIPSSubType_mips32el, + eMIPSSubType_mips32r2el, + eMIPSSubType_mips32r6el, + eMIPSSubType_mips64, + eMIPSSubType_mips64r2, + eMIPSSubType_mips64r6, + eMIPSSubType_mips64el, + eMIPSSubType_mips64r2el, + eMIPSSubType_mips64r6el, + }; + enum Core { eCore_arm_generic, @@ -66,8 +83,26 @@ eCore_arm_armv8, eCore_arm_aarch64, + eCore_mips32, + eCore_mips32r2, + eCore_mips32r3, + eCore_mips32r5, + eCore_mips32r6, + eCore_mips32el, + eCore_mips32r2el, + eCore_mips32r3el, + eCore_mips32r5el, + eCore_mips32r6el, eCore_mips64, + eCore_mips64r2, + eCore_mips64r3, + eCore_mips64r5, + eCore_mips64r6, eCore_mips64el, + eCore_mips64r2el, + eCore_mips64r3el, + eCore_mips64r5el, + eCore_mips64r6el, eCore_ppc_generic, eCore_ppc_ppc601, Index: lldb/trunk/source/Core/ArchSpec.cpp =================================================================== --- lldb/trunk/source/Core/ArchSpec.cpp +++ lldb/trunk/source/Core/ArchSpec.cpp @@ -89,8 +89,29 @@ { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8 , "armv8" }, { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" }, - { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" }, - { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" }, + // mips32, mips32r2, mips32r3, mips32r5, mips32r6 + { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips32" }, + { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mips32r2" }, + { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mips32r3" }, + { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mips32r5" }, + { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mips32r6" }, + { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mips32el" }, + { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mips32r2el" }, + { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mips32r3el" }, + { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mips32r5el" }, + { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mips32r6el" }, + + // mips64, mips64r2, mips64r3, mips64r5, mips64r6 + { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" }, + { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" }, + { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" }, + { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" }, + { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" }, + { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" }, + { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" }, + { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" }, + { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" }, + { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" }, { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "powerpc" }, { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" }, @@ -269,8 +290,18 @@ { ArchSpec::eCore_arm_aarch64 , llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM64 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64 - { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , llvm::Triple::mips64, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64 - { ArchSpec::eCore_mips64el , llvm::ELF::EM_MIPS , llvm::Triple::mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64el + { ArchSpec::eCore_mips32 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32 + { ArchSpec::eCore_mips32r2 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r2 + { ArchSpec::eCore_mips32r6 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r6 + { ArchSpec::eCore_mips32el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32el + { ArchSpec::eCore_mips32r2el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r2el + { ArchSpec::eCore_mips32r6el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r6el + { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64 + { ArchSpec::eCore_mips64r2 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r2 + { ArchSpec::eCore_mips64r6 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r6 + { ArchSpec::eCore_mips64el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64el + { ArchSpec::eCore_mips64r2el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r2el + { ArchSpec::eCore_mips64r6el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r6el { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // HEXAGON { ArchSpec::eCore_kalimba3 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA { ArchSpec::eCore_kalimba4 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA Index: lldb/trunk/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp =================================================================== --- lldb/trunk/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp +++ lldb/trunk/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp @@ -382,10 +382,11 @@ // FreeBSD and NetBSD (need to validate other OSes). // http://svnweb.freebsd.org/base/head/sys/sys/link_elf.h?revision=217153&view=markup#l57 const ArchSpec &arch = m_process->GetTarget().GetArchitecture(); - if (arch.GetCore() == ArchSpec::eCore_mips64) + if ((arch.GetTriple().getOS() == llvm::Triple::FreeBSD + || arch.GetTriple().getOS() == llvm::Triple::NetBSD) && + (arch.GetMachine() == llvm::Triple::mips || arch.GetMachine() == llvm::Triple::mipsel + || arch.GetMachine() == llvm::Triple::mips64 || arch.GetMachine() == llvm::Triple::mips64el)) { - assert (arch.GetTriple().getOS() == llvm::Triple::FreeBSD || - arch.GetTriple().getOS() == llvm::Triple::NetBSD); addr_t mips_l_offs; if (!(addr = ReadPointer(addr, &mips_l_offs))) return false; Index: lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp =================================================================== --- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -76,7 +76,8 @@ { if (EmulateInstructionMIPS64::SupportsEmulatingInstructionsOfTypeStatic(inst_type)) { - if (arch.GetTriple().getArch() == llvm::Triple::mips64) + if (arch.GetTriple().getArch() == llvm::Triple::mips64 + || arch.GetTriple().getArch() == llvm::Triple::mips64el) { std::auto_ptr emulate_insn_ap (new EmulateInstructionMIPS64 (arch)); if (emulate_insn_ap.get()) @@ -90,7 +91,8 @@ bool EmulateInstructionMIPS64::SetTargetTriple (const ArchSpec &arch) { - if (arch.GetTriple().getArch () == llvm::Triple::mips64) + if (arch.GetTriple().getArch () == llvm::Triple::mips64 + || arch.GetTriple().getArch () == llvm::Triple::mips64el) return true; return false; } Index: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp =================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -286,17 +286,22 @@ mipsVariantFromElfFlags(const elf::elf_word e_flags, uint32_t endian) { const uint32_t mips_arch = e_flags & llvm::ELF::EF_MIPS_ARCH; - uint32_t arch_variant = LLDB_INVALID_CPUTYPE; + uint32_t arch_variant = ArchSpec::eMIPSSubType_unknown; switch (mips_arch) { + case llvm::ELF::EF_MIPS_ARCH_32: + return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips32el : ArchSpec::eMIPSSubType_mips32; + case llvm::ELF::EF_MIPS_ARCH_32R2: + return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips32r2el : ArchSpec::eMIPSSubType_mips32r2; + case llvm::ELF::EF_MIPS_ARCH_32R6: + return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips32r6el : ArchSpec::eMIPSSubType_mips32r6; case llvm::ELF::EF_MIPS_ARCH_64: - if (endian == ELFDATA2LSB) - arch_variant = llvm::Triple::mips64el; - else - arch_variant = llvm::Triple::mips64; - break; - + return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips64el : ArchSpec::eMIPSSubType_mips64; + case llvm::ELF::EF_MIPS_ARCH_64R2: + return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips64r2el : ArchSpec::eMIPSSubType_mips64r2; + case llvm::ELF::EF_MIPS_ARCH_64R6: + return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips64r6el : ArchSpec::eMIPSSubType_mips64r6; default: break; } Index: lldb/trunk/source/Plugins/Process/Linux/NativeProcessLinux.cpp =================================================================== --- lldb/trunk/source/Plugins/Process/Linux/NativeProcessLinux.cpp +++ lldb/trunk/source/Plugins/Process/Linux/NativeProcessLinux.cpp @@ -3559,6 +3559,7 @@ // set per architecture. Need ARM, MIPS support here. static const uint8_t g_aarch64_opcode[] = { 0x00, 0x00, 0x20, 0xd4 }; static const uint8_t g_i386_opcode [] = { 0xCC }; + static const uint8_t g_mips64_opcode[] = { 0x00, 0x00, 0x00, 0x0d }; switch (m_arch.GetMachine ()) { @@ -3575,6 +3576,11 @@ actual_opcode_size = static_cast (sizeof(g_i386_opcode)); return Error (); + case llvm::Triple::mips64: + case llvm::Triple::mips64el: + actual_opcode_size = static_cast (sizeof(g_mips64_opcode)); + return Error (); + default: assert(false && "CPU type not supported!"); return Error ("CPU type not supported"); Index: lldb/trunk/source/Target/Thread.cpp =================================================================== --- lldb/trunk/source/Target/Thread.cpp +++ lldb/trunk/source/Target/Thread.cpp @@ -2321,6 +2321,7 @@ case llvm::Triple::aarch64: case llvm::Triple::thumb: case llvm::Triple::mips64: + case llvm::Triple::mips64el: case llvm::Triple::ppc: case llvm::Triple::ppc64: case llvm::Triple::hexagon: