diff --git a/llvm/lib/Target/VE/VEFrameLowering.h b/llvm/lib/Target/VE/VEFrameLowering.h --- a/llvm/lib/Target/VE/VEFrameLowering.h +++ b/llvm/lib/Target/VE/VEFrameLowering.h @@ -39,8 +39,9 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override; - bool hasBP(const MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const override; + bool hasBP(const MachineFunction &MF) const; + // VE reserves argument space always for call sites in the function // immediately on entry of the current function. bool hasReservedCallFrame(const MachineFunction &MF) const override { diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp b/llvm/lib/Target/VE/VEFrameLowering.cpp --- a/llvm/lib/Target/VE/VEFrameLowering.cpp +++ b/llvm/lib/Target/VE/VEFrameLowering.cpp @@ -198,6 +198,7 @@ void VEFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { + const VEMachineFunctionInfo *FuncInfo = MF.getInfo(); assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); MachineFrameInfo &MFI = MF.getFrameInfo(); const VEInstrInfo &TII = *STI.getInstrInfo(); @@ -234,6 +235,9 @@ // Update stack size with corrected value. MFI.setStackSize(NumBytes); + if (FuncInfo->isLeafProc()) + return; + // Emit Prologue instructions to save multiple registers. emitPrologueInsns(MF, MBB, MBBI, NumBytes, true); @@ -283,20 +287,22 @@ void VEFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + const VEMachineFunctionInfo *FuncInfo = MF.getInfo(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineFrameInfo &MFI = MF.getFrameInfo(); uint64_t NumBytes = MFI.getStackSize(); + if (FuncInfo->isLeafProc()) + return; + // Emit Epilogue instructions to restore multiple registers. emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true); } // hasFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas -// or if frame pointer elimination is disabled. For the case of VE, we don't -// implement FP eliminator yet, but we returns false from this function to -// not refer fp from generated code. +// or if frame pointer elimination is disabled. bool VEFrameLowering::hasFP(const MachineFunction &MF) const { const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); @@ -318,22 +324,19 @@ Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const VERegisterInfo *RegInfo = STI.getRegisterInfo(); - const VEMachineFunctionInfo *FuncInfo = MF.getInfo(); bool isFixed = MFI.isFixedObjectIndex(FI); int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI); - if (FuncInfo->isLeafProc()) { - // If there's a leaf proc, all offsets need to be %sp-based, - // because we haven't caused %fp to actually point to our frame. + if (!hasFP(MF)) { + // If FP is not used, frame indexies are based on a %sp regiter. FrameReg = VE::SX11; // %sp return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize()); } if (RegInfo->needsStackRealignment(MF) && !isFixed) { - // If there is dynamic stack realignment, all local object - // references need to be via %sp or %s17 (bp), to take account - // of the re-alignment. + // If data on stack require realignemnt, frame indexies are based on a %sp + // or %s17 (bp) register. If there is a variable sized object, bp is used. if (hasBP(MF)) FrameReg = VE::SX17; // %bp else @@ -341,7 +344,7 @@ return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize()); } - // Finally, default to using %fp. + // Use %fp by default. FrameReg = RegInfo->getFrameRegister(MF); return StackOffset::getFixed(FrameOffset); } @@ -362,9 +365,12 @@ BitVector &SavedRegs, RegScavenger *RS) const { TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); + const MachineFrameInfo &MFI = MF.getFrameInfo(); - if (isLeafProc(MF)) { - VEMachineFunctionInfo *MFI = MF.getInfo(); - MFI->setLeafProc(true); + // Functions having BP or stack objects need to emit prologue and epilogue + // to allocate local buffer on the stack. + if (isLeafProc(MF) && !hasBP(MF) && !MFI.hasStackObjects()) { + VEMachineFunctionInfo *FuncInfo = MF.getInfo(); + FuncInfo->setLeafProc(true); } } diff --git a/llvm/test/CodeGen/VE/Scalar/addition.ll b/llvm/test/CodeGen/VE/Scalar/addition.ll --- a/llvm/test/CodeGen/VE/Scalar/addition.ll +++ b/llvm/test/CodeGen/VE/Scalar/addition.ll @@ -2,48 +2,48 @@ define signext i8 @func8s(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i8 %1, %0 ret i8 %3 } define signext i16 @func16s(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i16 %1, %0 ret i16 %3 } define signext i32 @func32s(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add nsw i32 %1, %0 ret i32 %3 } define i64 @func64s(i64 %0, i64 %1) { ; CHECK-LABEL: func64s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.l %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add nsw i64 %1, %0 ret i64 %3 } define i128 @func128s(i128 %0, i128 %1) { ; CHECK-LABEL: func128s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.l %s1, %s3, %s1 ; CHECK-NEXT: adds.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s2, %s0, %s2 @@ -51,53 +51,53 @@ ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2 ; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1 ; CHECK-NEXT: adds.l %s1, %s1, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add nsw i128 %1, %0 ret i128 %3 } define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i8 %1, %0 ret i8 %3 } define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i16 %1, %0 ret i16 %3 } define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i32 %1, %0 ret i32 %3 } define i64 @func64z(i64 %0, i64 %1) { ; CHECK-LABEL: func64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.l %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i64 %1, %0 ret i64 %3 } define i128 @func128z(i128 %0, i128 %1) { ; CHECK-LABEL: func128z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.l %s1, %s3, %s1 ; CHECK-NEXT: adds.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s2, %s0, %s2 @@ -105,55 +105,55 @@ ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2 ; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1 ; CHECK-NEXT: adds.l %s1, %s1, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = add i128 %1, %0 ret i128 %3 } define signext i8 @funci8s(i8 signext %0) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i8 %0, 5 ret i8 %2 } define signext i16 @funci16s(i16 signext %0) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i16 %0, 5 ret i16 %2 } define signext i32 @funci32s(i32 signext %0) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i32 %0, 5 ret i32 %2 } define i64 @funci64s(i64 %0) { ; CHECK-LABEL: funci64s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 5(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i64 %0, 5 ret i64 %2 } define i128 @funci128s(i128 %0) { ; CHECK-LABEL: funci128s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 5(, %s0) ; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -161,53 +161,53 @@ ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.l %s1, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i128 %0, 5 ret i128 %2 } define zeroext i8 @funci8z(i8 zeroext %0) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i8 %0, 5 ret i8 %2 } define zeroext i16 @funci16z(i16 zeroext %0) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i16 %0, 5 ret i16 %2 } define zeroext i32 @funci32z(i32 zeroext %0) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i32 %0, 5 ret i32 %2 } define i64 @funci64z(i64 %0) { ; CHECK-LABEL: funci64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 5(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i64 %0, 5 ret i64 %2 } define i128 @funci128z(i128 %0) { ; CHECK-LABEL: funci128z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 5(, %s0) ; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -215,25 +215,25 @@ ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.l %s1, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i128 %0, 5 ret i128 %2 } define i64 @funci64_2(i64 %0) { ; CHECK-LABEL: funci64_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: adds.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i64 %0, 2147483648 ret i64 %2 } define i128 @funci128_2(i128 %0) { ; CHECK-LABEL: funci128_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: adds.l %s2, %s0, %s2 @@ -243,7 +243,7 @@ ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.l %s1, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i128 %0, 2147483648 ret i128 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/and.ll b/llvm/test/CodeGen/VE/Scalar/and.ll --- a/llvm/test/CodeGen/VE/Scalar/and.ll +++ b/llvm/test/CodeGen/VE/Scalar/and.ll @@ -2,146 +2,146 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i8 %a, %b ret i8 %res } define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i8 %b, %a ret i8 %res } define signext i8 @funci8s(i8 signext %a) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i8 %a, 5 ret i8 %res } define zeroext i8 @funci8z(i8 zeroext %a) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i8 -5, %a ret i8 %res } define signext i16 @func16s(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i16 %a, %b ret i16 %res } define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i16 %b, %a ret i16 %res } define signext i16 @funci16s(i16 signext %a) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %res = and i16 %a, 65535 ret i16 %res } define zeroext i16 @funci16z(i16 zeroext %a) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (52)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i16 4095, %a ret i16 %res } define signext i32 @func32s(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i32 %a, %b ret i32 %res } define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i32 %a, %b ret i32 %res } define signext i32 @funci32s(i32 signext %a) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i32 %a, 268435455 ret i32 %res } define zeroext i32 @funci32z(i32 zeroext %a) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i32 %a, 268435455 ret i32 %res } define i64 @func64(i64 %a, i64 %b) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i64 %a, %b ret i64 %res } define i64 @func64i(i64 %a) { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (24)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i64 %a, 1099511627775 ret i64 %res } define i128 @func128(i128 %a, i128 %b) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s2, %s0 ; CHECK-NEXT: and %s1, %s3, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i128 %b, %a ret i128 %res } define i128 @funci128(i128 %a) { ; CHECK-LABEL: funci128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, 5, %s0 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = and i128 %a, 5 ret i128 %res } diff --git a/llvm/test/CodeGen/VE/Scalar/atomic_fence.ll b/llvm/test/CodeGen/VE/Scalar/atomic_fence.ll --- a/llvm/test/CodeGen/VE/Scalar/atomic_fence.ll +++ b/llvm/test/CodeGen/VE/Scalar/atomic_fence.ll @@ -5,17 +5,17 @@ ; Function Attrs: norecurse nounwind readnone define void @_Z20atomic_fence_relaxedv() { ; CHECK-LABEL: _Z20atomic_fence_relaxedv: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret void } ; Function Attrs: nofree norecurse nounwind define void @_Z20atomic_fence_consumev() { ; CHECK-LABEL: _Z20atomic_fence_consumev: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) fence acquire ret void } @@ -23,9 +23,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z20atomic_fence_acquirev() { ; CHECK-LABEL: _Z20atomic_fence_acquirev: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) fence acquire ret void } @@ -33,9 +33,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z20atomic_fence_releasev() { ; CHECK-LABEL: _Z20atomic_fence_releasev: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) fence release ret void } @@ -43,9 +43,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z20atomic_fence_acq_relv() { ; CHECK-LABEL: _Z20atomic_fence_acq_relv: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) fence acq_rel ret void } @@ -53,9 +53,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z20atomic_fence_seq_cstv() { ; CHECK-LABEL: _Z20atomic_fence_seq_cstv: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) fence seq_cst ret void } diff --git a/llvm/test/CodeGen/VE/Scalar/atomic_load.ll b/llvm/test/CodeGen/VE/Scalar/atomic_load.ll --- a/llvm/test/CodeGen/VE/Scalar/atomic_load.ll +++ b/llvm/test/CodeGen/VE/Scalar/atomic_load.ll @@ -64,10 +64,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i1 @_Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: and %s0, 1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 monotonic, align 1 %4 = and i8 %3, 1 @@ -78,9 +78,9 @@ ; Function Attrs: nofree norecurse nounwind define signext i8 @_Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 monotonic, align 1 ret i8 %3 @@ -89,9 +89,9 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i8 @_Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 monotonic, align 1 ret i8 %3 @@ -100,9 +100,9 @@ ; Function Attrs: nofree norecurse nounwind define signext i16 @_Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { ; CHECK-LABEL: _Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i16, i16* %2 monotonic, align 2 ret i16 %3 @@ -111,9 +111,9 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i16 @_Z23atomic_load_relaxed_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { ; CHECK-LABEL: _Z23atomic_load_relaxed_u16RNSt3__16atomicItEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i16, i16* %2 monotonic, align 2 ret i16 %3 @@ -122,9 +122,9 @@ ; Function Attrs: nofree norecurse nounwind define signext i32 @_Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { ; CHECK-LABEL: _Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i32, i32* %2 monotonic, align 4 ret i32 %3 @@ -133,9 +133,9 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i32 @_Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { ; CHECK-LABEL: _Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i32, i32* %2 monotonic, align 4 ret i32 %3 @@ -144,9 +144,9 @@ ; Function Attrs: nofree norecurse nounwind define i64 @_Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { ; CHECK-LABEL: _Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i64, i64* %2 monotonic, align 8 ret i64 %3 @@ -155,9 +155,9 @@ ; Function Attrs: nofree norecurse nounwind define i64 @_Z23atomic_load_relaxed_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { ; CHECK-LABEL: _Z23atomic_load_relaxed_u64RNSt3__16atomicImEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i64, i64* %2 monotonic, align 8 ret i64 %3 @@ -171,12 +171,12 @@ ; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s1, -8(, %s9) -; CHECK-NEXT: ld %s0, -16(, %s9) +; CHECK-NEXT: ld %s1, 248(, %s11) +; CHECK-NEXT: ld %s0, 240(, %s11) ; CHECK-NEXT: or %s11, 0, %s9 %2 = alloca i128, align 16 %3 = bitcast i128* %2 to i8* @@ -196,12 +196,12 @@ ; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s1, -8(, %s9) -; CHECK-NEXT: ld %s0, -16(, %s9) +; CHECK-NEXT: ld %s1, 248(, %s11) +; CHECK-NEXT: ld %s0, 240(, %s11) ; CHECK-NEXT: or %s11, 0, %s9 %2 = alloca i128, align 16 %3 = bitcast i128* %2 to i8* @@ -216,11 +216,11 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i1 @_Z22atomic_load_acquire_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_acquire_i1RNSt3__16atomicIbEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 acquire, align 1 %4 = and i8 %3, 1 @@ -231,10 +231,10 @@ ; Function Attrs: nofree norecurse nounwind define signext i8 @_Z22atomic_load_acquire_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_acquire_i8RNSt3__16atomicIcEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.sx %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 acquire, align 1 ret i8 %3 @@ -243,10 +243,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i8 @_Z22atomic_load_acquire_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_acquire_u8RNSt3__16atomicIhEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 acquire, align 1 ret i8 %3 @@ -255,10 +255,10 @@ ; Function Attrs: nofree norecurse nounwind define signext i16 @_Z23atomic_load_acquire_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { ; CHECK-LABEL: _Z23atomic_load_acquire_i16RNSt3__16atomicIsEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.sx %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i16, i16* %2 acquire, align 2 ret i16 %3 @@ -267,10 +267,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i16 @_Z23atomic_load_acquire_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { ; CHECK-LABEL: _Z23atomic_load_acquire_u16RNSt3__16atomicItEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i16, i16* %2 acquire, align 2 ret i16 %3 @@ -279,10 +279,10 @@ ; Function Attrs: nofree norecurse nounwind define signext i32 @_Z23atomic_load_acquire_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { ; CHECK-LABEL: _Z23atomic_load_acquire_i32RNSt3__16atomicIiEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i32, i32* %2 acquire, align 4 ret i32 %3 @@ -291,10 +291,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i32 @_Z23atomic_load_acquire_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { ; CHECK-LABEL: _Z23atomic_load_acquire_u32RNSt3__16atomicIjEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.zx %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i32, i32* %2 acquire, align 4 ret i32 %3 @@ -303,10 +303,10 @@ ; Function Attrs: nofree norecurse nounwind define i64 @_Z23atomic_load_acquire_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { ; CHECK-LABEL: _Z23atomic_load_acquire_i64RNSt3__16atomicIlEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i64, i64* %2 acquire, align 8 ret i64 %3 @@ -315,10 +315,10 @@ ; Function Attrs: nofree norecurse nounwind define i64 @_Z23atomic_load_acquire_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { ; CHECK-LABEL: _Z23atomic_load_acquire_u64RNSt3__16atomicImEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: fencem 2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i64, i64* %2 acquire, align 8 ret i64 %3 @@ -332,12 +332,12 @@ ; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 2, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s1, -8(, %s9) -; CHECK-NEXT: ld %s0, -16(, %s9) +; CHECK-NEXT: ld %s1, 248(, %s11) +; CHECK-NEXT: ld %s0, 240(, %s11) ; CHECK-NEXT: or %s11, 0, %s9 %2 = alloca i128, align 16 %3 = bitcast i128* %2 to i8* @@ -357,12 +357,12 @@ ; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 2, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s1, -8(, %s9) -; CHECK-NEXT: ld %s0, -16(, %s9) +; CHECK-NEXT: ld %s1, 248(, %s11) +; CHECK-NEXT: ld %s0, 240(, %s11) ; CHECK-NEXT: or %s11, 0, %s9 %2 = alloca i128, align 16 %3 = bitcast i128* %2 to i8* @@ -377,11 +377,11 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i1 @_Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 seq_cst, align 1 %4 = and i8 %3, 1 @@ -392,10 +392,10 @@ ; Function Attrs: nofree norecurse nounwind define signext i8 @_Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.sx %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 seq_cst, align 1 ret i8 %3 @@ -404,10 +404,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i8 @_Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { ; CHECK-LABEL: _Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i8, i8* %2 seq_cst, align 1 ret i8 %3 @@ -416,10 +416,10 @@ ; Function Attrs: nofree norecurse nounwind define signext i16 @_Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { ; CHECK-LABEL: _Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.sx %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i16, i16* %2 seq_cst, align 2 ret i16 %3 @@ -428,10 +428,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i16 @_Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { ; CHECK-LABEL: _Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i16, i16* %2 seq_cst, align 2 ret i16 %3 @@ -440,10 +440,10 @@ ; Function Attrs: nofree norecurse nounwind define signext i32 @_Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { ; CHECK-LABEL: _Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i32, i32* %2 seq_cst, align 4 ret i32 %3 @@ -452,10 +452,10 @@ ; Function Attrs: nofree norecurse nounwind define zeroext i32 @_Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { ; CHECK-LABEL: _Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.zx %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i32, i32* %2 seq_cst, align 4 ret i32 %3 @@ -464,10 +464,10 @@ ; Function Attrs: nofree norecurse nounwind define i64 @_Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { ; CHECK-LABEL: _Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i64, i64* %2 seq_cst, align 8 ret i64 %3 @@ -476,10 +476,10 @@ ; Function Attrs: nofree norecurse nounwind define i64 @_Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { ; CHECK-LABEL: _Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = load atomic i64, i64* %2 seq_cst, align 8 ret i64 %3 @@ -493,12 +493,12 @@ ; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s1, -8(, %s9) -; CHECK-NEXT: ld %s0, -16(, %s9) +; CHECK-NEXT: ld %s1, 248(, %s11) +; CHECK-NEXT: ld %s0, 240(, %s11) ; CHECK-NEXT: or %s11, 0, %s9 %2 = alloca i128, align 16 %3 = bitcast i128* %2 to i8* @@ -518,12 +518,12 @@ ; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s1, -8(, %s9) -; CHECK-NEXT: ld %s0, -16(, %s9) +; CHECK-NEXT: ld %s1, 248(, %s11) +; CHECK-NEXT: ld %s0, 240(, %s11) ; CHECK-NEXT: or %s11, 0, %s9 %2 = alloca i128, align 16 %3 = bitcast i128* %2 to i8* diff --git a/llvm/test/CodeGen/VE/Scalar/atomic_store.ll b/llvm/test/CodeGen/VE/Scalar/atomic_store.ll --- a/llvm/test/CodeGen/VE/Scalar/atomic_store.ll +++ b/llvm/test/CodeGen/VE/Scalar/atomic_store.ll @@ -64,9 +64,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { ; CHECK-LABEL: _Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i1 %1 to i8 %4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %3, i8* %4 monotonic, align 1 @@ -76,9 +76,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { ; CHECK-LABEL: _Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %1, i8* %3 monotonic, align 1 ret void @@ -87,9 +87,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { ; CHECK-LABEL: _Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %1, i8* %3 monotonic, align 1 ret void @@ -98,9 +98,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { ; CHECK-LABEL: _Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i16 %1, i16* %3 monotonic, align 2 ret void @@ -109,9 +109,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { ; CHECK-LABEL: _Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i16 %1, i16* %3 monotonic, align 2 ret void @@ -120,9 +120,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { ; CHECK-LABEL: _Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i32 %1, i32* %3 monotonic, align 4 ret void @@ -131,9 +131,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { ; CHECK-LABEL: _Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i32 %1, i32* %3 monotonic, align 4 ret void @@ -142,9 +142,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { ; CHECK-LABEL: _Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i64 %1, i64* %3 monotonic, align 8 ret void @@ -153,9 +153,9 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { ; CHECK-LABEL: _Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i64 %1, i64* %3 monotonic, align 8 ret void @@ -166,12 +166,12 @@ ; CHECK-LABEL: _Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn: ; CHECK: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s4, 0, %s0 -; CHECK-NEXT: st %s2, -8(, %s9) -; CHECK-NEXT: st %s1, -16(, %s9) +; CHECK-NEXT: st %s2, 248(, %s11) +; CHECK-NEXT: st %s1, 240(, %s11) ; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s1, 0, %s4 @@ -192,12 +192,12 @@ ; CHECK-LABEL: _Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo: ; CHECK: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s4, 0, %s0 -; CHECK-NEXT: st %s2, -8(, %s9) -; CHECK-NEXT: st %s1, -16(, %s9) +; CHECK-NEXT: st %s2, 248(, %s11) +; CHECK-NEXT: st %s1, 240(, %s11) ; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s1, 0, %s4 @@ -216,10 +216,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_release_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { ; CHECK-LABEL: _Z23atomic_store_release_i1RNSt3__16atomicIbEEb: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i1 %1 to i8 %4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %3, i8* %4 release, align 1 @@ -229,10 +229,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_release_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { ; CHECK-LABEL: _Z23atomic_store_release_i8RNSt3__16atomicIcEEc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %1, i8* %3 release, align 1 ret void @@ -241,10 +241,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_release_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { ; CHECK-LABEL: _Z23atomic_store_release_u8RNSt3__16atomicIhEEh: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %1, i8* %3 release, align 1 ret void @@ -253,10 +253,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_release_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { ; CHECK-LABEL: _Z24atomic_store_release_i16RNSt3__16atomicIsEEs: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i16 %1, i16* %3 release, align 2 ret void @@ -265,10 +265,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_release_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { ; CHECK-LABEL: _Z24atomic_store_release_u16RNSt3__16atomicItEEt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i16 %1, i16* %3 release, align 2 ret void @@ -277,10 +277,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_release_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { ; CHECK-LABEL: _Z24atomic_store_release_i32RNSt3__16atomicIiEEi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i32 %1, i32* %3 release, align 4 ret void @@ -289,10 +289,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_release_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { ; CHECK-LABEL: _Z24atomic_store_release_u32RNSt3__16atomicIjEEj: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i32 %1, i32* %3 release, align 4 ret void @@ -301,10 +301,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_release_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { ; CHECK-LABEL: _Z24atomic_store_release_i64RNSt3__16atomicIlEEl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i64 %1, i64* %3 release, align 8 ret void @@ -313,10 +313,10 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_release_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { ; CHECK-LABEL: _Z24atomic_store_release_u64RNSt3__16atomicImEEm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 1 ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i64 %1, i64* %3 release, align 8 ret void @@ -327,12 +327,12 @@ ; CHECK-LABEL: _Z25atomic_store_release_i128RNSt3__16atomicInEEn: ; CHECK: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s4, 0, %s0 -; CHECK-NEXT: st %s2, -8(, %s9) -; CHECK-NEXT: st %s1, -16(, %s9) +; CHECK-NEXT: st %s2, 248(, %s11) +; CHECK-NEXT: st %s1, 240(, %s11) ; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 3, (0)1 ; CHECK-NEXT: or %s1, 0, %s4 @@ -353,12 +353,12 @@ ; CHECK-LABEL: _Z25atomic_store_release_u128RNSt3__16atomicIoEEo: ; CHECK: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s4, 0, %s0 -; CHECK-NEXT: st %s2, -8(, %s9) -; CHECK-NEXT: st %s1, -16(, %s9) +; CHECK-NEXT: st %s2, 248(, %s11) +; CHECK-NEXT: st %s1, 240(, %s11) ; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 3, (0)1 ; CHECK-NEXT: or %s1, 0, %s4 @@ -377,11 +377,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { ; CHECK-LABEL: _Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i1 %1 to i8 %4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %3, i8* %4 seq_cst, align 1 @@ -391,11 +391,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { ; CHECK-LABEL: _Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %1, i8* %3 seq_cst, align 1 ret void @@ -404,11 +404,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { ; CHECK-LABEL: _Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i8 %1, i8* %3 seq_cst, align 1 ret void @@ -417,11 +417,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { ; CHECK-LABEL: _Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i16 %1, i16* %3 seq_cst, align 2 ret void @@ -430,11 +430,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { ; CHECK-LABEL: _Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i16 %1, i16* %3 seq_cst, align 2 ret void @@ -443,11 +443,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { ; CHECK-LABEL: _Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i32 %1, i32* %3 seq_cst, align 4 ret void @@ -456,11 +456,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { ; CHECK-LABEL: _Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i32 %1, i32* %3 seq_cst, align 4 ret void @@ -469,11 +469,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { ; CHECK-LABEL: _Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i64 %1, i64* %3 seq_cst, align 8 ret void @@ -482,11 +482,11 @@ ; Function Attrs: nofree norecurse nounwind define void @_Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { ; CHECK-LABEL: _Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fencem 3 ; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: fencem 3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 store atomic i64 %1, i64* %3 seq_cst, align 8 ret void @@ -497,12 +497,12 @@ ; CHECK-LABEL: _Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn: ; CHECK: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s4, 0, %s0 -; CHECK-NEXT: st %s2, -8(, %s9) -; CHECK-NEXT: st %s1, -16(, %s9) +; CHECK-NEXT: st %s2, 248(, %s11) +; CHECK-NEXT: st %s1, 240(, %s11) ; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: or %s1, 0, %s4 @@ -523,12 +523,12 @@ ; CHECK-LABEL: _Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo: ; CHECK: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s4, 0, %s0 -; CHECK-NEXT: st %s2, -8(, %s9) -; CHECK-NEXT: st %s1, -16(, %s9) +; CHECK-NEXT: st %s2, 248(, %s11) +; CHECK-NEXT: st %s1, 240(, %s11) ; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) -; CHECK-NEXT: lea %s2, -16(, %s9) +; CHECK-NEXT: lea %s2, 240(, %s11) ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: or %s1, 0, %s4 diff --git a/llvm/test/CodeGen/VE/Scalar/bitcast.ll b/llvm/test/CodeGen/VE/Scalar/bitcast.ll --- a/llvm/test/CodeGen/VE/Scalar/bitcast.ll +++ b/llvm/test/CodeGen/VE/Scalar/bitcast.ll @@ -3,8 +3,8 @@ ; Function Attrs: noinline nounwind optnone define dso_local i64 @bitcastd2l(double %x) { ; CHECK-LABEL: bitcastd2l: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %r = bitcast double %x to i64 ret i64 %r } @@ -12,8 +12,8 @@ ; Function Attrs: noinline nounwind optnone define dso_local double @bitcastl2d(i64 %x) { ; CHECK-LABEL: bitcastl2d: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %r = bitcast i64 %x to double ret double %r } @@ -21,9 +21,9 @@ ; Function Attrs: noinline nounwind optnone define dso_local float @bitcastw2f(i32 %x) { ; CHECK-LABEL: bitcastw2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = bitcast i32 %x to float ret float %r } @@ -31,9 +31,9 @@ ; Function Attrs: noinline nounwind optnone define dso_local i32 @bitcastf2w(float %x) { ; CHECK-LABEL: bitcastf2w: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = bitcast float %x to i32 ret i32 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/bitreverse.ll b/llvm/test/CodeGen/VE/Scalar/bitreverse.ll --- a/llvm/test/CodeGen/VE/Scalar/bitreverse.ll +++ b/llvm/test/CodeGen/VE/Scalar/bitreverse.ll @@ -8,154 +8,154 @@ define i128 @func128(i128 %p) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s2, %s1 ; CHECK-NEXT: brv %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.bitreverse.i128(i128 %p) ret i128 %r } define i64 @func64(i64 %p) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.bitreverse.i64(i64 %p) ret i64 %r } define signext i32 @func32s(i32 signext %p) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: sra.l %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bitreverse.i32(i32 %p) ret i32 %r } define zeroext i32 @func32z(i32 zeroext %p) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: srl %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bitreverse.i32(i32 %p) ret i32 %r } define signext i16 @func16s(i16 signext %p) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bitreverse.i16(i16 %p) ret i16 %r } define zeroext i16 @func16z(i16 zeroext %p) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: srl %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bitreverse.i16(i16 %p) ret i16 %r } define signext i8 @func8s(i8 signext %p) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.bitreverse.i8(i8 %p) ret i8 %r } define zeroext i8 @func8z(i8 zeroext %p) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: srl %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.bitreverse.i8(i8 %p) ret i8 %r } define i128 @func128i() { ; CHECK-LABEL: func128i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea.sl %s1, -65536 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.bitreverse.i128(i128 65535) ret i128 %r } define i64 @func64i() { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -65536 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.bitreverse.i64(i64 65535) ret i64 %r } define signext i32 @func32is() { ; CHECK-LABEL: func32is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -65536 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bitreverse.i32(i32 65535) ret i32 %r } define zeroext i32 @func32iz() { ; CHECK-LABEL: func32iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -65536 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bitreverse.i32(i32 65535) ret i32 %r } define signext i16 @func16is() { ; CHECK-LABEL: func16is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -256 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bitreverse.i16(i16 255) ret i16 %r } define zeroext i16 @func16iz() { ; CHECK-LABEL: func16iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 65280 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bitreverse.i16(i16 255) ret i16 %r } define signext i8 @func8is() { ; CHECK-LABEL: func8is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 15, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.bitreverse.i8(i8 240) ret i8 %r } define zeroext i8 @func8iz() { ; CHECK-LABEL: func8iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 15, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.bitreverse.i8(i8 240) ret i8 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/blockaddress.ll b/llvm/test/CodeGen/VE/Scalar/blockaddress.ll --- a/llvm/test/CodeGen/VE/Scalar/blockaddress.ll +++ b/llvm/test/CodeGen/VE/Scalar/blockaddress.ll @@ -5,7 +5,7 @@ ; Function Attrs: nofree norecurse nounwind writeonly define void @test() { ; CHECK-LABEL: test: -; CHECK: .LBB0_3: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: .Ltmp0: # Block address taken ; CHECK-NEXT: # %bb.1: # %test1 ; CHECK-NEXT: lea %s0, addr@lo @@ -15,7 +15,7 @@ ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, .Ltmp0@hi(, %s1) ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: br label %test1 diff --git a/llvm/test/CodeGen/VE/Scalar/br_cc.ll b/llvm/test/CodeGen/VE/Scalar/br_cc.ll --- a/llvm/test/CodeGen/VE/Scalar/br_cc.ll +++ b/llvm/test/CodeGen/VE/Scalar/br_cc.ll @@ -3,7 +3,7 @@ ; Function Attrs: nounwind define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) { ; CHECK-LABEL: br_cc_i1_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -11,7 +11,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = xor i1 %0, %1 br i1 %3, label %5, label %4 @@ -26,14 +26,14 @@ ; Function Attrs: nounwind define void @br_cc_i8_var(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: br_cc_i8_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i8 %0, %1 br i1 %3, label %4, label %5 @@ -48,14 +48,14 @@ ; Function Attrs: nounwind define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: br_cc_u8_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i8 %0, %1 br i1 %3, label %4, label %5 @@ -70,14 +70,14 @@ ; Function Attrs: nounwind define void @br_cc_i16_var(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: br_cc_i16_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i16 %0, %1 br i1 %3, label %4, label %5 @@ -92,14 +92,14 @@ ; Function Attrs: nounwind define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: br_cc_u16_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i16 %0, %1 br i1 %3, label %4, label %5 @@ -114,14 +114,14 @@ ; Function Attrs: nounwind define void @br_cc_i32_var(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: br_cc_i32_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i32 %0, %1 br i1 %3, label %4, label %5 @@ -136,14 +136,14 @@ ; Function Attrs: nounwind define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: br_cc_u32_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i32 %0, %1 br i1 %3, label %4, label %5 @@ -158,14 +158,14 @@ ; Function Attrs: nounwind define void @br_cc_i64_var(i64 %0, i64 %1) { ; CHECK-LABEL: br_cc_i64_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i64 %0, %1 br i1 %3, label %4, label %5 @@ -180,14 +180,14 @@ ; Function Attrs: nounwind define void @br_cc_u64_var(i64 %0, i64 %1) { ; CHECK-LABEL: br_cc_u64_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i64 %0, %1 br i1 %3, label %4, label %5 @@ -202,7 +202,7 @@ ; Function Attrs: nounwind define void @br_cc_i128_var(i128 %0, i128 %1) { ; CHECK-LABEL: br_cc_i128_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -212,7 +212,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i128 %0, %1 br i1 %3, label %4, label %5 @@ -227,7 +227,7 @@ ; Function Attrs: nounwind define void @br_cc_u128_var(i128 %0, i128 %1) { ; CHECK-LABEL: br_cc_u128_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -237,7 +237,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i128 %0, %1 br i1 %3, label %4, label %5 @@ -252,14 +252,14 @@ ; Function Attrs: nounwind define void @br_cc_float_var(float %0, float %1) { ; CHECK-LABEL: br_cc_float_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.s %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp fast oeq float %0, %1 br i1 %3, label %4, label %5 @@ -274,14 +274,14 @@ ; Function Attrs: nounwind define void @br_cc_double_var(double %0, double %1) { ; CHECK-LABEL: br_cc_double_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.d %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp fast oeq double %0, %1 br i1 %3, label %4, label %5 @@ -296,7 +296,7 @@ ; Function Attrs: nounwind define void @br_cc_quad_var(fp128 %0, fp128 %1) { ; CHECK-LABEL: br_cc_quad_var: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s2, %s0 ; CHECK-NEXT: brne.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -304,7 +304,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp fast oeq fp128 %0, %1 br i1 %3, label %4, label %5 @@ -319,14 +319,14 @@ ; Function Attrs: nounwind define void @br_cc_i1_imm(i1 zeroext %0) { ; CHECK-LABEL: br_cc_i1_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) br i1 %0, label %3, label %2 2: ; preds = %1 @@ -340,14 +340,14 @@ ; Function Attrs: nounwind define void @br_cc_i8_imm(i8 signext %0) { ; CHECK-LABEL: br_cc_i8_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brlt.w -10, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp slt i8 %0, -9 br i1 %2, label %3, label %4 @@ -362,7 +362,7 @@ ; Function Attrs: nounwind define void @br_cc_u8_imm(i8 zeroext %0) { ; CHECK-LABEL: br_cc_u8_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, 8, %s0 ; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -370,7 +370,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ult i8 %0, 9 br i1 %2, label %3, label %4 @@ -385,14 +385,14 @@ ; Function Attrs: nounwind define void @br_cc_i16_imm(i16 signext %0) { ; CHECK-LABEL: br_cc_i16_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brlt.w 62, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp slt i16 %0, 63 br i1 %2, label %3, label %4 @@ -407,7 +407,7 @@ ; Function Attrs: nounwind define void @br_cc_u16_imm(i16 zeroext %0) { ; CHECK-LABEL: br_cc_u16_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, 63, %s0 ; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -415,7 +415,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ult i16 %0, 64 br i1 %2, label %3, label %4 @@ -430,14 +430,14 @@ ; Function Attrs: nounwind define void @br_cc_i32_imm(i32 signext %0) { ; CHECK-LABEL: br_cc_i32_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brlt.w 63, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp slt i32 %0, 64 br i1 %2, label %3, label %4 @@ -452,7 +452,7 @@ ; Function Attrs: nounwind define void @br_cc_u32_imm(i32 zeroext %0) { ; CHECK-LABEL: br_cc_u32_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, 63, %s0 ; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -460,7 +460,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ult i32 %0, 64 br i1 %2, label %3, label %4 @@ -475,14 +475,14 @@ ; Function Attrs: nounwind define void @br_cc_i64_imm(i64 %0) { ; CHECK-LABEL: br_cc_i64_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brlt.l 63, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp slt i64 %0, 64 br i1 %2, label %3, label %4 @@ -497,7 +497,7 @@ ; Function Attrs: nounwind define void @br_cc_u64_imm(i64 %0) { ; CHECK-LABEL: br_cc_u64_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, 63, %s0 ; CHECK-NEXT: brgt.l 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -505,7 +505,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ult i64 %0, 64 br i1 %2, label %3, label %4 @@ -520,7 +520,7 @@ ; Function Attrs: nounwind define void @br_cc_i128_imm(i128 %0) { ; CHECK-LABEL: br_cc_i128_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmps.l %s1, %s1, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -534,7 +534,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp slt i128 %0, 64 br i1 %2, label %3, label %4 @@ -549,7 +549,7 @@ ; Function Attrs: nounwind define void @br_cc_u128_imm(i128 %0) { ; CHECK-LABEL: br_cc_u128_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmps.l %s1, %s1, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -563,7 +563,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ult i128 %0, 64 br i1 %2, label %3, label %4 @@ -578,14 +578,14 @@ ; Function Attrs: nounwind define void @br_cc_float_imm(float %0) { ; CHECK-LABEL: br_cc_float_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brle.s 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fcmp fast olt float %0, 0.000000e+00 br i1 %2, label %3, label %4 @@ -600,14 +600,14 @@ ; Function Attrs: nounwind define void @br_cc_double_imm(double %0) { ; CHECK-LABEL: br_cc_double_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brle.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fcmp fast olt double %0, 0.000000e+00 br i1 %2, label %3, label %4 @@ -622,7 +622,7 @@ ; Function Attrs: nounwind define void @br_cc_quad_imm(fp128 %0) { ; CHECK-LABEL: br_cc_quad_imm: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) @@ -635,7 +635,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000 br i1 %2, label %3, label %4 @@ -650,14 +650,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_i1(i1 zeroext %0) { ; CHECK-LABEL: br_cc_imm_i1: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) br i1 %0, label %2, label %3 2: ; preds = %1 @@ -671,14 +671,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_i8(i8 signext %0) { ; CHECK-LABEL: br_cc_imm_i8: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brgt.w -9, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp sgt i8 %0, -10 br i1 %2, label %3, label %4 @@ -693,7 +693,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_u8(i8 zeroext %0) { ; CHECK-LABEL: br_cc_imm_u8: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, 9, %s0 ; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -701,7 +701,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ugt i8 %0, 8 br i1 %2, label %3, label %4 @@ -716,14 +716,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_i16(i16 signext %0) { ; CHECK-LABEL: br_cc_imm_i16: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brgt.w 63, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp sgt i16 %0, 62 br i1 %2, label %3, label %4 @@ -738,7 +738,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_u16(i16 zeroext %0) { ; CHECK-LABEL: br_cc_imm_u16: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 64 ; CHECK-NEXT: cmpu.w %s0, %s1, %s0 ; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2 @@ -747,7 +747,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ugt i16 %0, 63 br i1 %2, label %3, label %4 @@ -762,14 +762,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_i32(i32 signext %0) { ; CHECK-LABEL: br_cc_imm_i32: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brgt.w -64, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp sgt i32 %0, -65 br i1 %2, label %3, label %4 @@ -784,7 +784,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_u32(i32 zeroext %0) { ; CHECK-LABEL: br_cc_imm_u32: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, -64, %s0 ; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -792,7 +792,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ugt i32 %0, -65 br i1 %2, label %3, label %4 @@ -807,14 +807,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_i64(i64 %0) { ; CHECK-LABEL: br_cc_imm_i64: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brgt.l -64, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp sgt i64 %0, -65 br i1 %2, label %3, label %4 @@ -829,7 +829,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_u64(i64 %0) { ; CHECK-LABEL: br_cc_imm_u64: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, -64, %s0 ; CHECK-NEXT: brlt.l 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: @@ -837,7 +837,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ugt i64 %0, -65 br i1 %2, label %3, label %4 @@ -852,7 +852,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_i128(i128 %0) { ; CHECK-LABEL: br_cc_imm_i128: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s1, %s1, (0)0 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -866,7 +866,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp sgt i128 %0, -65 br i1 %2, label %3, label %4 @@ -881,7 +881,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_u128(i128 %0) { ; CHECK-LABEL: br_cc_imm_u128: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s1, %s1, (0)0 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -895,7 +895,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp ugt i128 %0, -65 br i1 %2, label %3, label %4 @@ -910,14 +910,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_float(float %0) { ; CHECK-LABEL: br_cc_imm_float: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brgt.s 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fcmp fast ult float %0, 0.000000e+00 br i1 %2, label %4, label %3 @@ -932,14 +932,14 @@ ; Function Attrs: nounwind define void @br_cc_imm_double(double %0) { ; CHECK-LABEL: br_cc_imm_double: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brgt.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fcmp fast ult double %0, 0.000000e+00 br i1 %2, label %4, label %3 @@ -954,7 +954,7 @@ ; Function Attrs: nounwind define void @br_cc_imm_quad(fp128 %0) { ; CHECK-LABEL: br_cc_imm_quad: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) @@ -967,7 +967,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000 br i1 %2, label %4, label %3 diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll b/llvm/test/CodeGen/VE/Scalar/br_jt.ll --- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll +++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll @@ -3,31 +3,34 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @br_jt(i32 signext %0) { ; CHECK-LABEL: br_jt: -; CHECK: .LBB{{[0-9]+}}_11: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_3 +; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_4 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_2 -; CHECK-NEXT: # %bb.8: -; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_9 -; CHECK-NEXT: # %bb.6: +; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_8 +; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_7 +; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9 -; CHECK-NEXT: .LBB{{[0-9]+}}_3: -; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_7 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_9 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) +; CHECK-NEXT: .LBB{{[0-9]+}}_4: +; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_9 ; CHECK-NEXT: # %bb.5: +; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_7 +; CHECK-NEXT: # %bb.6: ; CHECK-NEXT: or %s0, 7, (0)1 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9 -; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 3, (0)1 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9 ; CHECK-NEXT: .LBB{{[0-9]+}}_7: -; CHECK-NEXT: or %s0, 4, (0)1 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) +; CHECK-NEXT: .LBB{{[0-9]+}}_8: +; CHECK-NEXT: or %s0, 3, (0)1 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: .LBB{{[0-9]+}}_9: +; CHECK-NEXT: or %s0, 4, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) switch i32 %0, label %5 [ i32 1, label %6 i32 2, label %2 diff --git a/llvm/test/CodeGen/VE/Scalar/brcond.ll b/llvm/test/CodeGen/VE/Scalar/brcond.ll --- a/llvm/test/CodeGen/VE/Scalar/brcond.ll +++ b/llvm/test/CodeGen/VE/Scalar/brcond.ll @@ -3,14 +3,14 @@ ; Function Attrs: nounwind define void @brcond_then(i1 zeroext %0) { ; CHECK-LABEL: brcond_then: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) br i1 %0, label %2, label %3 2: ; preds = %1 @@ -24,14 +24,14 @@ ; Function Attrs: nounwind define void @brcond_else(i1 zeroext %0) { ; CHECK-LABEL: brcond_else: -; CHECK: .LBB{{[0-9]+}}_4: +; CHECK: # %bb.0: ; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) br i1 %0, label %3, label %2 2: ; preds = %1 diff --git a/llvm/test/CodeGen/VE/Scalar/brind.ll b/llvm/test/CodeGen/VE/Scalar/brind.ll --- a/llvm/test/CodeGen/VE/Scalar/brind.ll +++ b/llvm/test/CodeGen/VE/Scalar/brind.ll @@ -3,7 +3,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @brind(i32 signext %0) { ; CHECK-LABEL: brind: -; CHECK: .LBB{{[0-9]+}}_6: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 1, (0)1 ; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 ; CHECK-NEXT: lea %s2, .Ltmp0@lo @@ -23,17 +23,18 @@ ; CHECK-NEXT: .Ltmp0: # Block address taken ; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: or %s0, -1, (0)1 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_4 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: .Ltmp2: # Block address taken ; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_4 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: .Ltmp1: # Block address taken ; CHECK-NEXT: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: .LBB{{[0-9]+}}_4: # %.split ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = icmp eq i32 %0, 1 %3 = select i1 %2, i8* blockaddress(@brind, %6), i8* blockaddress(@brind, %8) %4 = icmp eq i32 %0, 0 diff --git a/llvm/test/CodeGen/VE/Scalar/bswap.ll b/llvm/test/CodeGen/VE/Scalar/bswap.ll --- a/llvm/test/CodeGen/VE/Scalar/bswap.ll +++ b/llvm/test/CodeGen/VE/Scalar/bswap.ll @@ -7,121 +7,121 @@ define i128 @func128(i128 %p) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: bswp %s2, %s1, 0 ; CHECK-NEXT: bswp %s1, %s0, 0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.bswap.i128(i128 %p) ret i128 %r } define i64 @func64(i64 %p) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: bswp %s0, %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.bswap.i64(i64 %p) ret i64 %r } define signext i32 @func32s(i32 signext %p) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bswap.i32(i32 %p) ret i32 %r } define zeroext i32 @func32z(i32 zeroext %p) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bswap.i32(i32 %p) ret i32 %r } define signext i16 @func16s(i16 signext %p) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 16 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bswap.i16(i16 %p) ret i16 %r } define zeroext i16 @func16z(i16 zeroext %p) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 16 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bswap.i16(i16 %p) ret i16 %r } define i128 @func128i() { ; CHECK-LABEL: func128i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea.sl %s1, -16777216 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.bswap.i128(i128 255) ret i128 %r } define i64 @func64i() { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -16777216 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.bswap.i64(i64 255) ret i64 %r } define signext i32 @func32si() { ; CHECK-LABEL: func32si: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -16777216 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bswap.i32(i32 255) ret i32 %r } define zeroext i32 @func32zi() { ; CHECK-LABEL: func32zi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -16777216 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.bswap.i32(i32 255) ret i32 %r } define signext i16 @func16si() { ; CHECK-LABEL: func16si: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -256 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bswap.i16(i16 255) ret i16 %r } define zeroext i16 @func16zi() { ; CHECK-LABEL: func16zi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 65280 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.bswap.i16(i16 255) ret i16 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/callstruct.ll b/llvm/test/CodeGen/VE/Scalar/callstruct.ll --- a/llvm/test/CodeGen/VE/Scalar/callstruct.ll +++ b/llvm/test/CodeGen/VE/Scalar/callstruct.ll @@ -7,10 +7,10 @@ ; Function Attrs: norecurse nounwind define void @fun(%struct.a* noalias nocapture sret %a, i32 %p1, i32 %p2) { ; CHECK-LABEL: fun: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s2, 4(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a.zero = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 0 store i32 %p1, i32* %a.zero, align 4 %a.one = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 1 @@ -25,11 +25,11 @@ ; CHECK-NEXT: lea %s0, callee@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, callee@hi(, %s0) -; CHECK-NEXT: lea %s0, -8(, %s9) +; CHECK-NEXT: lea %s0, 248(, %s11) ; CHECK-NEXT: or %s1, 3, (0)1 ; CHECK-NEXT: or %s2, 4, (0)1 ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: ld %s0, -8(, %s9) +; CHECK-NEXT: ld %s0, 248(, %s11) ; CHECK-NEXT: lea %s1, A@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, A@hi(, %s1) diff --git a/llvm/test/CodeGen/VE/Scalar/cast.ll b/llvm/test/CodeGen/VE/Scalar/cast.ll --- a/llvm/test/CodeGen/VE/Scalar/cast.ll +++ b/llvm/test/CodeGen/VE/Scalar/cast.ll @@ -2,110 +2,110 @@ define signext i32 @i() { ; CHECK-LABEL: i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 -2147483648 } define zeroext i32 @ui() { ; CHECK-LABEL: ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 -2147483648 } define i64 @ll() { ; CHECK-LABEL: ll: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 -2147483648 } define i64 @ull() { ; CHECK-LABEL: ull: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2147483648 } define signext i8 @d2c(double %x) { ; CHECK-LABEL: d2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi double %x to i8 ret i8 %r } define zeroext i8 @d2uc(double %x) { ; CHECK-LABEL: d2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui double %x to i8 ret i8 %r } define signext i16 @d2s(double %x) { ; CHECK-LABEL: d2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi double %x to i16 ret i16 %r } define zeroext i16 @d2us(double %x) { ; CHECK-LABEL: d2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui double %x to i16 ret i16 %r } define signext i32 @d2i(double %x) { ; CHECK-LABEL: d2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi double %x to i32 ret i32 %r } define zeroext i32 @d2ui(double %x) { ; CHECK-LABEL: d2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui double %x to i32 ret i32 %r } define i64 @d2ll(double %x) { ; CHECK-LABEL: d2ll: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi double %x to i64 ret i64 %r } define i64 @d2ull(double %x) { ; CHECK-LABEL: d2ull: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1138753536 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fsub.d %s1, %s0, %s1 @@ -114,115 +114,115 @@ ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui double %x to i64 ret i64 %r } define float @d2f(double %x) { ; CHECK-LABEL: d2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptrunc double %x to float ret float %r } define double @d2d(double returned %0) { ; CHECK-LABEL: d2d: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret double %0 } define fp128 @d2q(double) { ; CHECK-LABEL: d2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fpext double %0 to fp128 ret fp128 %2 } define signext i8 @q2c(fp128) { ; CHECK-LABEL: q2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptosi fp128 %0 to i8 ret i8 %2 } define zeroext i8 @q2uc(fp128) { ; CHECK-LABEL: q2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptoui fp128 %0 to i8 ret i8 %2 } define signext i16 @q2s(fp128) { ; CHECK-LABEL: q2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptosi fp128 %0 to i16 ret i16 %2 } define zeroext i16 @q2us(fp128) { ; CHECK-LABEL: q2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptoui fp128 %0 to i16 ret i16 %2 } define signext i32 @q2i(fp128) { ; CHECK-LABEL: q2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptosi fp128 %0 to i32 ret i32 %2 } define zeroext i32 @q2ui(fp128) { ; CHECK-LABEL: q2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptoui fp128 %0 to i32 ret i32 %2 } define i64 @q2ll(fp128) { ; CHECK-LABEL: q2ll: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptosi fp128 %0 to i64 ret i64 %2 } define i64 @q2ull(fp128) { ; CHECK-LABEL: q2ull: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) @@ -237,110 +237,110 @@ ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cmov.d.lt %s2, %s0, %s3 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptoui fp128 %0 to i64 ret i64 %2 } define float @q2f(fp128) { ; CHECK-LABEL: q2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.q %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptrunc fp128 %0 to float ret float %2 } define double @q2d(fp128) { ; CHECK-LABEL: q2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.q %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fptrunc fp128 %0 to double ret double %2 } define fp128 @q2q(fp128 returned) { ; CHECK-LABEL: q2q: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret fp128 %0 } define signext i8 @f2c(float %x) { ; CHECK-LABEL: f2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi float %x to i8 ret i8 %r } define zeroext i8 @f2uc(float %x) { ; CHECK-LABEL: f2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui float %x to i8 ret i8 %r } define signext i16 @f2s(float %x) { ; CHECK-LABEL: f2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi float %x to i16 ret i16 %r } define zeroext i16 @f2us(float %x) { ; CHECK-LABEL: f2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui float %x to i16 ret i16 %r } define signext i32 @f2i(float %x) { ; CHECK-LABEL: f2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi float %x to i32 ret i32 %r } define zeroext i32 @f2ui(float %x) { ; CHECK-LABEL: f2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui float %x to i32 ret i32 %r } define i64 @f2ll(float %x) { ; CHECK-LABEL: f2ll: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptosi float %x to i64 ret i64 %r } define i64 @f2ull(float %x) { ; CHECK-LABEL: f2ull: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1593835520 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fsub.s %s1, %s0, %s1 @@ -351,208 +351,208 @@ ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fptoui float %x to i64 ret i64 %r } define float @f2f(float returned %0) { ; CHECK-LABEL: f2f: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret float %0 } define double @f2d(float %x) { ; CHECK-LABEL: f2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.s %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fpext float %x to double ret double %r } define fp128 @f2q(float) { ; CHECK-LABEL: f2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.q.s %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fpext float %0 to fp128 ret fp128 %2 } define signext i8 @ll2c(i64 %0) { ; CHECK-LABEL: ll2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i8 ret i8 %2 } define zeroext i8 @ll2uc(i64 %0) { ; CHECK-LABEL: ll2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i8 ret i8 %2 } define signext i16 @ll2s(i64 %0) { ; CHECK-LABEL: ll2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i16 ret i16 %2 } define zeroext i16 @ll2us(i64 %0) { ; CHECK-LABEL: ll2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i16 ret i16 %2 } define signext i32 @ll2i(i64 %0) { ; CHECK-LABEL: ll2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i32 ret i32 %2 } define zeroext i32 @ll2ui(i64 %0) { ; CHECK-LABEL: ll2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i32 ret i32 %2 } define i64 @ll2ll(i64 returned %0) { ; CHECK-LABEL: ll2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i64 %0 } define i64 @ll2ull(i64 returned %0) { ; CHECK-LABEL: ll2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i64 %0 } define float @ll2f(i64 %x) { ; CHECK-LABEL: ll2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i64 %x to float ret float %r } define double @ll2d(i64 %x) { ; CHECK-LABEL: ll2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.l %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i64 %x to double ret double %r } define fp128 @ll2q(i64) { ; CHECK-LABEL: ll2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sitofp i64 %0 to fp128 ret fp128 %2 } define signext i8 @ull2c(i64 %0) { ; CHECK-LABEL: ull2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i8 ret i8 %2 } define zeroext i8 @ull2uc(i64 %0) { ; CHECK-LABEL: ull2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i8 ret i8 %2 } define signext i16 @ull2s(i64 %0) { ; CHECK-LABEL: ull2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i16 ret i16 %2 } define zeroext i16 @ull2us(i64 %0) { ; CHECK-LABEL: ull2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i16 ret i16 %2 } define signext i32 @ull2i(i64 %0) { ; CHECK-LABEL: ull2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i32 ret i32 %2 } define zeroext i32 @ull2ui(i64 %0) { ; CHECK-LABEL: ull2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i64 %0 to i32 ret i32 %2 } define i64 @ull2ll(i64 returned %0) { ; CHECK-LABEL: ull2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i64 %0 } define i64 @ull2ull(i64 returned %0) { ; CHECK-LABEL: ull2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i64 %0 } define float @ull2f(i64 %x) { ; CHECK-LABEL: ull2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cvt.d.l %s1, %s0 ; CHECK-NEXT: cvt.s.d %s1, %s1 @@ -564,14 +564,14 @@ ; CHECK-NEXT: fadd.s %s0, %s0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i64 %x to float ret float %r } define double @ull2d(i64 %x) { ; CHECK-LABEL: ull2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s1, %s0, 32 ; CHECK-NEXT: lea.sl %s2, 1160773632 ; CHECK-NEXT: or %s1, %s1, %s2 @@ -582,14 +582,14 @@ ; CHECK-NEXT: lea.sl %s2, 1127219200 ; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i64 %x to double ret double %r } define fp128 @ull2q(i64) { ; CHECK-LABEL: ull2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s1, %s0, 61 ; CHECK-NEXT: and %s1, 4, %s1 ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo @@ -600,577 +600,577 @@ ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: fadd.q %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = uitofp i64 %0 to fp128 ret fp128 %2 } define signext i8 @i2c(i32 signext %0) { ; CHECK-LABEL: i2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i8 ret i8 %2 } define zeroext i8 @i2uc(i32 signext %0) { ; CHECK-LABEL: i2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i8 ret i8 %2 } define signext i16 @i2s(i32 signext %0) { ; CHECK-LABEL: i2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i16 ret i16 %2 } define zeroext i16 @i2us(i32 signext %0) { ; CHECK-LABEL: i2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i16 ret i16 %2 } define signext i32 @i2i(i32 signext returned %0) { ; CHECK-LABEL: i2i: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i32 %0 } define zeroext i32 @i2ui(i32 signext returned %0) { ; CHECK-LABEL: i2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 %0 } define i64 @i2ll(i32 signext %0) { ; CHECK-LABEL: i2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i32 %0 to i64 ret i64 %2 } define i64 @i2ull(i32 signext %0) { ; CHECK-LABEL: i2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i32 %0 to i64 ret i64 %2 } define float @i2f(i32 signext %x) { ; CHECK-LABEL: i2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i32 %x to float ret float %r } define double @i2d(i32 signext %x) { ; CHECK-LABEL: i2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i32 %x to double ret double %r } define fp128 @i2q(i32 signext %x) { ; CHECK-LABEL: i2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i32 %x to fp128 ret fp128 %r } define signext i8 @ui2c(i32 zeroext %0) { ; CHECK-LABEL: ui2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i8 ret i8 %2 } define zeroext i8 @ui2uc(i32 zeroext %0) { ; CHECK-LABEL: ui2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i8 ret i8 %2 } define signext i16 @ui2s(i32 zeroext %0) { ; CHECK-LABEL: ui2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i16 ret i16 %2 } define zeroext i16 @ui2us(i32 zeroext %0) { ; CHECK-LABEL: ui2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i32 %0 to i16 ret i16 %2 } define signext i32 @ui2i(i32 zeroext returned %0) { ; CHECK-LABEL: ui2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 %0 } define zeroext i32 @ui2ui(i32 zeroext returned %0) { ; CHECK-LABEL: ui2ui: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i32 %0 } define i64 @ui2ll(i32 zeroext %0) { ; CHECK-LABEL: ui2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i32 %0 to i64 ret i64 %2 } define i64 @ui2ull(i32 zeroext %0) { ; CHECK-LABEL: ui2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i32 %0 to i64 ret i64 %2 } define float @ui2f(i32 zeroext %x) { ; CHECK-LABEL: ui2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i32 %x to float ret float %r } define double @ui2d(i32 zeroext %x) { ; CHECK-LABEL: ui2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.l %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i32 %x to double ret double %r } define fp128 @ui2q(i32 zeroext %0) { ; CHECK-LABEL: ui2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = uitofp i32 %0 to fp128 ret fp128 %2 } define signext i8 @s2c(i16 signext %0) { ; CHECK-LABEL: s2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i16 %0 to i8 ret i8 %2 } define zeroext i8 @s2uc(i16 signext %0) { ; CHECK-LABEL: s2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i16 %0 to i8 ret i8 %2 } define signext i16 @s2s(i16 returned signext %0) { ; CHECK-LABEL: s2s: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i16 %0 } define zeroext i16 @s2us(i16 returned signext %0) { ; CHECK-LABEL: s2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i16 %0 } define signext i32 @s2i(i16 signext %0) { ; CHECK-LABEL: s2i: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i16 %0 to i32 ret i32 %2 } define zeroext i32 @s2ui(i16 signext %0) { ; CHECK-LABEL: s2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i16 %0 to i32 ret i32 %2 } define i64 @s2ll(i16 signext %0) { ; CHECK-LABEL: s2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i16 %0 to i64 ret i64 %2 } define i64 @s2ull(i16 signext %0) { ; CHECK-LABEL: s2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i16 %0 to i64 ret i64 %2 } define float @s2f(i16 signext %x) { ; CHECK-LABEL: s2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i16 %x to float ret float %r } define double @s2d(i16 signext %x) { ; CHECK-LABEL: s2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i16 %x to double ret double %r } define fp128 @s2q(i16 signext) { ; CHECK-LABEL: s2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sitofp i16 %0 to fp128 ret fp128 %2 } define signext i8 @us2c(i16 zeroext %0) { ; CHECK-LABEL: us2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i16 %0 to i8 ret i8 %2 } define zeroext i8 @us2uc(i16 zeroext %0) { ; CHECK-LABEL: us2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i16 %0 to i8 ret i8 %2 } define signext i16 @us2s(i16 returned zeroext %0) { ; CHECK-LABEL: us2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i16 %0 } define zeroext i16 @us2us(i16 returned zeroext %0) { ; CHECK-LABEL: us2us: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i16 %0 } define signext i32 @us2i(i16 zeroext %0) { ; CHECK-LABEL: us2i: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i32 ret i32 %2 } define zeroext i32 @us2ui(i16 zeroext %0) { ; CHECK-LABEL: us2ui: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i32 ret i32 %2 } define i64 @us2ll(i16 zeroext %0) { ; CHECK-LABEL: us2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i64 ret i64 %2 } define i64 @us2ull(i16 zeroext %0) { ; CHECK-LABEL: us2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i64 ret i64 %2 } define float @us2f(i16 zeroext %x) { ; CHECK-LABEL: us2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i16 %x to float ret float %r } define double @us2d(i16 zeroext %x) { ; CHECK-LABEL: us2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i16 %x to double ret double %r } define fp128 @us2q(i16 zeroext) { ; CHECK-LABEL: us2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = uitofp i16 %0 to fp128 ret fp128 %2 } define signext i8 @c2c(i8 returned signext %0) { ; CHECK-LABEL: c2c: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i8 %0 } define zeroext i8 @c2uc(i8 returned signext %0) { ; CHECK-LABEL: c2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 %0 } define signext i16 @c2s(i8 signext %0) { ; CHECK-LABEL: c2s: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i16 ret i16 %2 } define zeroext i16 @c2us(i8 signext %0) { ; CHECK-LABEL: c2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i16 ret i16 %2 } define signext i32 @c2i(i8 signext %0) { ; CHECK-LABEL: c2i: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i32 ret i32 %2 } define zeroext i32 @c2ui(i8 signext %0) { ; CHECK-LABEL: c2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i32 ret i32 %2 } define i64 @c2ll(i8 signext %0) { ; CHECK-LABEL: c2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i64 ret i64 %2 } define i64 @c2ull(i8 signext %0) { ; CHECK-LABEL: c2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i64 ret i64 %2 } define float @c2f(i8 signext %x) { ; CHECK-LABEL: c2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i8 %x to float ret float %r } define double @c2d(i8 signext %x) { ; CHECK-LABEL: c2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sitofp i8 %x to double ret double %r } define fp128 @c2q(i8 signext) { ; CHECK-LABEL: c2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sitofp i8 %0 to fp128 ret fp128 %2 } define signext i8 @uc2c(i8 returned zeroext %0) { ; CHECK-LABEL: uc2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 %0 } define zeroext i8 @uc2uc(i8 returned zeroext %0) { ; CHECK-LABEL: uc2uc: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i8 %0 } define signext i16 @uc2s(i8 zeroext %0) { ; CHECK-LABEL: uc2s: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i16 ret i16 %2 } define zeroext i16 @uc2us(i8 zeroext %0) { ; CHECK-LABEL: uc2us: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i16 ret i16 %2 } define signext i32 @uc2i(i8 zeroext %0) { ; CHECK-LABEL: uc2i: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i32 ret i32 %2 } define zeroext i32 @uc2ui(i8 zeroext %0) { ; CHECK-LABEL: uc2ui: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i32 ret i32 %2 } define i64 @uc2ll(i8 zeroext %0) { ; CHECK-LABEL: uc2ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i64 ret i64 %2 } define i64 @uc2ull(i8 zeroext %0) { ; CHECK-LABEL: uc2ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i64 ret i64 %2 } define float @uc2f(i8 zeroext %x) { ; CHECK-LABEL: uc2f: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i8 %x to float ret float %r } define double @uc2d(i8 zeroext %x) { ; CHECK-LABEL: uc2d: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i8 %x to double ret double %r } define fp128 @uc2q(i8 zeroext) { ; CHECK-LABEL: uc2q: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = uitofp i8 %0 to fp128 ret fp128 %2 } @@ -1178,30 +1178,30 @@ ; Function Attrs: norecurse nounwind readnone define i128 @i128() { ; CHECK-LABEL: i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: or %s1, -1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i128 -2147483648 } ; Function Attrs: norecurse nounwind readnone define i128 @ui128() { ; CHECK-LABEL: ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: or %s1, -1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i128 -2147483648 } ; Function Attrs: norecurse nounwind readnone define signext i8 @i1282c(i128 %0) { ; CHECK-LABEL: i1282c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i8 ret i8 %2 } @@ -1209,10 +1209,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @ui1282c(i128 %0) { ; CHECK-LABEL: ui1282c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i8 ret i8 %2 } @@ -1220,9 +1220,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @i1282uc(i128 %0) { ; CHECK-LABEL: i1282uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i8 ret i8 %2 } @@ -1230,9 +1230,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @ui1282uc(i128 %0) { ; CHECK-LABEL: ui1282uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i8 ret i8 %2 } @@ -1240,10 +1240,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @i1282s(i128 %0) { ; CHECK-LABEL: i1282s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i16 ret i16 %2 } @@ -1251,10 +1251,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @ui1282s(i128 %0) { ; CHECK-LABEL: ui1282s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i16 ret i16 %2 } @@ -1262,9 +1262,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @i1282us(i128 %0) { ; CHECK-LABEL: i1282us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i16 ret i16 %2 } @@ -1272,9 +1272,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @ui1282us(i128 %0) { ; CHECK-LABEL: ui1282us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i16 ret i16 %2 } @@ -1282,9 +1282,9 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @i1282i(i128 %0) { ; CHECK-LABEL: i1282i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i32 ret i32 %2 } @@ -1292,9 +1292,9 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @ui1282i(i128 %0) { ; CHECK-LABEL: ui1282i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i32 ret i32 %2 } @@ -1302,9 +1302,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @i1282ui(i128 %0) { ; CHECK-LABEL: i1282ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i32 ret i32 %2 } @@ -1312,9 +1312,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @ui1282ui(i128 %0) { ; CHECK-LABEL: ui1282ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i32 ret i32 %2 } @@ -1322,8 +1322,8 @@ ; Function Attrs: norecurse nounwind readnone define i64 @i1282ll(i128 %0) { ; CHECK-LABEL: i1282ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i64 ret i64 %2 } @@ -1331,8 +1331,8 @@ ; Function Attrs: norecurse nounwind readnone define i64 @ui1282ll(i128 %0) { ; CHECK-LABEL: ui1282ll: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i64 ret i64 %2 } @@ -1340,8 +1340,8 @@ ; Function Attrs: norecurse nounwind readnone define i64 @i1282ull(i128 %0) { ; CHECK-LABEL: i1282ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i64 ret i64 %2 } @@ -1349,8 +1349,8 @@ ; Function Attrs: norecurse nounwind readnone define i64 @ui1282ull(i128 %0) { ; CHECK-LABEL: ui1282ull: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) %2 = trunc i128 %0 to i64 ret i64 %2 } @@ -1358,16 +1358,16 @@ ; Function Attrs: norecurse nounwind readnone define i128 @i1282ui128(i128 returned %0) { ; CHECK-LABEL: i1282ui128: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i128 %0 } ; Function Attrs: norecurse nounwind readnone define i128 @ui1282i128(i128 returned %0) { ; CHECK-LABEL: ui1282i128: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret i128 %0 } @@ -1478,9 +1478,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @ll2i128(i64 %0) { ; CHECK-LABEL: ll2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i64 %0 to i128 ret i128 %2 } @@ -1488,9 +1488,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @ll2ui128(i64 %0) { ; CHECK-LABEL: ll2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i64 %0 to i128 ret i128 %2 } @@ -1498,9 +1498,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @ull2i128(i64 %0) { ; CHECK-LABEL: ull2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i64 %0 to i128 ret i128 %2 } @@ -1508,9 +1508,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @ull2ui128(i64 %0) { ; CHECK-LABEL: ull2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i64 %0 to i128 ret i128 %2 } @@ -1518,9 +1518,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @i2i128(i32 signext %0) { ; CHECK-LABEL: i2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i32 %0 to i128 ret i128 %2 } @@ -1528,9 +1528,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @i2ui128(i32 signext %0) { ; CHECK-LABEL: i2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i32 %0 to i128 ret i128 %2 } @@ -1538,9 +1538,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @ui2i128(i32 zeroext %0) { ; CHECK-LABEL: ui2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i32 %0 to i128 ret i128 %2 } @@ -1548,9 +1548,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @ui2ui128(i32 zeroext %0) { ; CHECK-LABEL: ui2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i32 %0 to i128 ret i128 %2 } @@ -1558,9 +1558,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @s2i128(i16 signext %0) { ; CHECK-LABEL: s2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i16 %0 to i128 ret i128 %2 } @@ -1568,9 +1568,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @s2ui128(i16 signext %0) { ; CHECK-LABEL: s2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i16 %0 to i128 ret i128 %2 } @@ -1578,9 +1578,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @us2i128(i16 zeroext %0) { ; CHECK-LABEL: us2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i128 ret i128 %2 } @@ -1588,9 +1588,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @us2ui128(i16 zeroext %0) { ; CHECK-LABEL: us2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i128 ret i128 %2 } @@ -1598,9 +1598,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @c2i128(i8 signext %0) { ; CHECK-LABEL: c2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i128 ret i128 %2 } @@ -1608,9 +1608,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @char2ui128(i8 signext %0) { ; CHECK-LABEL: char2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = sext i8 %0 to i128 ret i128 %2 } @@ -1618,9 +1618,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @uc2i128(i8 zeroext %0) { ; CHECK-LABEL: uc2i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i128 ret i128 %2 } @@ -1628,9 +1628,9 @@ ; Function Attrs: norecurse nounwind readnone define i128 @uc2ui128(i8 zeroext %0) { ; CHECK-LABEL: uc2ui128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i128 ret i128 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/constants.ll b/llvm/test/CodeGen/VE/Scalar/constants.ll --- a/llvm/test/CodeGen/VE/Scalar/constants.ll +++ b/llvm/test/CodeGen/VE/Scalar/constants.ll @@ -2,351 +2,351 @@ define i8 @p0i8() { ; CHECK-LABEL: p0i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 0 } define signext i8 @p0si8() { ; CHECK-LABEL: p0si8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 0 } define zeroext i8 @p0zi8() { ; CHECK-LABEL: p0zi8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 0 } define i8 @p128i8() { ; CHECK-LABEL: p128i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 128 } define signext i8 @p128si8() { ; CHECK-LABEL: p128si8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 128 } define zeroext i8 @p128zi8() { ; CHECK-LABEL: p128zi8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 128 } define i8 @p256i8() { ; CHECK-LABEL: p256i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 256 } define signext i8 @p256si8() { ; CHECK-LABEL: p256si8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 256 } define zeroext i8 @p256zi8() { ; CHECK-LABEL: p256zi8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i8 256 } define i16 @p0i16() { ; CHECK-LABEL: p0i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i16 0 } define signext i16 @p0si16() { ; CHECK-LABEL: p0si16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i16 0 } define zeroext i16 @p0zi16() { ; CHECK-LABEL: p0zi16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i16 0 } define i32 @p0i32() { ; CHECK-LABEL: p0i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 0 } define signext i32 @p0si32() { ; CHECK-LABEL: p0si32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 0 } define zeroext i32 @p0zi32() { ; CHECK-LABEL: p0zi32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 0 } define i32 @p128i32() { ; CHECK-LABEL: p128i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 128 } define signext i32 @p128si32() { ; CHECK-LABEL: p128si32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 128 } define zeroext i32 @p128zi32() { ; CHECK-LABEL: p128zi32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i32 128 } define i64 @p0i64() { ; CHECK-LABEL: p0i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 0 } define signext i64 @p0si64() { ; CHECK-LABEL: p0si64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 0 } define zeroext i64 @p0zi64() { ; CHECK-LABEL: p0zi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 0 } define i64 @p128i64() { ; CHECK-LABEL: p128i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 128 } define signext i64 @p128si64() { ; CHECK-LABEL: p128si64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 128 } define zeroext i64 @p128zi64() { ; CHECK-LABEL: p128zi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 128 } define i64 @p2264924160i64() { ; CHECK-LABEL: p2264924160i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2030043136 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2264924160 } define signext i64 @p2264924160si64() { ; CHECK-LABEL: p2264924160si64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2030043136 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2264924160 } define zeroext i64 @p2264924160zi64() { ; CHECK-LABEL: p2264924160zi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2030043136 ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2264924160 } define i64 @p2147483647i64() { ; CHECK-LABEL: p2147483647i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2147483647 } define signext i64 @p2147483647si64() { ; CHECK-LABEL: p2147483647si64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2147483647 } define zeroext i64 @p2147483647zi64() { ; CHECK-LABEL: p2147483647zi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 2147483647 } define i64 @p15032385535i64() { ; CHECK-LABEL: p15032385535i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea.sl %s0, 3(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 15032385535 } define signext i64 @p15032385535si64() { ; CHECK-LABEL: p15032385535si64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea.sl %s0, 3(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 15032385535 } define zeroext i64 @p15032385535zi64() { ; CHECK-LABEL: p15032385535zi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea.sl %s0, 3(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 15032385535 } define i64 @p15032385536i64() { ; CHECK-LABEL: p15032385536i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, 3(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 15032385536 } define signext i64 @p15032385536si64() { ; CHECK-LABEL: p15032385536si64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, 3(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 15032385536 } define zeroext i64 @p15032385536zi64() { ; CHECK-LABEL: p15032385536zi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, 3(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret i64 15032385536 } define float @m5f32() { ; CHECK-LABEL: m5f32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -1063256064 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float -5.000000e+00 } define double @m5f64() { ; CHECK-LABEL: m5f64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -1072431104 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double -5.000000e+00 } define float @p2p3f32() { ; CHECK-LABEL: p2p3f32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 1075000115 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0x4002666660000000 ; 2.3 } define double @p2p3f64() { ; CHECK-LABEL: p2p3f64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 1717986918 ; CHECK-NEXT: lea.sl %s0, 1073899110(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 2.3 } define float @p128p3f32() { ; CHECK-LABEL: p128p3f32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 1124093133 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0x40600999A0000000 ; 128.3 } define double @p128p3f64() { ; CHECK-LABEL: p128p3f64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -1717986918 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, 1080035737(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 128.3 } diff --git a/llvm/test/CodeGen/VE/Scalar/ctlz.ll b/llvm/test/CodeGen/VE/Scalar/ctlz.ll --- a/llvm/test/CodeGen/VE/Scalar/ctlz.ll +++ b/llvm/test/CodeGen/VE/Scalar/ctlz.ll @@ -8,265 +8,265 @@ define i128 @func128(i128 %p){ ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s2, %s1, (0)1 ; CHECK-NEXT: ldz %s1, %s1 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, 64(, %s0) ; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true) ret i128 %r } define i64 @func64(i64 %p) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 true) ret i64 %r } define signext i32 @func32s(i32 signext %p) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true) ret i32 %r } define zeroext i32 @func32z(i32 zeroext %p) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true) ret i32 %r } define signext i16 @func16s(i16 signext %p) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true) ret i16 %r } define zeroext i16 @func16z(i16 zeroext %p) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true) ret i16 %r } define signext i8 @func8s(i8 signext %p) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true) ret i8 %r } define zeroext i8 @func8z(i8 zeroext %p) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true) ret i8 %r } define i128 @func128i(){ ; CHECK-LABEL: func128i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 112 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctlz.i128(i128 65535, i1 true) ret i128 %r } define i64 @func64i() { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 48, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.ctlz.i64(i64 65535, i1 true) ret i64 %r } define signext i32 @func32is() { ; CHECK-LABEL: func32is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true) ret i32 %r } define zeroext i32 @func32iz() { ; CHECK-LABEL: func32iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true) ret i32 %r } define signext i16 @func16is() { ; CHECK-LABEL: func16is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true) ret i16 %r } define zeroext i16 @func16iz() { ; CHECK-LABEL: func16iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true) ret i16 %r } define signext i8 @func8is() { ; CHECK-LABEL: func8is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true) ret i8 %r } define zeroext i8 @func8iz() { ; CHECK-LABEL: func8iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true) ret i8 %r } define i128 @func128x(i128 %p){ ; CHECK-LABEL: func128x: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s2, %s1, (0)1 ; CHECK-NEXT: ldz %s1, %s1 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, 64(, %s0) ; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false) ret i128 %r } define i64 @func64x(i64 %p) { ; CHECK-LABEL: func64x: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 false) ret i64 %r } define signext i32 @func32sx(i32 signext %p) { ; CHECK-LABEL: func32sx: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false) ret i32 %r } define zeroext i32 @func32zx(i32 zeroext %p) { ; CHECK-LABEL: func32zx: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false) ret i32 %r } define signext i16 @func16sx(i16 signext %p) { ; CHECK-LABEL: func16sx: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false) ret i16 %r } define zeroext i16 @func16zx(i16 zeroext %p) { ; CHECK-LABEL: func16zx: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false) ret i16 %r } define signext i8 @func8sx(i8 signext %p) { ; CHECK-LABEL: func8sx: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false) ret i8 %r } define zeroext i8 @func8zx(i8 zeroext %p) { ; CHECK-LABEL: func8zx: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false) ret i8 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/ctpop.ll b/llvm/test/CodeGen/VE/Scalar/ctpop.ll --- a/llvm/test/CodeGen/VE/Scalar/ctpop.ll +++ b/llvm/test/CodeGen/VE/Scalar/ctpop.ll @@ -8,151 +8,151 @@ define i128 @func128(i128 %p) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: pcnt %s1, %s1 ; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: adds.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctpop.i128(i128 %p) ret i128 %r } define i64 @func64(i64 %p) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.ctpop.i64(i64 %p) ret i64 %r } define signext i32 @func32s(i32 signext %p) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctpop.i32(i32 %p) ret i32 %r } define zeroext i32 @func32z(i32 zeroext %p) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctpop.i32(i32 %p) ret i32 %r } define signext i16 @func16s(i16 signext %p) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctpop.i16(i16 %p) ret i16 %r } define zeroext i16 @func16z(i16 zeroext %p) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctpop.i16(i16 %p) ret i16 %r } define signext i8 @func8s(i8 signext %p) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctpop.i8(i8 %p) ret i8 %r } define zeroext i8 @func8z(i8 zeroext %p) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctpop.i8(i8 %p) ret i8 %r } define i128 @func128i() { ; CHECK-LABEL: func128i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctpop.i128(i128 65535) ret i128 %r } define i64 @func64i() { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.ctpop.i64(i64 65535) ret i64 %r } define signext i32 @func32is() { ; CHECK-LABEL: func32is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctpop.i32(i32 65535) ret i32 %r } define zeroext i32 @func32iz() { ; CHECK-LABEL: func32iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.ctpop.i32(i32 65535) ret i32 %r } define signext i16 @func16si() { ; CHECK-LABEL: func16si: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctpop.i16(i16 65535) ret i16 %r } define zeroext i16 @func16zi() { ; CHECK-LABEL: func16zi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 16, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.ctpop.i16(i16 65535) ret i16 %r } define signext i8 @func8si() { ; CHECK-LABEL: func8si: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctpop.i8(i8 255) ret i8 %r } define zeroext i8 @func8zi() { ; CHECK-LABEL: func8zi: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.ctpop.i8(i8 255) ret i8 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/cttz.ll b/llvm/test/CodeGen/VE/Scalar/cttz.ll --- a/llvm/test/CodeGen/VE/Scalar/cttz.ll +++ b/llvm/test/CodeGen/VE/Scalar/cttz.ll @@ -8,7 +8,7 @@ define i128 @func128(i128 %p) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: lea %s3, -1(, %s0) ; CHECK-NEXT: nnd %s0, %s0, %s3 @@ -19,163 +19,163 @@ ; CHECK-NEXT: lea %s0, 64(, %s0) ; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true) ret i128 %r } define i64 @func64(i64 %p) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -1(, %s0) ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true) ret i64 %r } define signext i32 @func32s(i32 signext %p) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true) ret i32 %r } define zeroext i32 @func32z(i32 zeroext %p) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true) ret i32 %r } define signext i16 @func16s(i16 signext %p) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true) ret i16 %r } define zeroext i16 @func16z(i16 zeroext %p) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true) ret i16 %r } define signext i8 @func8s(i8 signext %p) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true) ret i8 %r } define zeroext i8 @func8z(i8 zeroext %p) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true) ret i8 %r } define i128 @func128i() { ; CHECK-LABEL: func128i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.cttz.i128(i128 65280, i1 true) ret i128 %r } define i64 @func64i() { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i64 @llvm.cttz.i64(i64 65280, i1 true) ret i64 %r } define signext i32 @func32is() { ; CHECK-LABEL: func32is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true) ret i32 %r } define zeroext i32 @func32iz() { ; CHECK-LABEL: func32iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true) ret i32 %r } define signext i16 @func16is() { ; CHECK-LABEL: func16is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true) ret i16 %r } define zeroext i16 @func16iz() { ; CHECK-LABEL: func16iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 8, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true) ret i16 %r } define signext i8 @func8is() { ; CHECK-LABEL: func8is: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 4, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.cttz.i8(i8 240, i1 true) ret i8 %r } define zeroext i8 @func8iz() { ; CHECK-LABEL: func8iz: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 4, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = tail call i8 @llvm.cttz.i8(i8 240, i1 true) ret i8 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/div.ll b/llvm/test/CodeGen/VE/Scalar/div.ll --- a/llvm/test/CodeGen/VE/Scalar/div.ll +++ b/llvm/test/CodeGen/VE/Scalar/div.ll @@ -16,9 +16,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @divi64(i64 %a, i64 %b) { ; CHECK-LABEL: divi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sdiv i64 %a, %b ret i64 %r } @@ -26,10 +26,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @divi32(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: divi32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sdiv i32 %a, %b ret i32 %r } @@ -50,9 +50,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @divu64(i64 %a, i64 %b) { ; CHECK-LABEL: divu64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i64 %a, %b ret i64 %r } @@ -60,10 +60,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: divu32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i32 %a, %b ret i32 %r } @@ -71,11 +71,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @divi16(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: divi16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a32 = sext i16 %a to i32 %b32 = sext i16 %b to i32 %r32 = sdiv i32 %a32, %b32 @@ -86,10 +86,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: divu16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i16 %a, %b ret i16 %r } @@ -97,11 +97,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @divi8(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: divi8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a32 = sext i8 %a to i32 %b32 = sext i8 %b to i32 %r32 = sdiv i32 %a32, %b32 @@ -112,10 +112,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: divu8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i8 %a, %b ret i8 %r } @@ -138,9 +138,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @divi64ri(i64 %a, i64 %b) { ; CHECK-LABEL: divi64ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.l %s0, %s0, (62)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sdiv i64 %a, 3 ret i64 %r } @@ -148,10 +148,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @divi32ri(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: divi32ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sdiv i32 %a, 3 ret i32 %r } @@ -174,9 +174,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @divu64ri(i64 %a, i64 %b) { ; CHECK-LABEL: divu64ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.l %s0, %s0, (62)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i64 %a, 3 ret i64 %r } @@ -184,10 +184,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: divu32ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s0, %s0, (62)0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i32 %a, 3 ret i32 %r } @@ -212,9 +212,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @divi64li(i64 %a, i64 %b) { ; CHECK-LABEL: divi64li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.l %s0, 3, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sdiv i64 3, %b ret i64 %r } @@ -222,10 +222,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @divi32li(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: divi32li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s0, 3, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = sdiv i32 3, %b ret i32 %r } @@ -250,9 +250,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @divu64li(i64 %a, i64 %b) { ; CHECK-LABEL: divu64li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.l %s0, 3, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i64 3, %b ret i64 %r } @@ -260,10 +260,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: divu32li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s0, 3, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = udiv i32 3, %b ret i32 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/fabs.ll b/llvm/test/CodeGen/VE/Scalar/fabs.ll --- a/llvm/test/CodeGen/VE/Scalar/fabs.ll +++ b/llvm/test/CodeGen/VE/Scalar/fabs.ll @@ -30,11 +30,11 @@ ; Function Attrs: nounwind readnone define float @fabs_float_var(float %0) { ; CHECK-LABEL: fabs_float_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: and %s0, %s0, (33)0 ; CHECK-NEXT: sll %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast float @llvm.fabs.f32(float %0) ret float %2 } @@ -45,9 +45,9 @@ ; Function Attrs: nounwind readnone define double @fabs_double_var(double %0) { ; CHECK-LABEL: fabs_double_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (1)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast double @llvm.fabs.f64(double %0) ret double %2 } @@ -77,62 +77,62 @@ ; Function Attrs: norecurse nounwind readnone define float @fabs_float_zero() { ; CHECK-LABEL: fabs_float_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0.000000e+00 } ; Function Attrs: norecurse nounwind readnone define double @fabs_double_zero() { ; CHECK-LABEL: fabs_double_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 0.000000e+00 } ; Function Attrs: norecurse nounwind readnone define fp128 @fabs_quad_zero() { ; CHECK-LABEL: fabs_quad_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s1, (, %s2) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret fp128 0xL00000000000000000000000000000000 } ; Function Attrs: norecurse nounwind readnone define float @fabs_float_const() { ; CHECK-LABEL: fabs_float_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 1073741824 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 2.000000e+00 } ; Function Attrs: norecurse nounwind readnone define double @fabs_double_const() { ; CHECK-LABEL: fabs_double_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 1073741824 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 2.000000e+00 } ; Function Attrs: nounwind readnone define fp128 @fabs_quad_const() { ; CHECK-LABEL: fabs_quad_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s1, (, %s2) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = tail call fast fp128 @llvm.fabs.f128(fp128 0xL0000000000000000C000000000000000) ret fp128 %1 } diff --git a/llvm/test/CodeGen/VE/Scalar/fcopysign.ll b/llvm/test/CodeGen/VE/Scalar/fcopysign.ll --- a/llvm/test/CodeGen/VE/Scalar/fcopysign.ll +++ b/llvm/test/CodeGen/VE/Scalar/fcopysign.ll @@ -31,7 +31,7 @@ ; Function Attrs: nounwind readnone define float @copysign_float_var(float %0, float %1) { ; CHECK-LABEL: copysign_float_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s1, %s1, 32 ; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: and %s2, %s2, (32)0 @@ -40,7 +40,7 @@ ; CHECK-NEXT: and %s0, %s0, (33)0 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast float @llvm.copysign.f32(float %0, float %1) ret float %3 } @@ -51,11 +51,11 @@ ; Function Attrs: nounwind readnone define double @copysign_double_var(double %0, double %1) { ; CHECK-LABEL: copysign_double_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s1, %s1, (1)1 ; CHECK-NEXT: and %s0, %s0, (1)0 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast double @llvm.copysign.f64(double %0, double %1) ret double %3 } @@ -91,13 +91,13 @@ ; Function Attrs: nounwind readnone define float @copysign_float_zero(float %0) { ; CHECK-LABEL: copysign_float_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast float @llvm.copysign.f32(float 0.000000e+00, float %0) ret float %2 } @@ -105,9 +105,9 @@ ; Function Attrs: nounwind readnone define double @copysign_double_zero(double %0) { ; CHECK-LABEL: copysign_double_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (1)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast double @llvm.copysign.f64(double 0.000000e+00, double %0) ret double %2 } @@ -142,7 +142,7 @@ ; Function Attrs: nounwind readnone define float @copysign_float_const(float %0) { ; CHECK-LABEL: copysign_float_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 @@ -150,7 +150,7 @@ ; CHECK-NEXT: lea %s1, 1073741824 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast float @llvm.copysign.f32(float -2.000000e+00, float %0) ret float %2 } @@ -158,11 +158,11 @@ ; Function Attrs: nounwind readnone define double @copysign_double_const(double %0) { ; CHECK-LABEL: copysign_double_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (1)1 ; CHECK-NEXT: lea.sl %s1, 1073741824 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast double @llvm.copysign.f64(double -2.000000e+00, double %0) ret double %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/fcos.ll b/llvm/test/CodeGen/VE/Scalar/fcos.ll --- a/llvm/test/CodeGen/VE/Scalar/fcos.ll +++ b/llvm/test/CodeGen/VE/Scalar/fcos.ll @@ -80,18 +80,18 @@ ; Function Attrs: norecurse nounwind readnone define float @fcos_float_zero() { ; CHECK-LABEL: fcos_float_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 1065353216 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 1.000000e+00 } ; Function Attrs: norecurse nounwind readnone define double @fcos_double_zero() { ; CHECK-LABEL: fcos_double_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 1072693248 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 1.000000e+00 } @@ -116,19 +116,19 @@ ; Function Attrs: norecurse nounwind readnone define float @fcos_float_const() { ; CHECK-LABEL: fcos_float_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -1093332685 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0xBFDAA22660000000 } ; Function Attrs: norecurse nounwind readnone define double @fcos_double_const() { ; CHECK-LABEL: fcos_double_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, 1465086469 ; CHECK-NEXT: lea.sl %s0, -1076190682(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 0xBFDAA22657537205 } diff --git a/llvm/test/CodeGen/VE/Scalar/fp_add.ll b/llvm/test/CodeGen/VE/Scalar/fp_add.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_add.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_add.ll @@ -2,129 +2,129 @@ define float @func1(float %a, float %b) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fadd.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd float %a, %b ret float %r } define double @func2(double %a, double %b) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd double %a, %b ret double %r } define fp128 @func3(fp128 %a, fp128 %b) { ; CHECK-LABEL: func3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fadd.q %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd fp128 %a, %b ret fp128 %r } define float @func4(float %a) { ; CHECK-LABEL: func4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1084227584 ; CHECK-NEXT: fadd.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd float %a, 5.000000e+00 ret float %r } define double @func5(double %a) { ; CHECK-LABEL: func5: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1075052544 ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd double %a, 5.000000e+00 ret double %r } define fp128 @func6(fp128 %a) { ; CHECK-LABEL: func6: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fadd.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd fp128 %a, 0xL00000000000000004001400000000000 ret fp128 %r } define float @func7(float %a) { ; CHECK-LABEL: func7: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 2139095039 ; CHECK-NEXT: fadd.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd float %a, 0x47EFFFFFE0000000 ret float %r } define double @func8(double %a) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1) ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd double %a, 0x7FEFFFFFFFFFFFFF ret double %r } define fp128 @func9(fp128 %a) { ; CHECK-LABEL: func9: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fadd.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF ret fp128 %r } define float @fadds_imm(float %a) { ; CHECK-LABEL: fadds_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fadd.s %s0, %s0, (2)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd float %a, -2.e+00 ret float %r } define double @faddd_imm(double %a) { ; CHECK-LABEL: faddd_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fadd.d %s0, %s0, (2)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd double %a, -2.e+00 ret double %r } define fp128 @faddq_imm(fp128 %a) { ; CHECK-LABEL: faddq_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fadd.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd fp128 %a, 0xLA0000000000000000000000000000000 ret fp128 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/fp_div.ll b/llvm/test/CodeGen/VE/Scalar/fp_div.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_div.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_div.ll @@ -2,18 +2,18 @@ define float @func1(float %a, float %b) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fdiv.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fdiv float %a, %b ret float %r } define double @func2(double %a, double %b) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fdiv.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fdiv double %a, %b ret double %r } @@ -32,20 +32,20 @@ define float @func4(float %a) { ; CHECK-LABEL: func4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1084227584 ; CHECK-NEXT: fdiv.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fdiv float %a, 5.000000e+00 ret float %r } define double @func5(double %a) { ; CHECK-LABEL: func5: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1075052544 ; CHECK-NEXT: fdiv.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fdiv double %a, 5.000000e+00 ret double %r } @@ -69,22 +69,22 @@ define float @func7(float %a) { ; CHECK-LABEL: func7: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 2139095039 ; CHECK-NEXT: fdiv.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fdiv float %a, 0x47EFFFFFE0000000 ret float %r } define double @func8(double %a) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1) ; CHECK-NEXT: fdiv.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fdiv double %a, 0x7FEFFFFFFFFFFFFF ret double %r } diff --git a/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll b/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll @@ -67,7 +67,7 @@ define void @func_fp32i16(i16* %fl.ptr, float %val) { ; CHECK-LABEL: func_fp32i16: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo ; CHECK-NEXT: and %s0, %s0, (32)0 @@ -75,7 +75,7 @@ ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s0, (, %s18) -; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 %val.asf = call i16 @llvm.convert.to.fp16.f32(float %val) store i16 %val.asf, i16* %fl.ptr @@ -85,8 +85,8 @@ define half @func_fp32fp16(half* %fl.ptr, float %a) { ; CHECK-LABEL: func_fp32fp16: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill -; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill +; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill +; CHECK-NEXT: st %s19, 296(, %s11) # 8-byte Folded Spill ; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo ; CHECK-NEXT: and %s0, %s0, (32)0 @@ -100,8 +100,8 @@ ; CHECK-NEXT: or %s0, 0, %s19 ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s19, (, %s18) -; CHECK-NEXT: ld %s19, 56(, %s9) # 8-byte Folded Reload -; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; CHECK-NEXT: ld %s19, 296(, %s11) # 8-byte Folded Reload +; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 %a.asd = fptrunc float %a to half store half %a.asd, half* %fl.ptr @@ -110,10 +110,10 @@ define double @func_fp32fp64(float* %a) { ; CHECK-LABEL: func_fp32fp64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: cvt.d.s %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a.val = load float, float* %a, align 4 %a.asd = fpext float %a.val to double ret double %a.asd @@ -122,7 +122,7 @@ define void @func_fp64i16(i16* %fl.ptr, double %val) { ; CHECK-LABEL: func_fp64i16: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: lea %s0, __truncdfhf2@lo ; CHECK-NEXT: and %s0, %s0, (32)0 @@ -130,7 +130,7 @@ ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s0, (, %s18) -; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 %val.asf = call i16 @llvm.convert.to.fp16.f64(double %val) store i16 %val.asf, i16* %fl.ptr @@ -140,7 +140,7 @@ define void @func_fp64fp16(half* %fl.ptr, double %val) { ; CHECK-LABEL: func_fp64fp16: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: lea %s0, __truncdfhf2@lo ; CHECK-NEXT: and %s0, %s0, (32)0 @@ -148,7 +148,7 @@ ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s0, (, %s18) -; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 %val.asf = fptrunc double %val to half store half %val.asf, half* %fl.ptr @@ -157,10 +157,10 @@ define void @func_fp64fp32(float* %fl.ptr, double %val) { ; CHECK-LABEL: func_fp64fp32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cvt.s.d %s1, %s1 ; CHECK-NEXT: stu %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %val.asf = fptrunc double %val to float store float %val.asf, float* %fl.ptr ret void diff --git a/llvm/test/CodeGen/VE/Scalar/fp_fneg.ll b/llvm/test/CodeGen/VE/Scalar/fp_fneg.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_fneg.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_fneg.ll @@ -28,13 +28,13 @@ ; Function Attrs: norecurse nounwind readnone define float @fneg_float(float %0) { ; CHECK-LABEL: fneg_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 32 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fneg float %0 ret float %2 } @@ -42,9 +42,9 @@ ; Function Attrs: norecurse nounwind readnone define double @fneg_double(double %0) { ; CHECK-LABEL: fneg_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, (1)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = fneg double %0 ret double %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/fp_mul.ll b/llvm/test/CodeGen/VE/Scalar/fp_mul.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_mul.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_mul.ll @@ -2,133 +2,133 @@ define float @func1(float %a, float %b) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float %a, %b ret float %r } define double @func2(double %a, double %b) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul double %a, %b ret double %r } define fp128 @func3(fp128 %a, fp128 %b) { ; CHECK-LABEL: func3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.q %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul fp128 %a, %b ret fp128 %r } define float @func4(float %a) { ; CHECK-LABEL: func4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1084227584 ; CHECK-NEXT: fmul.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float %a, 5.000000e+00 ret float %r } define double @func5(double %a) { ; CHECK-LABEL: func5: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 1075052544 ; CHECK-NEXT: fmul.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul double %a, 5.000000e+00 ret double %r } define fp128 @func6(fp128 %a) { ; CHECK-LABEL: func6: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fmul.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul fp128 %a, 0xL00000000000000004001400000000000 ret fp128 %r } define float @func7(float %a) { ; CHECK-LABEL: func7: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 2139095039 ; CHECK-NEXT: fmul.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float %a, 0x47EFFFFFE0000000 ret float %r } define double @func8(double %a) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1) ; CHECK-NEXT: fmul.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul double %a, 0x7FEFFFFFFFFFFFFF ret double %r } define fp128 @func9(fp128 %a) { ; CHECK-LABEL: func9: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fmul.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF ret fp128 %r } define float @fmuls_ir(float %a) { ; CHECK-LABEL: fmuls_ir: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.s %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float 0.e+00, %a ret float %r } define float @fmuls_ri(float %a) { ; CHECK-LABEL: fmuls_ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.s %s0, %s0, (2)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float %a, -2. ret float %r } define float @fmuls_ri2(float %a) { ; CHECK-LABEL: fmuls_ri2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.s %s0, %s0, (3)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float %a, -36893488147419103232. ret float %r } define float @fmuls_ri3(float %a) { ; CHECK-LABEL: fmuls_ri3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmul.s %s0, %s0, (9)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fmul float %a, 1.175494210692441075487029444849287348827052428745893333857174530571588870475618904265502351336181163787841796875E-38 ret float %r } diff --git a/llvm/test/CodeGen/VE/Scalar/fp_sub.ll b/llvm/test/CodeGen/VE/Scalar/fp_sub.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_sub.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_sub.ll @@ -2,115 +2,115 @@ define float @func1(float %a, float %b) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fsub.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fsub float %a, %b ret float %r } define double @func2(double %a, double %b) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fsub.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fsub double %a, %b ret double %r } define fp128 @func3(fp128 %a, fp128 %b) { ; CHECK-LABEL: func3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fsub.q %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fsub fp128 %a, %b ret fp128 %r } define float @func4(float %a) { ; CHECK-LABEL: func4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, -1063256064 ; CHECK-NEXT: fadd.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd float %a, -5.000000e+00 ret float %r } define double @func5(double %a) { ; CHECK-LABEL: func5: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, -1072431104 ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd double %a, -5.000000e+00 ret double %r } define fp128 @func6(fp128 %a) { ; CHECK-LABEL: func6: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fadd.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd fp128 %a, 0xL0000000000000000C001400000000000 ret fp128 %r } define float @func7(float %a) { ; CHECK-LABEL: func7: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, -8388609 ; CHECK-NEXT: fadd.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd float %a, 0xC7EFFFFFE0000000 ret float %r } define double @func8(double %a) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, -1048577(, %s1) ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd double %a, 0xFFEFFFFFFFFFFFFF ret double %r } define fp128 @func9(fp128 %a) { ; CHECK-LABEL: func9: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: fadd.q %s0, %s0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFF ret fp128 %r } define float @fsubs_ir(float %a) { ; CHECK-LABEL: fsubs_ir: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fsub.s %s0, 0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fsub float 0.e+00, %a ret float %r } define float @fsubs_ri(float %a) { ; CHECK-LABEL: fsubs_ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fadd.s %s0, %s0, (2)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = fsub float %a, 2.0e+00 ret float %r } diff --git a/llvm/test/CodeGen/VE/Scalar/fp_to_int.ll b/llvm/test/CodeGen/VE/Scalar/fp_to_int.ll --- a/llvm/test/CodeGen/VE/Scalar/fp_to_int.ll +++ b/llvm/test/CodeGen/VE/Scalar/fp_to_int.ll @@ -3,10 +3,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @f2c(float %a) { ; CHECK-LABEL: f2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi float %a to i8 ret i8 %conv @@ -15,10 +15,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @f2s(float %a) { ; CHECK-LABEL: f2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi float %a to i16 ret i16 %conv @@ -27,9 +27,9 @@ ; Function Attrs: norecurse nounwind readnone define i32 @f2i(float %a) { ; CHECK-LABEL: f2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi float %a to i32 ret i32 %conv @@ -38,10 +38,10 @@ ; Function Attrs: norecurse nounwind readnone define i64 @f2l(float %a) { ; CHECK-LABEL: f2l: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi float %a to i64 ret i64 %conv @@ -50,10 +50,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @f2uc(float %a) { ; CHECK-LABEL: f2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui float %a to i8 ret i8 %conv @@ -62,10 +62,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @f2us(float %a) { ; CHECK-LABEL: f2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui float %a to i16 ret i16 %conv @@ -74,10 +74,10 @@ ; Function Attrs: norecurse nounwind readnone define i32 @f2ui(float %a) { ; CHECK-LABEL: f2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui float %a to i32 ret i32 %conv @@ -86,7 +86,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @f2ul(float %a) { ; CHECK-LABEL: f2ul: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea.sl %s1, 1593835520 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fsub.s %s1, %s0, %s1 @@ -97,7 +97,7 @@ ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui float %a to i64 ret i64 %conv @@ -106,10 +106,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @d2c(double %a) { ; CHECK-LABEL: d2c: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi double %a to i8 ret i8 %conv @@ -118,10 +118,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @d2s(double %a) { ; CHECK-LABEL: d2s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi double %a to i16 ret i16 %conv @@ -130,9 +130,9 @@ ; Function Attrs: norecurse nounwind readnone define i32 @d2i(double %a) { ; CHECK-LABEL: d2i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi double %a to i32 ret i32 %conv @@ -141,9 +141,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @d2l(double %a) { ; CHECK-LABEL: d2l: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptosi double %a to i64 ret i64 %conv @@ -152,10 +152,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @d2uc(double %a) { ; CHECK-LABEL: d2uc: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui double %a to i8 ret i8 %conv @@ -164,10 +164,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @d2us(double %a) { ; CHECK-LABEL: d2us: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui double %a to i16 ret i16 %conv @@ -176,9 +176,9 @@ ; Function Attrs: norecurse nounwind readnone define i32 @d2ui(double %a) { ; CHECK-LABEL: d2ui: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui double %a to i32 ret i32 %conv @@ -187,7 +187,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @d2ul(double %a) { ; CHECK-LABEL: d2ul: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea.sl %s1, 1138753536 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fsub.d %s1, %s0, %s1 @@ -196,7 +196,7 @@ ; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = fptoui double %a to i64 ret i64 %conv diff --git a/llvm/test/CodeGen/VE/Scalar/fsin.ll b/llvm/test/CodeGen/VE/Scalar/fsin.ll --- a/llvm/test/CodeGen/VE/Scalar/fsin.ll +++ b/llvm/test/CodeGen/VE/Scalar/fsin.ll @@ -80,18 +80,18 @@ ; Function Attrs: norecurse nounwind readnone define float @fsin_float_zero() { ; CHECK-LABEL: fsin_float_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0.000000e+00 } ; Function Attrs: norecurse nounwind readnone define double @fsin_double_zero() { ; CHECK-LABEL: fsin_double_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 0.000000e+00 } @@ -116,20 +116,20 @@ ; Function Attrs: norecurse nounwind readnone define float @fsin_float_const() { ; CHECK-LABEL: fsin_float_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -1083652169 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0xBFED18F6E0000000 } ; Function Attrs: norecurse nounwind readnone define double @fsin_double_const() { ; CHECK-LABEL: fsin_double_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -355355578 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, -1074980618(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 0xBFED18F6EAD1B446 } diff --git a/llvm/test/CodeGen/VE/Scalar/fsqrt.ll b/llvm/test/CodeGen/VE/Scalar/fsqrt.ll --- a/llvm/test/CodeGen/VE/Scalar/fsqrt.ll +++ b/llvm/test/CodeGen/VE/Scalar/fsqrt.ll @@ -81,18 +81,18 @@ ; Function Attrs: norecurse nounwind readnone define float @fsqrt_float_zero() { ; CHECK-LABEL: fsqrt_float_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0.000000e+00 } ; Function Attrs: norecurse nounwind readnone define double @fsqrt_double_zero() { ; CHECK-LABEL: fsqrt_double_zero: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, 0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 0.000000e+00 } @@ -117,18 +117,18 @@ ; Function Attrs: norecurse nounwind readnone define float @fsqrt_float_const() { ; CHECK-LABEL: fsqrt_float_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -4194304 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret float 0xFFF8000000000000 } ; Function Attrs: norecurse nounwind readnone define double @fsqrt_double_const() { ; CHECK-LABEL: fsqrt_double_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s0, -524288 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret double 0xFFF8000000000000 } diff --git a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll @@ -0,0 +1,132 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=ve | FileCheck %s +; RUN: llc < %s -mtriple=ve -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=PIC %s + +define void @func() { +; CHECK-LABEL: func: +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: func: +; PIC: # %bb.0: +; PIC-NEXT: b.l.t (, %s10) + + ret void +} + +@vi8 = common dso_local local_unnamed_addr global i8 0, align 1 + +define i8 @func_gv() { +; CHECK-LABEL: func_gv: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s0, vi8@lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) +; CHECK-NEXT: ld1b.zx %s0, (, %s0) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: func_gv: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -176 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB1_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s0, vi8@got_lo +; PIC-NEXT: and %s0, %s0, (32)0 +; PIC-NEXT: lea.sl %s0, vi8@got_hi(, %s0) +; PIC-NEXT: ld %s0, (%s0, %s15) +; PIC-NEXT: ld1b.zx %s0, (, %s0) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + + %v = load i8, i8* @vi8, align 1 + ret i8 %v +} + +define i32 @func_alloca(i32 signext %0) { +; CHECK-LABEL: func_alloca: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -192 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: stl %s0, 188(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: func_alloca: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -192 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB2_2: +; PIC-NEXT: stl %s0, 188(, %s11) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %2 = alloca i32, align 4 + store i32 %0, i32* %2, align 4 + %3 = load i32, i32* %2, align 4 + ret i32 %3 +} diff --git a/llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll b/llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll --- a/llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll +++ b/llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll @@ -2,55 +2,55 @@ define i64 @lea1a(i64 %x) nounwind { ; CHECK-LABEL: lea1a: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s0, (%s0) ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %asmtmp = tail call i64 asm "lea $0, ($1)", "=r,r"(i64 %x) nounwind ret i64 %asmtmp } define i64 @lea1b(i64 %x) nounwind { ; CHECK-LABEL: lea1b: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s0, (, %s0) ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %asmtmp = tail call i64 asm "lea $0, (, $1)", "=r,r"(i64 %x) nounwind ret i64 %asmtmp } define i64 @lea2(i64 %x, i64 %y) nounwind { ; CHECK-LABEL: lea2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s0, (%s0, %s1) ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %asmtmp = tail call i64 asm "lea $0, ($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind ret i64 %asmtmp } define i64 @lea3(i64 %x, i64 %y) nounwind { ; CHECK-LABEL: lea3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s0, 2048(%s0, %s1) ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %asmtmp = tail call i64 asm "lea $0, 2048($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind ret i64 %asmtmp } define i64 @leasl3(i64 %x, i64 %y) nounwind { ; CHECK-LABEL: leasl3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea.sl %s0, 2048(%s1, %s0) ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %asmtmp = tail call i64 asm "lea.sl $0, 2048($1, $2)", "=r,r,r"(i64 %y, i64 %x) nounwind ret i64 %asmtmp } diff --git a/llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll b/llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll --- a/llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll +++ b/llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll @@ -2,7 +2,7 @@ define void @vld(i8* %p, i64 %i) nounwind { ; CHECK-LABEL: vld: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: #NO_APP @@ -12,7 +12,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind @@ -21,7 +21,7 @@ define void @vldvst(i8* %p, i64 %i) nounwind { ; CHECK-LABEL: vldvst: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: #NO_APP @@ -34,7 +34,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind %1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind @@ -44,7 +44,7 @@ define void @vld2vst2(i8* %p, i64 %i) nounwind { ; CHECK-LABEL: vld2vst2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: #APP ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: #NO_APP @@ -63,7 +63,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v1, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind %1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind diff --git a/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll b/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll --- a/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll +++ b/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll @@ -3,9 +3,9 @@ ; Function Attrs: norecurse nounwind readnone define float @c2f(i8 signext %a) { ; CHECK-LABEL: c2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i8 %a to float ret float %conv @@ -14,9 +14,9 @@ ; Function Attrs: norecurse nounwind readnone define float @s2f(i16 signext %a) { ; CHECK-LABEL: s2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i16 %a to float ret float %conv @@ -25,9 +25,9 @@ ; Function Attrs: norecurse nounwind readnone define float @i2f(i32 %a) { ; CHECK-LABEL: i2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i32 %a to float ret float %conv @@ -36,10 +36,10 @@ ; Function Attrs: norecurse nounwind readnone define float @l2f(i64 %a) { ; CHECK-LABEL: l2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i64 %a to float ret float %conv @@ -48,9 +48,9 @@ ; Function Attrs: norecurse nounwind readnone define float @uc2f(i8 zeroext %a) { ; CHECK-LABEL: uc2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i8 %a to float ret float %conv @@ -59,9 +59,9 @@ ; Function Attrs: norecurse nounwind readnone define float @us2f(i16 zeroext %a) { ; CHECK-LABEL: us2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.s.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i16 %a to float ret float %conv @@ -70,11 +70,11 @@ ; Function Attrs: norecurse nounwind readnone define float @ui2f(i32 %a) { ; CHECK-LABEL: ui2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i32 %a to float ret float %conv @@ -83,7 +83,7 @@ ; Function Attrs: norecurse nounwind readnone define float @ul2f(i64 %a) { ; CHECK-LABEL: ul2f: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cvt.d.l %s1, %s0 ; CHECK-NEXT: cvt.s.d %s1, %s1 @@ -95,7 +95,7 @@ ; CHECK-NEXT: fadd.s %s0, %s0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i64 %a to float ret float %conv @@ -104,9 +104,9 @@ ; Function Attrs: norecurse nounwind readnone define double @c2d(i8 signext %a) { ; CHECK-LABEL: c2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i8 %a to double ret double %conv @@ -115,9 +115,9 @@ ; Function Attrs: norecurse nounwind readnone define double @s2d(i16 signext %a) { ; CHECK-LABEL: s2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i16 %a to double ret double %conv @@ -126,9 +126,9 @@ ; Function Attrs: norecurse nounwind readnone define double @i2d(i32 %a) { ; CHECK-LABEL: i2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i32 %a to double ret double %conv @@ -137,9 +137,9 @@ ; Function Attrs: norecurse nounwind readnone define double @l2d(i64 %a) { ; CHECK-LABEL: l2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.l %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = sitofp i64 %a to double ret double %conv @@ -148,9 +148,9 @@ ; Function Attrs: norecurse nounwind readnone define double @uc2d(i8 zeroext %a) { ; CHECK-LABEL: uc2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i8 %a to double ret double %conv @@ -159,9 +159,9 @@ ; Function Attrs: norecurse nounwind readnone define double @us2d(i16 zeroext %a) { ; CHECK-LABEL: us2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cvt.d.w %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i16 %a to double ret double %conv @@ -170,10 +170,10 @@ ; Function Attrs: norecurse nounwind readnone define double @ui2d(i32 %a) { ; CHECK-LABEL: ui2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: cvt.d.l %s0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i32 %a to double ret double %conv @@ -182,7 +182,7 @@ ; Function Attrs: norecurse nounwind readnone define double @ul2d(i64 %a) { ; CHECK-LABEL: ul2d: -; CHECK: .LBB{{[0-9]+}}_2: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: srl %s1, %s0, 32 ; CHECK-NEXT: lea.sl %s2, 1160773632 ; CHECK-NEXT: or %s1, %s1, %s2 @@ -193,7 +193,7 @@ ; CHECK-NEXT: lea.sl %s2, 1127219200 ; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: fadd.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %conv = uitofp i64 %a to double ret double %conv diff --git a/llvm/test/CodeGen/VE/Scalar/left_shift.ll b/llvm/test/CodeGen/VE/Scalar/left_shift.ll --- a/llvm/test/CodeGen/VE/Scalar/left_shift.ll +++ b/llvm/test/CodeGen/VE/Scalar/left_shift.ll @@ -2,11 +2,11 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i8 %0 to i32 %4 = sext i8 %1 to i32 %5 = shl i32 %3, %4 @@ -16,11 +16,11 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i16 %0 to i32 %4 = sext i16 %1 to i32 %5 = shl i32 %3, %4 @@ -30,28 +30,28 @@ define i32 @func3(i32 %0, i32 %1) { ; CHECK-LABEL: func3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i32 %0, %1 ret i32 %3 } define i64 @func4(i64 %0, i64 %1) { ; CHECK-LABEL: func4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i64 %0, %1 ret i64 %3 } define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: func6: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i8 %0 to i32 %4 = zext i8 %1 to i32 %5 = shl i32 %3, %4 @@ -61,10 +61,10 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: func7: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i16 %0 to i32 %4 = zext i16 %1 to i32 %5 = shl i32 %3, %4 @@ -74,98 +74,98 @@ define i32 @func8(i32 %0, i32 %1) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i32 %0, %1 ret i32 %3 } define i64 @func9(i64 %0, i64 %1) { ; CHECK-LABEL: func9: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i64 %0, %1 ret i64 %3 } define signext i8 @func11(i8 signext %0) { ; CHECK-LABEL: func11: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i8 %0, 5 ret i8 %2 } define signext i16 @func12(i16 signext %0) { ; CHECK-LABEL: func12: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i16 %0, 5 ret i16 %2 } define i32 @func13(i32 %0) { ; CHECK-LABEL: func13: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i32 %0, 5 ret i32 %2 } define i64 @func14(i64 %0) { ; CHECK-LABEL: func14: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i64 %0, 5 ret i64 %2 } define zeroext i8 @func16(i8 zeroext %0) { ; CHECK-LABEL: func16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: lea %s1, 224 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i8 %0, 5 ret i8 %2 } define zeroext i16 @func17(i16 zeroext %0) { ; CHECK-LABEL: func17: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: lea %s1, 65504 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i16 %0, 5 ret i16 %2 } define i32 @func18(i32 %0) { ; CHECK-LABEL: func18: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i32 %0, 5 ret i32 %2 } define i64 @func19(i64 %0) { ; CHECK-LABEL: func19: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i64 %0, 5 ret i64 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/load-align1.ll b/llvm/test/CodeGen/VE/Scalar/load-align1.ll --- a/llvm/test/CodeGen/VE/Scalar/load-align1.ll +++ b/llvm/test/CodeGen/VE/Scalar/load-align1.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define double @loadf64com() { ; CHECK-LABEL: loadf64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load double, double* @vf64, align 1 ret double %1 } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define float @loadf32com() { ; CHECK-LABEL: loadf32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: ldu %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load float, float* @vf32, align 1 ret float %1 } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi64com() { ; CHECK-LABEL: loadi64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i64, i64* @vi64, align 1 ret i64 %1 } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define i32 @loadi32com() { ; CHECK-LABEL: loadi32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i32, i32* @vi32, align 1 ret i32 %1 } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define i16 @loadi16com() { ; CHECK-LABEL: loadi16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i16, i16* @vi16, align 1 ret i16 %1 } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define i8 @loadi8com() { ; CHECK-LABEL: loadi8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i8, i8* @vi8, align 1 ret i8 %1 } diff --git a/llvm/test/CodeGen/VE/Scalar/load-align2.ll b/llvm/test/CodeGen/VE/Scalar/load-align2.ll --- a/llvm/test/CodeGen/VE/Scalar/load-align2.ll +++ b/llvm/test/CodeGen/VE/Scalar/load-align2.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define double @loadf64com() { ; CHECK-LABEL: loadf64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load double, double* @vf64, align 2 ret double %1 } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define float @loadf32com() { ; CHECK-LABEL: loadf32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: ldu %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load float, float* @vf32, align 2 ret float %1 } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi64com() { ; CHECK-LABEL: loadi64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i64, i64* @vi64, align 2 ret i64 %1 } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define i32 @loadi32com() { ; CHECK-LABEL: loadi32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i32, i32* @vi32, align 2 ret i32 %1 } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define i16 @loadi16com() { ; CHECK-LABEL: loadi16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i16, i16* @vi16, align 2 ret i16 %1 } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define i8 @loadi8com() { ; CHECK-LABEL: loadi8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i8, i8* @vi8, align 2 ret i8 %1 } diff --git a/llvm/test/CodeGen/VE/Scalar/load-align4.ll b/llvm/test/CodeGen/VE/Scalar/load-align4.ll --- a/llvm/test/CodeGen/VE/Scalar/load-align4.ll +++ b/llvm/test/CodeGen/VE/Scalar/load-align4.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define double @loadf64com() { ; CHECK-LABEL: loadf64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load double, double* @vf64, align 4 ret double %1 } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define float @loadf32com() { ; CHECK-LABEL: loadf32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: ldu %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load float, float* @vf32, align 4 ret float %1 } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi64com() { ; CHECK-LABEL: loadi64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i64, i64* @vi64, align 4 ret i64 %1 } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define i32 @loadi32com() { ; CHECK-LABEL: loadi32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i32, i32* @vi32, align 4 ret i32 %1 } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define i16 @loadi16com() { ; CHECK-LABEL: loadi16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i16, i16* @vi16, align 4 ret i16 %1 } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define i8 @loadi8com() { ; CHECK-LABEL: loadi8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i8, i8* @vi8, align 4 ret i8 %1 } diff --git a/llvm/test/CodeGen/VE/Scalar/load-align8.ll b/llvm/test/CodeGen/VE/Scalar/load-align8.ll --- a/llvm/test/CodeGen/VE/Scalar/load-align8.ll +++ b/llvm/test/CodeGen/VE/Scalar/load-align8.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define double @loadf64com() { ; CHECK-LABEL: loadf64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load double, double* @vf64, align 8 ret double %1 } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define float @loadf32com() { ; CHECK-LABEL: loadf32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: ldu %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load float, float* @vf32, align 8 ret float %1 } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi64com() { ; CHECK-LABEL: loadi64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i64, i64* @vi64, align 8 ret i64 %1 } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define i32 @loadi32com() { ; CHECK-LABEL: loadi32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i32, i32* @vi32, align 8 ret i32 %1 } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define i16 @loadi16com() { ; CHECK-LABEL: loadi16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i16, i16* @vi16, align 8 ret i16 %1 } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define i8 @loadi8com() { ; CHECK-LABEL: loadi8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i8, i8* @vi8, align 8 ret i8 %1 } diff --git a/llvm/test/CodeGen/VE/Scalar/load.ll b/llvm/test/CodeGen/VE/Scalar/load.ll --- a/llvm/test/CodeGen/VE/Scalar/load.ll +++ b/llvm/test/CodeGen/VE/Scalar/load.ll @@ -3,12 +3,12 @@ ; Function Attrs: norecurse nounwind readonly define fp128 @loadf128(fp128* nocapture readonly %0) { ; CHECK-LABEL: loadf128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s2, 8(, %s0) ; CHECK-NEXT: ld %s3, (, %s0) ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load fp128, fp128* %0, align 16 ret fp128 %2 } @@ -16,9 +16,9 @@ ; Function Attrs: norecurse nounwind readonly define double @loadf64(double* nocapture readonly %0) { ; CHECK-LABEL: loadf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load double, double* %0, align 16 ret double %2 } @@ -26,9 +26,9 @@ ; Function Attrs: norecurse nounwind readonly define float @loadf32(float* nocapture readonly %0) { ; CHECK-LABEL: loadf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldu %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load float, float* %0, align 16 ret float %2 } @@ -36,11 +36,11 @@ ; Function Attrs: norecurse nounwind readonly define i128 @loadi128(i128* nocapture readonly %0) { ; CHECK-LABEL: loadi128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s2, (, %s0) ; CHECK-NEXT: ld %s1, 8(, %s0) ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i128, i128* %0, align 16 ret i128 %2 } @@ -48,9 +48,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi64(i64* nocapture readonly %0) { ; CHECK-LABEL: loadi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i64, i64* %0, align 16 ret i64 %2 } @@ -58,9 +58,9 @@ ; Function Attrs: norecurse nounwind readonly define i32 @loadi32(i32* nocapture readonly %0) { ; CHECK-LABEL: loadi32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i32, i32* %0, align 16 ret i32 %2 } @@ -68,9 +68,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi32sext(i32* nocapture readonly %0) { ; CHECK-LABEL: loadi32sext: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i32, i32* %0, align 16 %3 = sext i32 %2 to i64 ret i64 %3 @@ -79,9 +79,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi32zext(i32* nocapture readonly %0) { ; CHECK-LABEL: loadi32zext: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ldl.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i32, i32* %0, align 16 %3 = zext i32 %2 to i64 ret i64 %3 @@ -90,9 +90,9 @@ ; Function Attrs: norecurse nounwind readonly define i16 @loadi16(i16* nocapture readonly %0) { ; CHECK-LABEL: loadi16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i16, i16* %0, align 16 ret i16 %2 } @@ -100,9 +100,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi16sext(i16* nocapture readonly %0) { ; CHECK-LABEL: loadi16sext: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i16, i16* %0, align 16 %3 = sext i16 %2 to i64 ret i64 %3 @@ -111,9 +111,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi16zext(i16* nocapture readonly %0) { ; CHECK-LABEL: loadi16zext: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i16, i16* %0, align 16 %3 = zext i16 %2 to i64 ret i64 %3 @@ -122,9 +122,9 @@ ; Function Attrs: norecurse nounwind readonly define i8 @loadi8(i8* nocapture readonly %0) { ; CHECK-LABEL: loadi8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i8, i8* %0, align 16 ret i8 %2 } @@ -132,9 +132,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi8sext(i8* nocapture readonly %0) { ; CHECK-LABEL: loadi8sext: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i8, i8* %0, align 16 %3 = sext i8 %2 to i64 ret i64 %3 @@ -143,9 +143,9 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi8zext(i8* nocapture readonly %0) { ; CHECK-LABEL: loadi8zext: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = load i8, i8* %0, align 16 %3 = zext i8 %2 to i64 ret i64 %3 diff --git a/llvm/test/CodeGen/VE/Scalar/load_gv.ll b/llvm/test/CodeGen/VE/Scalar/load_gv.ll --- a/llvm/test/CodeGen/VE/Scalar/load_gv.ll +++ b/llvm/test/CodeGen/VE/Scalar/load_gv.ll @@ -12,13 +12,13 @@ ; Function Attrs: norecurse nounwind readonly define fp128 @loadf128com() { ; CHECK-LABEL: loadf128com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf128@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s0) ; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s1, (, %s2) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load fp128, fp128* @vf128, align 16 ret fp128 %1 } @@ -26,12 +26,12 @@ ; Function Attrs: norecurse nounwind readonly define double @loadf64com() { ; CHECK-LABEL: loadf64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load double, double* @vf64, align 8 ret double %1 } @@ -39,12 +39,12 @@ ; Function Attrs: norecurse nounwind readonly define float @loadf32com() { ; CHECK-LABEL: loadf32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: ldu %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load float, float* @vf32, align 4 ret float %1 } @@ -52,13 +52,13 @@ ; Function Attrs: norecurse nounwind readonly define i128 @loadi128com() { ; CHECK-LABEL: loadi128com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi128@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s1, vi128@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s1) ; CHECK-NEXT: ld %s1, 8(, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i128, i128* @vi128, align 16 ret i128 %1 } @@ -66,12 +66,12 @@ ; Function Attrs: norecurse nounwind readonly define i64 @loadi64com() { ; CHECK-LABEL: loadi64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: ld %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i64, i64* @vi64, align 8 ret i64 %1 } @@ -79,12 +79,12 @@ ; Function Attrs: norecurse nounwind readonly define i32 @loadi32com() { ; CHECK-LABEL: loadi32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i32, i32* @vi32, align 4 ret i32 %1 } @@ -92,12 +92,12 @@ ; Function Attrs: norecurse nounwind readonly define i16 @loadi16com() { ; CHECK-LABEL: loadi16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i16, i16* @vi16, align 2 ret i16 %1 } @@ -105,12 +105,12 @@ ; Function Attrs: norecurse nounwind readonly define i8 @loadi8com() { ; CHECK-LABEL: loadi8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %1 = load i8, i8* @vi8, align 1 ret i8 %1 } diff --git a/llvm/test/CodeGen/VE/Scalar/load_off.ll b/llvm/test/CodeGen/VE/Scalar/load_off.ll --- a/llvm/test/CodeGen/VE/Scalar/load_off.ll +++ b/llvm/test/CodeGen/VE/Scalar/load_off.ll @@ -12,12 +12,12 @@ ; Function Attrs: noinline nounwind optnone define signext i8 @loadi8s() { ; CHECK-LABEL: loadi8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0) ; CHECK-NEXT: ld1b.sx %s0, 2(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1 ret i8 %0 @@ -26,12 +26,12 @@ ; Function Attrs: noinline nounwind optnone define signext i16 @loadi16s() { ; CHECK-LABEL: loadi16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0) ; CHECK-NEXT: ld2b.sx %s0, 4(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2 ret i16 %0 @@ -40,12 +40,12 @@ ; Function Attrs: noinline nounwind optnone define signext i32 @loadi32s() { ; CHECK-LABEL: loadi32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0) ; CHECK-NEXT: ldl.sx %s0, 8(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4 ret i32 %0 @@ -54,12 +54,12 @@ ; Function Attrs: noinline nounwind optnone define i64 @loadi64s() { ; CHECK-LABEL: loadi64s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0) ; CHECK-NEXT: ld %s0, 16(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8 ret i64 %0 @@ -68,13 +68,13 @@ ; Function Attrs: noinline nounwind optnone define i128 @loadi128s() { ; CHECK-LABEL: loadi128s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi128@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0) ; CHECK-NEXT: ld %s0, 32(, %s1) ; CHECK-NEXT: ld %s1, 40(, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16 ret i128 %0 @@ -83,12 +83,12 @@ ; Function Attrs: noinline nounwind optnone define zeroext i8 @loadi8z() { ; CHECK-LABEL: loadi8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi8@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0) ; CHECK-NEXT: ld1b.zx %s0, 2(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1 ret i8 %0 @@ -97,12 +97,12 @@ ; Function Attrs: noinline nounwind optnone define zeroext i16 @loadi16z() { ; CHECK-LABEL: loadi16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi16@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0) ; CHECK-NEXT: ld2b.zx %s0, 4(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2 ret i16 %0 @@ -111,12 +111,12 @@ ; Function Attrs: noinline nounwind optnone define zeroext i32 @loadi32z() { ; CHECK-LABEL: loadi32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0) ; CHECK-NEXT: ldl.zx %s0, 8(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4 ret i32 %0 @@ -125,12 +125,12 @@ ; Function Attrs: noinline nounwind optnone define i64 @loadi64z() { ; CHECK-LABEL: loadi64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0) ; CHECK-NEXT: ld %s0, 16(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8 ret i64 %0 @@ -139,13 +139,13 @@ ; Function Attrs: noinline nounwind optnone define i128 @loadi128z() { ; CHECK-LABEL: loadi128z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, bufi128@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0) ; CHECK-NEXT: ld %s0, 32(, %s1) ; CHECK-NEXT: ld %s1, 40(, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16 ret i128 %0 @@ -154,12 +154,12 @@ ; Function Attrs: noinline nounwind optnone define float @loadf32() { ; CHECK-LABEL: loadf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, buff32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, buff32@hi(, %s0) ; CHECK-NEXT: ldu %s0, 8(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load float, float* getelementptr inbounds ([3 x float], [3 x float]* @buff32, i64 0, i64 2), align 4 ret float %0 @@ -168,12 +168,12 @@ ; Function Attrs: noinline nounwind optnone define double @loadf64() { ; CHECK-LABEL: loadf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, buff64@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, buff64@hi(, %s0) ; CHECK-NEXT: ld %s0, 16(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load double, double* getelementptr inbounds ([3 x double], [3 x double]* @buff64, i64 0, i64 2), align 8 ret double %0 @@ -182,13 +182,13 @@ ; Function Attrs: noinline nounwind optnone define fp128 @loadf128() { ; CHECK-LABEL: loadf128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lea %s0, buff128@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s2, buff128@hi(, %s0) ; CHECK-NEXT: ld %s0, 40(, %s2) ; CHECK-NEXT: ld %s1, 32(, %s2) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) entry: %0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @buff128, i64 0, i64 2), align 16 ret fp128 %0 diff --git a/llvm/test/CodeGen/VE/Scalar/loadrri.ll b/llvm/test/CodeGen/VE/Scalar/loadrri.ll --- a/llvm/test/CodeGen/VE/Scalar/loadrri.ll +++ b/llvm/test/CodeGen/VE/Scalar/loadrri.ll @@ -12,10 +12,10 @@ ; Function Attrs: norecurse nounwind readonly define signext i8 @func_rr(%struct.data* nocapture readonly %0, i32 signext %1) { ; CHECK-LABEL: func_rr: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 2 ; CHECK-NEXT: ld1b.sx %s0, (%s1, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i32 %1 to i64 %4 = getelementptr inbounds %struct.data, %struct.data* %0, i64 %3, i32 0, i64 0 %5 = load i8, i8* %4, align 1 diff --git a/llvm/test/CodeGen/VE/Scalar/max.ll b/llvm/test/CodeGen/VE/Scalar/max.ll --- a/llvm/test/CodeGen/VE/Scalar/max.ll +++ b/llvm/test/CodeGen/VE/Scalar/max.ll @@ -2,9 +2,9 @@ define double @maxf64(double, double) { ; CHECK-LABEL: maxf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmax.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ogt double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -12,9 +12,9 @@ define double @max2f64(double, double) { ; CHECK-LABEL: max2f64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmax.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oge double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -23,11 +23,11 @@ ; VE has no max for unordered comparison define double @maxuf64(double, double) { ; CHECK-LABEL: maxuf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ugt double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -36,11 +36,11 @@ ; VE has no max for unordered comparison define double @max2uf64(double, double) { ; CHECK-LABEL: max2uf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uge double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -48,9 +48,9 @@ define float @maxf32(float, float) { ; CHECK-LABEL: maxf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmax.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ogt float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -58,9 +58,9 @@ define float @max2f32(float, float) { ; CHECK-LABEL: max2f32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmax.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oge float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -68,11 +68,11 @@ define float @maxuf32(float, float) { ; CHECK-LABEL: maxuf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ugt float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -80,11 +80,11 @@ define float @max2uf32(float, float) { ; CHECK-LABEL: max2uf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uge float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -92,9 +92,9 @@ define i64 @maxi64(i64, i64) { ; CHECK-LABEL: maxi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: maxs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sgt i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -102,9 +102,9 @@ define i64 @max2i64(i64, i64) { ; CHECK-LABEL: max2i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: maxs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sge i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -112,11 +112,11 @@ define i64 @maxu64(i64, i64) { ; CHECK-LABEL: maxu64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ugt i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -124,11 +124,11 @@ define i64 @max2u64(i64, i64) { ; CHECK-LABEL: max2u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp uge i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -136,9 +136,9 @@ define i32 @maxi32(i32, i32) { ; CHECK-LABEL: maxi32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sgt i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -146,9 +146,9 @@ define i32 @max2i32(i32, i32) { ; CHECK-LABEL: max2i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sge i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -156,11 +156,11 @@ define i32 @maxu32(i32, i32) { ; CHECK-LABEL: maxu32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ugt i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -168,11 +168,11 @@ define i32 @max2u32(i32, i32) { ; CHECK-LABEL: max2u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp uge i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -180,10 +180,10 @@ define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) { ; CHECK-LABEL: maxi1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = xor i1 %1, true %4 = and i1 %3, %0 %5 = select i1 %4, i1 %0, i1 %1 diff --git a/llvm/test/CodeGen/VE/Scalar/min.ll b/llvm/test/CodeGen/VE/Scalar/min.ll --- a/llvm/test/CodeGen/VE/Scalar/min.ll +++ b/llvm/test/CodeGen/VE/Scalar/min.ll @@ -2,9 +2,9 @@ define double @minf64(double, double) { ; CHECK-LABEL: minf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmin.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp olt double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -12,9 +12,9 @@ define double @min2f64(double, double) { ; CHECK-LABEL: min2f64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmin.d %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ole double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -22,11 +22,11 @@ define double @minuf64(double, double) { ; CHECK-LABEL: minuf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ult double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -34,11 +34,11 @@ define double @min2uf64(double, double) { ; CHECK-LABEL: min2uf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ule double %0, %1 %4 = select i1 %3, double %0, double %1 ret double %4 @@ -46,9 +46,9 @@ define float @minf32(float, float) { ; CHECK-LABEL: minf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmin.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp olt float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -56,9 +56,9 @@ define float @min2f32(float, float) { ; CHECK-LABEL: min2f32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fmin.s %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ole float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -66,11 +66,11 @@ define float @minuf32(float, float) { ; CHECK-LABEL: minuf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ult float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -78,11 +78,11 @@ define float @min2uf32(float, float) { ; CHECK-LABEL: min2uf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ule float %0, %1 %4 = select i1 %3, float %0, float %1 ret float %4 @@ -90,9 +90,9 @@ define i64 @mini64(i64, i64) { ; CHECK-LABEL: mini64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: mins.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp slt i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -100,9 +100,9 @@ define i64 @min2i64(i64, i64) { ; CHECK-LABEL: min2i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: mins.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sle i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -110,11 +110,11 @@ define i64 @minu64(i64, i64) { ; CHECK-LABEL: minu64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ult i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -122,11 +122,11 @@ define i64 @min2u64(i64, i64) { ; CHECK-LABEL: min2u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmov.l.le %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ule i64 %0, %1 %4 = select i1 %3, i64 %0, i64 %1 ret i64 %4 @@ -134,9 +134,9 @@ define i32 @mini32(i32, i32) { ; CHECK-LABEL: mini32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: mins.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp slt i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -144,9 +144,9 @@ define i32 @min2i32(i32, i32) { ; CHECK-LABEL: min2i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: mins.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sle i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -154,11 +154,11 @@ define i32 @minu32(i32, i32) { ; CHECK-LABEL: minu32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ult i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -166,11 +166,11 @@ define i32 @min2u32(i32, i32) { ; CHECK-LABEL: min2u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmov.w.le %s1, %s0, %s2 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ule i32 %0, %1 %4 = select i1 %3, i32 %0, i32 %1 ret i32 %4 @@ -178,11 +178,11 @@ define zeroext i1 @mini1(i1 zeroext, i1 zeroext) { ; CHECK-LABEL: mini1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = xor i1 %0, true %4 = and i1 %3, %1 %5 = select i1 %4, i1 %0, i1 %1 diff --git a/llvm/test/CodeGen/VE/Scalar/multiply.ll b/llvm/test/CodeGen/VE/Scalar/multiply.ll --- a/llvm/test/CodeGen/VE/Scalar/multiply.ll +++ b/llvm/test/CodeGen/VE/Scalar/multiply.ll @@ -2,41 +2,41 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i8 %b, %a ret i8 %r } define signext i16 @func16s(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i16 %b, %a ret i16 %r } define signext i32 @func32s(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul nsw i32 %b, %a ret i32 %r } define i64 @func64(i64 %a, i64 %b) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.l %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul nsw i64 %b, %a ret i64 %r } @@ -61,39 +61,39 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i8 %b, %a ret i8 %r } define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i16 %b, %a ret i16 %r } define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i32 %b, %a ret i32 %r } define i64 @func64z(i64 %a, i64 %b) { ; CHECK-LABEL: func64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.l %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i64 %b, %a ret i64 %r } @@ -118,41 +118,41 @@ define signext i8 @funci8s(i8 signext %a) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i8 %a, 5 ret i8 %r } define signext i16 @funci16s(i16 signext %a) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i16 %a, 5 ret i16 %r } define signext i32 @funci32s(i32 signext %a) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul nsw i32 %a, 5 ret i32 %r } define i64 @funci64(i64 %a) { ; CHECK-LABEL: funci64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.l %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul nsw i64 %a, 5 ret i64 %r } @@ -173,39 +173,39 @@ define zeroext i8 @funci8z(i8 zeroext %a) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i8 %a, 5 ret i8 %r } define zeroext i16 @funci16z(i16 zeroext %a) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i16 %a, 5 ret i16 %r } define zeroext i32 @funci32z(i32 zeroext %a) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i32 %a, 5 ret i32 %r } define i64 @funci64z(i64 %a) { ; CHECK-LABEL: funci64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: muls.l %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = mul i64 %a, 5 ret i64 %r } @@ -226,31 +226,31 @@ define zeroext i32 @funci32z_2(i32 zeroext %a) { ; CHECK-LABEL: funci32z_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 31 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = shl i32 %a, 31 ret i32 %r } define i64 @funci64_2(i64 %a) { ; CHECK-LABEL: funci64_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 31 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = shl nsw i64 %a, 31 ret i64 %r } define i128 @funci128_2(i128 %a) { ; CHECK-LABEL: funci128_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s2, %s0, 33 ; CHECK-NEXT: sll %s1, %s1, 31 ; CHECK-NEXT: or %s1, %s1, %s2 ; CHECK-NEXT: sll %s0, %s0, 31 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = shl nsw i128 %a, 31 ret i128 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/nnd.ll b/llvm/test/CodeGen/VE/Scalar/nnd.ll --- a/llvm/test/CodeGen/VE/Scalar/nnd.ll +++ b/llvm/test/CodeGen/VE/Scalar/nnd.ll @@ -2,9 +2,9 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i8 %a, -1 %res = and i8 %not, %b ret i8 %res @@ -12,9 +12,9 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i8 %a, -1 %res = and i8 %b, %not ret i8 %res @@ -22,10 +22,10 @@ define signext i8 @funci8s(i8 signext %a) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 5, (0)1 ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i8 %a, -1 %res = and i8 %not, 5 ret i8 %res @@ -33,10 +33,10 @@ define zeroext i8 @funci8z(i8 zeroext %a) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i8 %a, -1 %res = and i8 -5, %not ret i8 %res @@ -44,9 +44,9 @@ define signext i16 @func16s(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i16 %a, -1 %res = and i16 %not, %b ret i16 %res @@ -54,9 +54,9 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i16 %a, -1 %res = and i16 %b, %not ret i16 %res @@ -64,9 +64,9 @@ define signext i16 @funci16s(i16 signext %a) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, -1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i16 %a, -1 %res = and i16 %not, 65535 ret i16 %res @@ -74,9 +74,9 @@ define zeroext i16 @funci16z(i16 zeroext %a) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, (52)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i16 %a, -1 %res = and i16 4095, %not ret i16 %res @@ -84,9 +84,9 @@ define signext i32 @func32s(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i32 %a, -1 %res = and i32 %not, %b ret i32 %res @@ -94,9 +94,9 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i32 %a, -1 %res = and i32 %not, %b ret i32 %res @@ -104,9 +104,9 @@ define signext i32 @funci32s(i32 signext %a) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i32 %a, -1 %res = and i32 %not, 268435455 ret i32 %res @@ -114,9 +114,9 @@ define zeroext i32 @funci32z(i32 zeroext %a) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i32 %a, -1 %res = and i32 %not, 268435455 ret i32 %res @@ -124,9 +124,9 @@ define i64 @func64(i64 %a, i64 %b) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i64 %a, -1 %res = and i64 %not, %b ret i64 %res @@ -134,9 +134,9 @@ define i64 @func64_2(i64 %a, i64 %b) { ; CHECK-LABEL: func64_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i64 %b, -1 %res = and i64 %not, %a ret i64 %res @@ -144,9 +144,9 @@ define i64 @func64i(i64 %a) { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, (24)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i64 %a, -1 %res = and i64 %not, 1099511627775 ret i64 %res @@ -154,10 +154,10 @@ define i128 @func128(i128 %a, i128 %b) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s2 ; CHECK-NEXT: nnd %s1, %s1, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i128 %a, -1 %res = and i128 %b, %not ret i128 %res @@ -165,11 +165,11 @@ define i128 @funci128(i128 %a) { ; CHECK-LABEL: funci128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 5, (0)1 ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %not = xor i128 %a, -1 %res = and i128 %not, 5 ret i128 %res @@ -177,11 +177,11 @@ define i64 @func64_nnd_fold(i64 %x, i64 %y, i64 %m) { ; CHECK-LABEL: func64_nnd_fold: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s1, %s2, %s1 ; CHECK-NEXT: and %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %D = xor i64 %x, %y %A = and i64 %D, %m %res = xor i64 %A, %y @@ -190,11 +190,11 @@ define i64 @func64iy_nnd_fold(i64 %x, i64 %m) { ; CHECK-LABEL: func64iy_nnd_fold: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: or %s1, -64, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %D = xor i64 %x, -64 %A = and i64 %D, %m %res = xor i64 %A, -64 @@ -203,11 +203,11 @@ define i64 @func64im_nnd_fold(i64 %x, i64 %y) { ; CHECK-LABEL: func64im_nnd_fold: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: and %s0, 30, %s0 ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %D = xor i64 %x, %y %A = and i64 %D, 30 %res = xor i64 %A, %y diff --git a/llvm/test/CodeGen/VE/Scalar/or.ll b/llvm/test/CodeGen/VE/Scalar/or.ll --- a/llvm/test/CodeGen/VE/Scalar/or.ll +++ b/llvm/test/CodeGen/VE/Scalar/or.ll @@ -2,146 +2,146 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i8 %a, %b ret i8 %res } define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i8 %b, %a ret i8 %res } define signext i8 @funci8s(i8 signext %a) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i8 %a, 5 ret i8 %res } define zeroext i8 @funci8z(i8 zeroext %a) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i8 -5, %a ret i8 %res } define signext i16 @func16s(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i16 %a, %b ret i16 %res } define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i16 %b, %a ret i16 %res } define signext i16 @funci16s(i16 signext %a) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, -1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i16 %a, 65535 ret i16 %res } define zeroext i16 @funci16z(i16 zeroext %a) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, (52)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i16 4095, %a ret i16 %res } define signext i32 @func32s(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i32 %a, %b ret i32 %res } define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i32 %a, %b ret i32 %res } define signext i32 @funci32s(i32 signext %a) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i32 %a, 268435455 ret i32 %res } define zeroext i32 @funci32z(i32 zeroext %a) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i32 %a, 268435455 ret i32 %res } define i64 @func64(i64 %a, i64 %b) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i64 %a, %b ret i64 %res } define i64 @func64i(i64 %a) { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, (24)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i64 %a, 1099511627775 ret i64 %res } define i128 @func128(i128 %a, i128 %b) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s2, %s0 ; CHECK-NEXT: or %s1, %s3, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i128 %b, %a ret i128 %res } define i128 @funci128(i128 %a) { ; CHECK-LABEL: funci128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = or i128 %a, 5 ret i128 %res } diff --git a/llvm/test/CodeGen/VE/Scalar/rem.ll b/llvm/test/CodeGen/VE/Scalar/rem.ll --- a/llvm/test/CodeGen/VE/Scalar/rem.ll +++ b/llvm/test/CodeGen/VE/Scalar/rem.ll @@ -16,11 +16,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @remi64(i64 %a, i64 %b) { ; CHECK-LABEL: remi64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.l %s2, %s0, %s1 ; CHECK-NEXT: muls.l %s1, %s2, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = srem i64 %a, %b ret i64 %r } @@ -28,12 +28,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @remi32(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: remi32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = srem i32 %a, %b ret i32 %r } @@ -54,11 +54,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @remu64(i64 %a, i64 %b) { ; CHECK-LABEL: remu64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.l %s2, %s0, %s1 ; CHECK-NEXT: muls.l %s1, %s2, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i64 %a, %b ret i64 %r } @@ -66,12 +66,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: remu32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i32 %a, %b ret i32 %r } @@ -79,13 +79,13 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @remi16(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: remi16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a32 = sext i16 %a to i32 %b32 = sext i16 %b to i32 %r32 = srem i32 %a32, %b32 @@ -96,12 +96,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: remu16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i16 %a, %b ret i16 %r } @@ -109,13 +109,13 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @remi8(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: remi8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a32 = sext i8 %a to i32 %b32 = sext i8 %b to i32 %r32 = srem i32 %a32, %b32 @@ -126,12 +126,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: remu8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i8 %a, %b ret i8 %r } @@ -154,11 +154,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @remi64ri(i64 %a) { ; CHECK-LABEL: remi64ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.l %s1, %s0, (62)0 ; CHECK-NEXT: muls.l %s1, 3, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = srem i64 %a, 3 ret i64 %r } @@ -166,12 +166,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @remi32ri(i32 signext %a) { ; CHECK-LABEL: remi32ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = srem i32 %a, 3 ret i32 %r } @@ -194,11 +194,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @remu64ri(i64 %a) { ; CHECK-LABEL: remu64ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.l %s1, %s0, (62)0 ; CHECK-NEXT: muls.l %s1, 3, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i64 %a, 3 ret i64 %r } @@ -206,12 +206,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @remu32ri(i32 zeroext %a) { ; CHECK-LABEL: remu32ri: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s1, %s0, (62)0 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i32 %a, 3 ret i32 %r } @@ -236,11 +236,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @remi64li(i64 %a, i64 %b) { ; CHECK-LABEL: remi64li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.l %s0, 3, %s1 ; CHECK-NEXT: muls.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, 3, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = srem i64 3, %b ret i64 %r } @@ -248,12 +248,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @remi32li(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: remi32li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divs.w.sx %s0, 3, %s1 ; CHECK-NEXT: muls.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = srem i32 3, %b ret i32 %r } @@ -278,11 +278,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @remu64li(i64 %a, i64 %b) { ; CHECK-LABEL: remu64li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.l %s0, 3, %s1 ; CHECK-NEXT: muls.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, 3, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i64 3, %b ret i64 %r } @@ -290,12 +290,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: remu32li: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: divu.w %s0, 3, %s1 ; CHECK-NEXT: muls.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %r = urem i32 3, %b ret i32 %r } diff --git a/llvm/test/CodeGen/VE/Scalar/right_shift.ll b/llvm/test/CodeGen/VE/Scalar/right_shift.ll --- a/llvm/test/CodeGen/VE/Scalar/right_shift.ll +++ b/llvm/test/CodeGen/VE/Scalar/right_shift.ll @@ -2,10 +2,10 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i8 %0 to i32 %4 = sext i8 %1 to i32 %5 = ashr i32 %3, %4 @@ -15,10 +15,10 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i16 %0 to i32 %4 = sext i16 %1 to i32 %5 = ashr i32 %3, %4 @@ -28,29 +28,29 @@ define i32 @func3(i32 %0, i32 %1) { ; CHECK-LABEL: func3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = ashr i32 %0, %1 ret i32 %3 } define i64 @func4(i64 %0, i64 %1) { ; CHECK-LABEL: func4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = ashr i64 %0, %1 ret i64 %3 } define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: func7: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i8 %0 to i32 %4 = zext i8 %1 to i32 %5 = lshr i32 %3, %4 @@ -60,11 +60,11 @@ define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i16 %0 to i32 %4 = zext i16 %1 to i32 %5 = lshr i32 %3, %4 @@ -74,98 +74,98 @@ define i32 @func9(i32 %0, i32 %1) { ; CHECK-LABEL: func9: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = lshr i32 %0, %1 ret i32 %3 } define i64 @func10(i64 %0, i64 %1) { ; CHECK-LABEL: func10: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = lshr i64 %0, %1 ret i64 %3 } define signext i8 @func12(i8 signext %0) { ; CHECK-LABEL: func12: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, 5 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i8 %0, 5 ret i8 %2 } define signext i16 @func13(i16 signext %0) { ; CHECK-LABEL: func13: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, 5 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i16 %0, 5 ret i16 %2 } define i32 @func14(i32 %0) { ; CHECK-LABEL: func14: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i32 %0, 5 ret i32 %2 } define i64 @func15(i64 %0) { ; CHECK-LABEL: func15: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i64 %0, 5 ret i64 %2 } define zeroext i8 @func17(i8 zeroext %0) { ; CHECK-LABEL: func17: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 5 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i8 %0, 5 ret i8 %2 } define zeroext i16 @func18(i16 zeroext %0) { ; CHECK-LABEL: func18: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 5 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i16 %0, 5 ret i16 %2 } define i32 @func19(i32 %0) { ; CHECK-LABEL: func19: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i32 %0, 5 ret i32 %2 } define i64 @func20(i64 %0) { ; CHECK-LABEL: func20: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s0, %s0, 5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i64 %0, 5 ret i64 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/rotl.ll b/llvm/test/CodeGen/VE/Scalar/rotl.ll --- a/llvm/test/CodeGen/VE/Scalar/rotl.ll +++ b/llvm/test/CodeGen/VE/Scalar/rotl.ll @@ -2,13 +2,13 @@ define i64 @func1(i64 %a, i32 %b) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s2, %s0, %s1 ; CHECK-NEXT: lea %s3, 64 ; CHECK-NEXT: subs.w.sx %s1, %s3, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %b64 = zext i32 %b to i64 %a.sl = shl i64 %a, %b64 %b.inv = sub nsw i32 64, %b @@ -20,13 +20,13 @@ define i32 @func2(i32 %a, i32 %b) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s2, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s1, 32, %s1 ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a.sl = shl i32 %a, %b %b.inv = sub nsw i32 32, %b %a.sr = lshr i32 %a, %b.inv diff --git a/llvm/test/CodeGen/VE/Scalar/rotr.ll b/llvm/test/CodeGen/VE/Scalar/rotr.ll --- a/llvm/test/CodeGen/VE/Scalar/rotr.ll +++ b/llvm/test/CodeGen/VE/Scalar/rotr.ll @@ -2,13 +2,13 @@ define i64 @func1(i64 %a, i32 %b) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s2, %s0, %s1 ; CHECK-NEXT: lea %s3, 64 ; CHECK-NEXT: subs.w.sx %s1, %s3, %s1 ; CHECK-NEXT: sll %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %b64 = zext i32 %b to i64 %a.lr = lshr i64 %a, %b64 %b.inv = sub nsw i32 64, %b @@ -20,13 +20,13 @@ define i32 @func2(i32 %a, i32 %b) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s2, %s0, (32)0 ; CHECK-NEXT: srl %s2, %s2, %s1 ; CHECK-NEXT: subs.w.sx %s1, 32, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %a.lr = lshr i32 %a, %b %b.inv = sub nsw i32 32, %b %a.sl = shl i32 %a, %b.inv diff --git a/llvm/test/CodeGen/VE/Scalar/select.ll b/llvm/test/CodeGen/VE/Scalar/select.ll --- a/llvm/test/CodeGen/VE/Scalar/select.ll +++ b/llvm/test/CodeGen/VE/Scalar/select.ll @@ -41,10 +41,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) { ; CHECK-LABEL: select_i1_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i1 %1, i1 %2 ret i1 %4 } @@ -52,10 +52,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) { ; CHECK-LABEL: select_i8_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i8 %1, i8 %2 ret i8 %4 } @@ -63,10 +63,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) { ; CHECK-LABEL: select_u8_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i8 %1, i8 %2 ret i8 %4 } @@ -74,10 +74,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2) { ; CHECK-LABEL: select_i16_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i16 %1, i16 %2 ret i16 %4 } @@ -85,10 +85,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2) { ; CHECK-LABEL: select_u16_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i16 %1, i16 %2 ret i16 %4 } @@ -96,10 +96,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2) { ; CHECK-LABEL: select_i32_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i32 %1, i32 %2 ret i32 %4 } @@ -107,10 +107,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2) { ; CHECK-LABEL: select_u32_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i32 %1, i32 %2 ret i32 %4 } @@ -118,11 +118,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) { ; CHECK-LABEL: select_i64_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i64 %1, i64 %2 ret i64 %4 } @@ -130,11 +130,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) { ; CHECK-LABEL: select_u64_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i64 %1, i64 %2 ret i64 %4 } @@ -142,13 +142,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) { ; CHECK-LABEL: select_i128_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i128 %1, i128 %2 ret i128 %4 } @@ -156,13 +156,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) { ; CHECK-LABEL: select_u128_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select i1 %0, i128 %1, i128 %2 ret i128 %4 } @@ -170,11 +170,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_float_var(i1 zeroext %0, float %1, float %2) { ; CHECK-LABEL: select_float_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select fast i1 %0, float %1, float %2 ret float %4 } @@ -182,11 +182,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_double_var(i1 zeroext %0, double %1, double %2) { ; CHECK-LABEL: select_double_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select fast i1 %0, double %1, double %2 ret double %4 } @@ -194,13 +194,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) { ; CHECK-LABEL: select_quad_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = select fast i1 %0, fp128 %1, fp128 %2 ret fp128 %4 } @@ -208,9 +208,9 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) { ; CHECK-LABEL: select_i1_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = or i1 %0, %1 ret i1 %3 } @@ -218,10 +218,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) { ; CHECK-LABEL: select_i8_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s1, (57)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i8 -128, i8 %1 ret i8 %3 } @@ -229,10 +229,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: select_u8_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s1, (57)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i8 127, i8 %1 ret i8 %3 } @@ -240,10 +240,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) { ; CHECK-LABEL: select_i16_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s1, (49)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i16 -32768, i16 %1 ret i16 %3 } @@ -251,10 +251,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: select_u16_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s1, (49)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i16 32767, i16 %1 ret i16 %3 } @@ -262,10 +262,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) { ; CHECK-LABEL: select_i32_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i32 65535, i32 %1 ret i32 %3 } @@ -273,10 +273,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: select_u32_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i32 65535, i32 %1 ret i32 %3 } @@ -284,11 +284,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) { ; CHECK-LABEL: select_i64_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i64 65535, i64 %1 ret i64 %3 } @@ -296,11 +296,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) { ; CHECK-LABEL: select_u64_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i64 65535, i64 %1 ret i64 %3 } @@ -308,13 +308,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) { ; CHECK-LABEL: select_i128_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s1, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i128 65535, i128 %1 ret i128 %3 } @@ -322,13 +322,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) { ; CHECK-LABEL: select_u128_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s1, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i128 65535, i128 %1 ret i128 %3 } @@ -336,11 +336,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_float_mimm(i1 zeroext %0, float %1) { ; CHECK-LABEL: select_float_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, float -2.000000e+00, float %1 ret float %3 } @@ -348,11 +348,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_double_mimm(i1 zeroext %0, double %1) { ; CHECK-LABEL: select_double_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select fast i1 %0, double -2.000000e+00, double %1 ret double %3 } @@ -360,7 +360,7 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) { ; CHECK-LABEL: select_quad_mimm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1) @@ -371,7 +371,7 @@ ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select fast i1 %0, fp128 0xL0000000000000000C000000000000000, fp128 %1 ret fp128 %3 } @@ -379,10 +379,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) { ; CHECK-LABEL: select_mimm_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, 1, %s0 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = xor i1 %0, true %4 = or i1 %3, %1 ret i1 %4 @@ -391,10 +391,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) { ; CHECK-LABEL: select_mimm_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.eq %s1, (57)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i8 %1, i8 -128 ret i8 %3 } @@ -402,10 +402,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: select_mimm_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.eq %s1, (57)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i8 %1, i8 127 ret i8 %3 } @@ -413,10 +413,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) { ; CHECK-LABEL: select_mimm_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.eq %s1, (49)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i16 %1, i16 -32768 ret i16 %3 } @@ -424,10 +424,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: select_mimm_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.eq %s1, (49)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i16 %1, i16 32767 ret i16 %3 } @@ -435,10 +435,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) { ; CHECK-LABEL: select_mimm_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i32 %1, i32 65535 ret i32 %3 } @@ -446,10 +446,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: select_mimm_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i32 %1, i32 65535 ret i32 %3 } @@ -457,11 +457,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) { ; CHECK-LABEL: select_mimm_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i64 %1, i64 65535 ret i64 %3 } @@ -469,11 +469,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) { ; CHECK-LABEL: select_mimm_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i64 %1, i64 65535 ret i64 %3 } @@ -481,13 +481,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) { ; CHECK-LABEL: select_mimm_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s1, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i128 %1, i128 65535 ret i128 %3 } @@ -495,13 +495,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) { ; CHECK-LABEL: select_mimm_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s1, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, i128 %1, i128 65535 ret i128 %3 } @@ -509,11 +509,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_mimm_float(i1 zeroext %0, float %1) { ; CHECK-LABEL: select_mimm_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select i1 %0, float %1, float -2.000000e+00 ret float %3 } @@ -521,11 +521,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_mimm_double(i1 zeroext %0, double %1) { ; CHECK-LABEL: select_mimm_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0 ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select fast i1 %0, double %1, double -2.000000e+00 ret double %3 } @@ -533,7 +533,7 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) { ; CHECK-LABEL: select_mimm_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1) @@ -544,7 +544,7 @@ ; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = select fast i1 %0, fp128 %1, fp128 0xL0000000000000000C000000000000000 ret fp128 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/select_cc.ll b/llvm/test/CodeGen/VE/Scalar/select_cc.ll --- a/llvm/test/CodeGen/VE/Scalar/select_cc.ll +++ b/llvm/test/CodeGen/VE/Scalar/select_cc.ll @@ -8,11 +8,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_i1_i1(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i1_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i1 %3, i1 %2 ret i1 %6 @@ -21,11 +21,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_i8_i1(i8 signext %0, i8 signext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i8_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -34,11 +34,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_u8_i1(i8 zeroext %0, i8 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u8_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -47,11 +47,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_i16_i1(i16 signext %0, i16 signext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i16_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -60,11 +60,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_u16_i1(i16 zeroext %0, i16 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u16_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -73,11 +73,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_i32_i1(i32 signext %0, i32 signext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i32_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -86,11 +86,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_u32_i1(i32 zeroext %0, i32 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u32_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -99,11 +99,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_i64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i64_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -112,11 +112,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_u64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u64_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -125,14 +125,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_i128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i128_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -141,14 +141,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_u128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u128_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -157,11 +157,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_float_i1(float %0, float %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_float_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -170,11 +170,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_double_i1(double %0, double %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_double_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -183,11 +183,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @select_cc_quad_i1(fp128 %0, fp128 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_quad_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i1 %2, i1 %3 ret i1 %6 @@ -196,11 +196,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_i1_i8(i1 zeroext %0, i1 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i1_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i8 %3, i8 %2 ret i8 %6 @@ -209,11 +209,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_i8_i8(i8 signext %0, i8 signext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i8_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -222,11 +222,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_u8_i8(i8 zeroext %0, i8 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u8_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -235,11 +235,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_i16_i8(i16 signext %0, i16 signext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i16_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -248,11 +248,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_u16_i8(i16 zeroext %0, i16 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u16_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -261,11 +261,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_i32_i8(i32 signext %0, i32 signext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i32_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -274,11 +274,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_u32_i8(i32 zeroext %0, i32 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u32_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -287,11 +287,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_i64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i64_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -300,11 +300,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_u64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u64_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -313,14 +313,14 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_i128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i128_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -329,14 +329,14 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_u128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u128_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -345,11 +345,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_float_i8(float %0, float %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_float_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -358,11 +358,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_double_i8(double %0, double %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_double_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -371,11 +371,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @select_cc_quad_i8(fp128 %0, fp128 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_quad_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -384,11 +384,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_i1_u8(i1 zeroext %0, i1 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i1_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i8 %3, i8 %2 ret i8 %6 @@ -397,11 +397,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_i8_u8(i8 signext %0, i8 signext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i8_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -410,11 +410,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_u8_u8(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u8_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -423,11 +423,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_i16_u8(i16 signext %0, i16 signext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i16_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -436,11 +436,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_u16_u8(i16 zeroext %0, i16 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u16_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -449,11 +449,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_i32_u8(i32 signext %0, i32 signext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i32_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -462,11 +462,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_u32_u8(i32 zeroext %0, i32 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u32_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -475,11 +475,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_i64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i64_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -488,11 +488,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_u64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u64_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -501,14 +501,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_i128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i128_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -517,14 +517,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_u128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u128_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -533,11 +533,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_float_u8(float %0, float %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_float_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -546,11 +546,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_double_u8(double %0, double %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_double_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -559,11 +559,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @select_cc_quad_u8(fp128 %0, fp128 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_quad_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i8 %2, i8 %3 ret i8 %6 @@ -572,11 +572,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_i1_i16(i1 zeroext %0, i1 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i1_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i16 %3, i16 %2 ret i16 %6 @@ -585,11 +585,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_i8_i16(i8 signext %0, i8 signext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i8_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -598,11 +598,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_u8_i16(i8 zeroext %0, i8 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u8_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -611,11 +611,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_i16_i16(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i16_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -624,11 +624,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_u16_i16(i16 zeroext %0, i16 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u16_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -637,11 +637,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_i32_i16(i32 signext %0, i32 signext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i32_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -650,11 +650,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_u32_i16(i32 zeroext %0, i32 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u32_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -663,11 +663,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_i64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i64_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -676,11 +676,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_u64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u64_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -689,14 +689,14 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_i128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i128_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -705,14 +705,14 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_u128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u128_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -721,11 +721,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_float_i16(float %0, float %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_float_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -734,11 +734,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_double_i16(double %0, double %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_double_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -747,11 +747,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @select_cc_quad_i16(fp128 %0, fp128 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_quad_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -760,11 +760,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_i1_u16(i1 zeroext %0, i1 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i1_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i16 %3, i16 %2 ret i16 %6 @@ -773,11 +773,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_i8_u16(i8 signext %0, i8 signext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i8_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -786,11 +786,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_u8_u16(i8 zeroext %0, i8 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u8_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -799,11 +799,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_i16_u16(i16 signext %0, i16 signext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i16_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -812,11 +812,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_u16_u16(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u16_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -825,11 +825,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_i32_u16(i32 signext %0, i32 signext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i32_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -838,11 +838,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_u32_u16(i32 zeroext %0, i32 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u32_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -851,11 +851,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_i64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i64_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -864,11 +864,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_u64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u64_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -877,14 +877,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_i128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i128_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -893,14 +893,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_u128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u128_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -909,11 +909,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_float_u16(float %0, float %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_float_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -922,11 +922,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_double_u16(double %0, double %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_double_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -935,11 +935,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @select_cc_quad_u16(fp128 %0, fp128 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_quad_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i16 %2, i16 %3 ret i16 %6 @@ -948,11 +948,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_i1_i32(i1 zeroext %0, i1 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i1_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i32 %3, i32 %2 ret i32 %6 @@ -961,11 +961,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_i8_i32(i8 signext %0, i8 signext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i8_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -974,11 +974,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_u8_i32(i8 zeroext %0, i8 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u8_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -987,11 +987,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_i16_i32(i16 signext %0, i16 signext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i16_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1000,11 +1000,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_u16_i32(i16 zeroext %0, i16 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u16_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1013,11 +1013,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_i32_i32(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i32_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1026,11 +1026,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_u32_i32(i32 zeroext %0, i32 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u32_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1039,11 +1039,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_i64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i64_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1052,11 +1052,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_u64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u64_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1065,14 +1065,14 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_i128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i128_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1081,14 +1081,14 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_u128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u128_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1097,11 +1097,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_float_i32(float %0, float %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_float_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1110,11 +1110,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_double_i32(double %0, double %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_double_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1123,11 +1123,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @select_cc_quad_i32(fp128 %0, fp128 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_quad_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1136,11 +1136,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_i1_u32(i1 zeroext %0, i1 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i1_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i32 %3, i32 %2 ret i32 %6 @@ -1149,11 +1149,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_i8_u32(i8 signext %0, i8 signext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i8_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1162,11 +1162,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_u8_u32(i8 zeroext %0, i8 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u8_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1175,11 +1175,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_i16_u32(i16 signext %0, i16 signext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i16_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1188,11 +1188,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_u16_u32(i16 zeroext %0, i16 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u16_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1201,11 +1201,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_i32_u32(i32 signext %0, i32 signext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i32_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1214,11 +1214,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_u32_u32(i32 zeroext %0, i32 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u32_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1227,11 +1227,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_i64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i64_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1240,11 +1240,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_u64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u64_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1253,14 +1253,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_i128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i128_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1269,14 +1269,14 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_u128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u128_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1285,11 +1285,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_float_u32(float %0, float %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_float_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1298,11 +1298,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_double_u32(double %0, double %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_double_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1311,11 +1311,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @select_cc_quad_u32(fp128 %0, fp128 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_quad_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -1324,12 +1324,12 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i1_i64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i1_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i64 %3, i64 %2 ret i64 %6 @@ -1338,11 +1338,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i8_i64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i8_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1351,11 +1351,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u8_i64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u8_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1364,11 +1364,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i16_i64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i16_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1377,11 +1377,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u16_i64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u16_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1390,11 +1390,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i32_i64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i32_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1403,11 +1403,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u32_i64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u32_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1416,11 +1416,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i64_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1429,11 +1429,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u64_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1442,14 +1442,14 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i128_i64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i128_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1458,14 +1458,14 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u128_i64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u128_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1474,11 +1474,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_float_i64(float %0, float %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_float_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1487,11 +1487,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_double_i64(double %0, double %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_double_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1500,11 +1500,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_quad_i64(fp128 %0, fp128 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_quad_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1513,12 +1513,12 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i1_u64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i1_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i64 %3, i64 %2 ret i64 %6 @@ -1527,11 +1527,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i8_u64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i8_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1540,11 +1540,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u8_u64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u8_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1553,11 +1553,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i16_u64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i16_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1566,11 +1566,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u16_u64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u16_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1579,11 +1579,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i32_u64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i32_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1592,11 +1592,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u32_u64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u32_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1605,11 +1605,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i64_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1618,11 +1618,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u64_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1631,14 +1631,14 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_i128_u64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i128_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1647,14 +1647,14 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_u128_u64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u128_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1663,11 +1663,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_float_u64(float %0, float %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_float_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1676,11 +1676,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_double_u64(double %0, double %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_double_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1689,11 +1689,11 @@ ; Function Attrs: norecurse nounwind readnone define i64 @select_cc_quad_u64(fp128 %0, fp128 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_quad_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -1702,14 +1702,14 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i1_i128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i1_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i128 %3, i128 %2 ret i128 %6 @@ -1718,13 +1718,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i8_i128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i8_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1733,13 +1733,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u8_i128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u8_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1748,13 +1748,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i16_i128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i16_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1763,13 +1763,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u16_i128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u16_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1778,13 +1778,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i32_i128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i32_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1793,13 +1793,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u32_i128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u32_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1808,13 +1808,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i64_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1823,13 +1823,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u64_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1838,7 +1838,7 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i128_i128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i128_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -1847,7 +1847,7 @@ ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1856,7 +1856,7 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u128_i128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u128_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -1865,7 +1865,7 @@ ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1874,13 +1874,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_float_i128(float %0, float %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_float_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1889,13 +1889,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_double_i128(double %0, double %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_double_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1904,13 +1904,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_quad_i128(fp128 %0, fp128 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_quad_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1919,14 +1919,14 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i1_u128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i1_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select i1 %5, i128 %3, i128 %2 ret i128 %6 @@ -1935,13 +1935,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i8_u128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i8_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1950,13 +1950,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u8_u128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u8_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1965,13 +1965,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i16_u128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i16_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1980,13 +1980,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u16_u128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u16_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -1995,13 +1995,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i32_u128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i32_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2010,13 +2010,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u32_u128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u32_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2025,13 +2025,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i64_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2040,13 +2040,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u64_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2055,7 +2055,7 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_i128_u128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i128_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -2064,7 +2064,7 @@ ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2073,7 +2073,7 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_u128_u128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u128_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -2082,7 +2082,7 @@ ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2091,13 +2091,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_float_u128(float %0, float %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_float_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2106,13 +2106,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_double_u128(double %0, double %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_double_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2121,13 +2121,13 @@ ; Function Attrs: norecurse nounwind readnone define i128 @select_cc_quad_u128(fp128 %0, fp128 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_quad_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select i1 %5, i128 %2, i128 %3 ret i128 %6 @@ -2136,12 +2136,12 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_i1_float(i1 zeroext %0, i1 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i1_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select fast i1 %5, float %3, float %2 ret float %6 @@ -2150,11 +2150,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_i8_float(i8 signext %0, i8 signext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i8_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2163,11 +2163,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_u8_float(i8 zeroext %0, i8 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u8_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2176,11 +2176,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_i16_float(i16 signext %0, i16 signext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i16_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2189,11 +2189,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_u16_float(i16 zeroext %0, i16 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u16_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2202,11 +2202,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_i32_float(i32 signext %0, i32 signext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i32_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2215,11 +2215,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_u32_float(i32 zeroext %0, i32 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u32_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2228,11 +2228,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_i64_float(i64 %0, i64 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i64_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2241,11 +2241,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_u64_float(i64 %0, i64 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u64_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2254,14 +2254,14 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_i128_float(i128 %0, i128 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i128_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2270,14 +2270,14 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_u128_float(i128 %0, i128 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u128_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2286,11 +2286,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_float_float(float %0, float %1, float %2, float %3) { ; CHECK-LABEL: select_cc_float_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2299,11 +2299,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_double_float(double %0, double %1, float %2, float %3) { ; CHECK-LABEL: select_cc_double_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2312,11 +2312,11 @@ ; Function Attrs: norecurse nounwind readnone define float @select_cc_quad_float(fp128 %0, fp128 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_quad_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select fast i1 %5, float %2, float %3 ret float %6 @@ -2325,12 +2325,12 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_i1_double(i1 zeroext %0, i1 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i1_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select fast i1 %5, double %3, double %2 ret double %6 @@ -2339,11 +2339,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_i8_double(i8 signext %0, i8 signext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i8_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2352,11 +2352,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_u8_double(i8 zeroext %0, i8 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u8_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2365,11 +2365,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_i16_double(i16 signext %0, i16 signext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i16_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2378,11 +2378,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_u16_double(i16 zeroext %0, i16 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u16_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2391,11 +2391,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_i32_double(i32 signext %0, i32 signext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i32_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2404,11 +2404,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_u32_double(i32 zeroext %0, i32 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u32_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2417,11 +2417,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_i64_double(i64 %0, i64 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i64_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2430,11 +2430,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_u64_double(i64 %0, i64 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u64_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2443,14 +2443,14 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_i128_double(i128 %0, i128 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i128_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2459,14 +2459,14 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_u128_double(i128 %0, i128 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u128_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2475,11 +2475,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_float_double(float %0, float %1, double %2, double %3) { ; CHECK-LABEL: select_cc_float_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2488,11 +2488,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_double_double(double %0, double %1, double %2, double %3) { ; CHECK-LABEL: select_cc_double_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2501,11 +2501,11 @@ ; Function Attrs: norecurse nounwind readnone define double @select_cc_quad_double(fp128 %0, fp128 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_quad_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select fast i1 %5, double %2, double %3 ret double %6 @@ -2514,14 +2514,14 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_i1_quad(i1 zeroext %0, i1 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i1_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = xor i1 %0, %1 %6 = select fast i1 %5, fp128 %3, fp128 %2 ret fp128 %6 @@ -2530,13 +2530,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_i8_quad(i8 signext %0, i8 signext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i8_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2545,13 +2545,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_u8_quad(i8 zeroext %0, i8 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u8_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i8 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2560,13 +2560,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_i16_quad(i16 signext %0, i16 signext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i16_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2575,13 +2575,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_u16_quad(i16 zeroext %0, i16 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u16_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i16 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2590,13 +2590,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_i32_quad(i32 signext %0, i32 signext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i32_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2605,13 +2605,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_u32_quad(i32 zeroext %0, i32 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u32_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2620,13 +2620,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_i64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i64_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2635,13 +2635,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_u64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u64_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2650,7 +2650,7 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_i128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i128_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -2659,7 +2659,7 @@ ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2668,7 +2668,7 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_u128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u128_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -2677,7 +2677,7 @@ ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i128 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2686,13 +2686,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_float_quad(float %0, float %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_float_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq float %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2701,13 +2701,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_double_quad(double %0, double %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_double_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq double %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 @@ -2716,13 +2716,13 @@ ; Function Attrs: norecurse nounwind readnone define fp128 @select_cc_quad_quad(fp128 %0, fp128 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_quad_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s1, 0, %s7 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp fast oeq fp128 %0, %1 %6 = select fast i1 %5, fp128 %2, fp128 %3 ret fp128 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf32.ll b/llvm/test/CodeGen/VE/Scalar/selectccf32.ll --- a/llvm/test/CodeGen/VE/Scalar/selectccf32.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf32.ll @@ -2,9 +2,9 @@ define float @selectccaf(float, float, float, float) { ; CHECK-LABEL: selectccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp false float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -12,9 +12,9 @@ define float @selectccat(float, float, float, float) { ; CHECK-LABEL: selectccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp true float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -22,11 +22,11 @@ define float @selectccoeq(float, float, float, float) { ; CHECK-LABEL: selectccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oeq float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -34,11 +34,11 @@ define float @selectccone(float, float, float, float) { ; CHECK-LABEL: selectccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp one float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -46,11 +46,11 @@ define float @selectccogt(float, float, float, float) { ; CHECK-LABEL: selectccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -58,11 +58,11 @@ define float @selectccoge(float, float, float, float) { ; CHECK-LABEL: selectccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oge float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -70,11 +70,11 @@ define float @selectccolt(float, float, float, float) { ; CHECK-LABEL: selectccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp olt float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -82,11 +82,11 @@ define float @selectccole(float, float, float, float) { ; CHECK-LABEL: selectccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ole float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -94,11 +94,11 @@ define float @selectccord(float, float, float, float) { ; CHECK-LABEL: selectccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.num %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ord float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -106,11 +106,11 @@ define float @selectccuno(float, float, float, float) { ; CHECK-LABEL: selectccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uno float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -118,11 +118,11 @@ define float @selectccueq(float, float, float, float) { ; CHECK-LABEL: selectccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ueq float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -130,11 +130,11 @@ define float @selectccune(float, float, float, float) { ; CHECK-LABEL: selectccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp une float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -142,11 +142,11 @@ define float @selectccugt(float, float, float, float) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ugt float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -154,11 +154,11 @@ define float @selectccuge(float, float, float, float) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uge float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -166,11 +166,11 @@ define float @selectccult(float, float, float, float) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ult float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -178,11 +178,11 @@ define float @selectccule(float, float, float, float) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ule float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll b/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll --- a/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll @@ -2,7 +2,7 @@ define float @selectccsgti8(i8, i8, float, float) { ; CHECK-LABEL: selectccsgti8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 @@ -10,7 +10,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i8 %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -18,7 +18,7 @@ define float @selectccsgti16(i16, i16, float, float) { ; CHECK-LABEL: selectccsgti16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 @@ -26,7 +26,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i16 %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -34,11 +34,11 @@ define float @selectccsgti32(i32, i32, float, float) { ; CHECK-LABEL: selectccsgti32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -46,11 +46,11 @@ define float @selectccsgti64(i64, i64, float, float) { ; CHECK-LABEL: selectccsgti64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -58,7 +58,7 @@ define float @selectccsgti128(i128, i128, float, float) { ; CHECK-LABEL: selectccsgti128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1 @@ -70,7 +70,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -78,11 +78,11 @@ define float @selectccogtf32(float, float, float, float) { ; CHECK-LABEL: selectccogtf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt float %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -90,11 +90,11 @@ define float @selectccogtf64(double, double, float, float) { ; CHECK-LABEL: selectccogtf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt double %0, %1 %6 = select i1 %5, float %2, float %3 ret float %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll b/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll --- a/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll @@ -2,9 +2,9 @@ define float @selectccaf(float, float, float, float) { ; CHECK-LABEL: selectccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp false float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -12,9 +12,9 @@ define float @selectccat(float, float, float, float) { ; CHECK-LABEL: selectccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp true float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -22,12 +22,12 @@ define float @selectccoeq(float, float, float, float) { ; CHECK-LABEL: selectccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oeq float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -35,12 +35,12 @@ define float @selectccone(float, float, float, float) { ; CHECK-LABEL: selectccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp one float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -48,12 +48,12 @@ define float @selectccogt(float, float, float, float) { ; CHECK-LABEL: selectccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -61,12 +61,12 @@ define float @selectccoge(float, float, float, float) { ; CHECK-LABEL: selectccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oge float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -74,12 +74,12 @@ define float @selectccolt(float, float, float, float) { ; CHECK-LABEL: selectccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp olt float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -87,12 +87,12 @@ define float @selectccole(float, float, float, float) { ; CHECK-LABEL: selectccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ole float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -100,11 +100,11 @@ define float @selectccord(float, float, float, float) { ; CHECK-LABEL: selectccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: cmov.s.num %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ord float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -112,11 +112,11 @@ define float @selectccuno(float, float, float, float) { ; CHECK-LABEL: selectccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uno float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -124,12 +124,12 @@ define float @selectccueq(float, float, float, float) { ; CHECK-LABEL: selectccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ueq float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -137,12 +137,12 @@ define float @selectccune(float, float, float, float) { ; CHECK-LABEL: selectccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp une float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -150,12 +150,12 @@ define float @selectccugt(float, float, float, float) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ugt float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -163,12 +163,12 @@ define float @selectccuge(float, float, float, float) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uge float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -176,12 +176,12 @@ define float @selectccult(float, float, float, float) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ult float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 @@ -189,12 +189,12 @@ define float @selectccule(float, float, float, float) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ule float %0, 0.0 %6 = select i1 %5, float %2, float %3 ret float %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf64.ll b/llvm/test/CodeGen/VE/Scalar/selectccf64.ll --- a/llvm/test/CodeGen/VE/Scalar/selectccf64.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf64.ll @@ -2,9 +2,9 @@ define double @selectccaf(double, double, double, double) { ; CHECK-LABEL: selectccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp false double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -12,9 +12,9 @@ define double @selectccat(double, double, double, double) { ; CHECK-LABEL: selectccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp true double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -22,11 +22,11 @@ define double @selectccoeq(double, double, double, double) { ; CHECK-LABEL: selectccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oeq double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -34,11 +34,11 @@ define double @selectccone(double, double, double, double) { ; CHECK-LABEL: selectccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp one double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -46,11 +46,11 @@ define double @selectccogt(double, double, double, double) { ; CHECK-LABEL: selectccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -58,11 +58,11 @@ define double @selectccoge(double, double, double, double) { ; CHECK-LABEL: selectccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oge double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -70,11 +70,11 @@ define double @selectccolt(double, double, double, double) { ; CHECK-LABEL: selectccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp olt double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -82,11 +82,11 @@ define double @selectccole(double, double, double, double) { ; CHECK-LABEL: selectccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ole double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -94,11 +94,11 @@ define double @selectccord(double, double, double, double) { ; CHECK-LABEL: selectccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.num %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ord double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -106,11 +106,11 @@ define double @selectccuno(double, double, double, double) { ; CHECK-LABEL: selectccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uno double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -118,11 +118,11 @@ define double @selectccueq(double, double, double, double) { ; CHECK-LABEL: selectccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ueq double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -130,11 +130,11 @@ define double @selectccune(double, double, double, double) { ; CHECK-LABEL: selectccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp une double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -142,11 +142,11 @@ define double @selectccugt(double, double, double, double) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ugt double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -154,11 +154,11 @@ define double @selectccuge(double, double, double, double) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uge double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -166,11 +166,11 @@ define double @selectccult(double, double, double, double) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ult double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -178,11 +178,11 @@ define double @selectccule(double, double, double, double) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ule double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll b/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll --- a/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll @@ -2,7 +2,7 @@ define double @selectccsgti8(i8, i8, double, double) { ; CHECK-LABEL: selectccsgti8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 @@ -10,7 +10,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i8 %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -18,7 +18,7 @@ define double @selectccsgti16(i16, i16, double, double) { ; CHECK-LABEL: selectccsgti16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 @@ -26,7 +26,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i16 %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -34,11 +34,11 @@ define double @selectccsgti32(i32, i32, double, double) { ; CHECK-LABEL: selectccsgti32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -46,11 +46,11 @@ define double @selectccsgti64(i64, i64, double, double) { ; CHECK-LABEL: selectccsgti64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -58,7 +58,7 @@ define double @selectccsgti128(i128, i128, double, double) { ; CHECK-LABEL: selectccsgti128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1 @@ -70,7 +70,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -78,11 +78,11 @@ define double @selectccogtf32(float, float, double, double) { ; CHECK-LABEL: selectccogtf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt float %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -90,11 +90,11 @@ define double @selectccogtf64(double, double, double, double) { ; CHECK-LABEL: selectccogtf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt double %0, %1 %6 = select i1 %5, double %2, double %3 ret double %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll b/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll --- a/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll @@ -2,9 +2,9 @@ define double @selectccaf(double, double, double, double) { ; CHECK-LABEL: selectccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp false double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -12,9 +12,9 @@ define double @selectccat(double, double, double, double) { ; CHECK-LABEL: selectccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp true double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -22,12 +22,12 @@ define double @selectccoeq(double, double, double, double) { ; CHECK-LABEL: selectccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oeq double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -35,12 +35,12 @@ define double @selectccone(double, double, double, double) { ; CHECK-LABEL: selectccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp one double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -48,12 +48,12 @@ define double @selectccogt(double, double, double, double) { ; CHECK-LABEL: selectccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -61,12 +61,12 @@ define double @selectccoge(double, double, double, double) { ; CHECK-LABEL: selectccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp oge double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -74,12 +74,12 @@ define double @selectccolt(double, double, double, double) { ; CHECK-LABEL: selectccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp olt double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -87,12 +87,12 @@ define double @selectccole(double, double, double, double) { ; CHECK-LABEL: selectccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ole double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -100,11 +100,11 @@ define double @selectccord(double, double, double, double) { ; CHECK-LABEL: selectccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: cmov.d.num %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ord double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -112,11 +112,11 @@ define double @selectccuno(double, double, double, double) { ; CHECK-LABEL: selectccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uno double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -124,12 +124,12 @@ define double @selectccueq(double, double, double, double) { ; CHECK-LABEL: selectccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ueq double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -137,12 +137,12 @@ define double @selectccune(double, double, double, double) { ; CHECK-LABEL: selectccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp une double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -150,12 +150,12 @@ define double @selectccugt(double, double, double, double) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ugt double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -163,12 +163,12 @@ define double @selectccuge(double, double, double, double) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp uge double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -176,12 +176,12 @@ define double @selectccult(double, double, double, double) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ult double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 @@ -189,12 +189,12 @@ define double @selectccule(double, double, double, double) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ule double %0, 0.0 %6 = select i1 %5, double %2, double %3 ret double %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32.ll --- a/llvm/test/CodeGen/VE/Scalar/selectcci32.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci32.ll @@ -2,11 +2,11 @@ define i32 @selectcceq(i32, i32, i32, i32) { ; CHECK-LABEL: selectcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -14,11 +14,11 @@ define i32 @selectccne(i32, i32, i32, i32) { ; CHECK-LABEL: selectccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ne i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -26,11 +26,11 @@ define i32 @selectccsgt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -38,11 +38,11 @@ define i32 @selectccsge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sge i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -50,11 +50,11 @@ define i32 @selectccslt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp slt i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -62,11 +62,11 @@ define i32 @selectccsle(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sle i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -74,11 +74,11 @@ define i32 @selectccugt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -86,11 +86,11 @@ define i32 @selectccuge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -98,11 +98,11 @@ define i32 @selectccult(i32, i32, i32, i32) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -110,11 +110,11 @@ define i32 @selectccule(i32, i32, i32, i32) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -122,11 +122,11 @@ define i32 @selectccugt2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccugt2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -134,11 +134,11 @@ define i32 @selectccuge2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccuge2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -146,11 +146,11 @@ define i32 @selectccult2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccult2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -158,11 +158,11 @@ define i32 @selectccule2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccule2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll --- a/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll @@ -2,7 +2,7 @@ define i32 @selectccsgti8(i8, i8, i32, i32) { ; CHECK-LABEL: selectccsgti8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 @@ -10,7 +10,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i8 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -18,7 +18,7 @@ define i32 @selectccsgti16(i16, i16, i32, i32) { ; CHECK-LABEL: selectccsgti16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 @@ -26,7 +26,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i16 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -34,11 +34,11 @@ define i32 @selectccsgti32(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsgti32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -46,11 +46,11 @@ define i32 @selectccsgti64(i64, i64, i32, i32) { ; CHECK-LABEL: selectccsgti64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -58,7 +58,7 @@ define i32 @selectccsgti128(i128, i128, i32, i32) { ; CHECK-LABEL: selectccsgti128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1 @@ -70,7 +70,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -78,11 +78,11 @@ define i32 @selectccogtf32(float, float, i32, i32) { ; CHECK-LABEL: selectccogtf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt float %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -90,11 +90,11 @@ define i32 @selectccogtf64(double, double, i32, i32) { ; CHECK-LABEL: selectccogtf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt double %0, %1 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll --- a/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll @@ -2,12 +2,12 @@ define i32 @selectcceq(i32, i32, i32, i32) { ; CHECK-LABEL: selectcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -15,12 +15,12 @@ define i32 @selectccne(i32, i32, i32, i32) { ; CHECK-LABEL: selectccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ne i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -28,12 +28,12 @@ define i32 @selectccsgt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -41,12 +41,12 @@ define i32 @selectccsge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sge i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -54,12 +54,12 @@ define i32 @selectccslt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp slt i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -67,12 +67,12 @@ define i32 @selectccsle(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sle i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -80,12 +80,12 @@ define i32 @selectccugt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -93,12 +93,12 @@ define i32 @selectccuge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -106,12 +106,12 @@ define i32 @selectccult(i32, i32, i32, i32) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -119,12 +119,12 @@ define i32 @selectccule(i32, i32, i32, i32) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -132,12 +132,12 @@ define i32 @selectccugt2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccugt2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -145,12 +145,12 @@ define i32 @selectccuge2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccuge2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -158,12 +158,12 @@ define i32 @selectccult2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccult2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 @@ -171,12 +171,12 @@ define i32 @selectccule2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccule2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i32 %0, 12 %6 = select i1 %5, i32 %2, i32 %3 ret i32 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64.ll --- a/llvm/test/CodeGen/VE/Scalar/selectcci64.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci64.ll @@ -2,11 +2,11 @@ define i64 @selectcceq(i64, i64, i64, i64) { ; CHECK-LABEL: selectcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -14,11 +14,11 @@ define i64 @selectccne(i64, i64, i64, i64) { ; CHECK-LABEL: selectccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ne i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -26,11 +26,11 @@ define i64 @selectccsgt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -38,11 +38,11 @@ define i64 @selectccsge(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sge i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -50,11 +50,11 @@ define i64 @selectccslt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp slt i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -62,11 +62,11 @@ define i64 @selectccsle(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sle i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -74,11 +74,11 @@ define i64 @selectccugt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -86,11 +86,11 @@ define i64 @selectccuge(i64, i64, i64, i64) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -98,11 +98,11 @@ define i64 @selectccult(i64, i64, i64, i64) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -110,11 +110,11 @@ define i64 @selectccule(i64, i64, i64, i64) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -122,11 +122,11 @@ define i64 @selectccugt2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccugt2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -134,11 +134,11 @@ define i64 @selectccuge2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccuge2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -146,11 +146,11 @@ define i64 @selectccult2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccult2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -158,11 +158,11 @@ define i64 @selectccule2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccule2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll --- a/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll @@ -2,7 +2,7 @@ define i64 @selectccsgti8(i8, i8, i64, i64) { ; CHECK-LABEL: selectccsgti8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 @@ -10,7 +10,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i8 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -18,7 +18,7 @@ define i64 @selectccsgti16(i16, i16, i64, i64) { ; CHECK-LABEL: selectccsgti16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 @@ -26,7 +26,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i16 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -34,11 +34,11 @@ define i64 @selectccsgti32(i32, i32, i64, i64) { ; CHECK-LABEL: selectccsgti32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -46,11 +46,11 @@ define i64 @selectccsgti64(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsgti64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -58,7 +58,7 @@ define i64 @selectccsgti128(i128, i128, i64, i64) { ; CHECK-LABEL: selectccsgti128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1 @@ -70,7 +70,7 @@ ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -78,11 +78,11 @@ define i64 @selectccogtf32(float, float, i64, i64) { ; CHECK-LABEL: selectccogtf32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt float %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -90,11 +90,11 @@ define i64 @selectccogtf64(double, double, i64, i64) { ; CHECK-LABEL: selectccogtf64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = fcmp ogt double %0, %1 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll --- a/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll @@ -2,12 +2,12 @@ define i64 @selectcceq(i64, i64, i64, i64) { ; CHECK-LABEL: selectcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp eq i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -15,12 +15,12 @@ define i64 @selectccne(i64, i64, i64, i64) { ; CHECK-LABEL: selectccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ne i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -28,12 +28,12 @@ define i64 @selectccsgt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -41,12 +41,12 @@ define i64 @selectccsge(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sge i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -54,12 +54,12 @@ define i64 @selectccslt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp slt i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -67,12 +67,12 @@ define i64 @selectccsle(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sle i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -80,12 +80,12 @@ define i64 @selectccugt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -93,12 +93,12 @@ define i64 @selectccuge(i64, i64, i64, i64) { ; CHECK-LABEL: selectccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -106,12 +106,12 @@ define i64 @selectccult(i64, i64, i64, i64) { ; CHECK-LABEL: selectccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -119,12 +119,12 @@ define i64 @selectccule(i64, i64, i64, i64) { ; CHECK-LABEL: selectccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -132,12 +132,12 @@ define i64 @selectccugt2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccugt2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -145,12 +145,12 @@ define i64 @selectccuge2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccuge2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -158,12 +158,12 @@ define i64 @selectccult2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccult2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 @@ -171,12 +171,12 @@ define i64 @selectccule2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccule2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i64 %0, 12 %6 = select i1 %5, i64 %2, i64 %3 ret i64 %6 diff --git a/llvm/test/CodeGen/VE/Scalar/setcc.ll b/llvm/test/CodeGen/VE/Scalar/setcc.ll --- a/llvm/test/CodeGen/VE/Scalar/setcc.ll +++ b/llvm/test/CodeGen/VE/Scalar/setcc.ll @@ -8,10 +8,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) { ; CHECK-LABEL: setcc_i1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, 1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = xor i1 %0, %1 %4 = xor i1 %3, true ret i1 %4 @@ -20,12 +20,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: setcc_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i8 %0, %1 ret i1 %3 } @@ -33,12 +33,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: setcc_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i8 %0, %1 ret i1 %3 } @@ -46,12 +46,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: setcc_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i16 %0, %1 ret i1 %3 } @@ -59,12 +59,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: setcc_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i16 %0, %1 ret i1 %3 } @@ -72,12 +72,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: setcc_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i32 %0, %1 ret i1 %3 } @@ -85,12 +85,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: setcc_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i32 %0, %1 ret i1 %3 } @@ -98,12 +98,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_i64(i64 %0, i64 %1) { ; CHECK-LABEL: setcc_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i64 %0, %1 ret i1 %3 } @@ -111,12 +111,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_u64(i64 %0, i64 %1) { ; CHECK-LABEL: setcc_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i64 %0, %1 ret i1 %3 } @@ -124,7 +124,7 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_i128(i128 %0, i128 %1) { ; CHECK-LABEL: setcc_i128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -132,7 +132,7 @@ ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i128 %0, %1 ret i1 %3 } @@ -140,7 +140,7 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_u128(i128 %0, i128 %1) { ; CHECK-LABEL: setcc_u128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 @@ -148,7 +148,7 @@ ; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i128 %0, %1 ret i1 %3 } @@ -156,12 +156,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_float(float %0, float %1) { ; CHECK-LABEL: setcc_float: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp fast oeq float %0, %1 ret i1 %3 } @@ -169,12 +169,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_double(double %0, double %1) { ; CHECK-LABEL: setcc_double: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp fast oeq double %0, %1 ret i1 %3 } @@ -182,12 +182,12 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) { ; CHECK-LABEL: setcc_quad: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp fast oeq fp128 %0, %1 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setccf32.ll b/llvm/test/CodeGen/VE/Scalar/setccf32.ll --- a/llvm/test/CodeGen/VE/Scalar/setccf32.ll +++ b/llvm/test/CodeGen/VE/Scalar/setccf32.ll @@ -2,186 +2,186 @@ define zeroext i1 @setccaf(float, float) { ; CHECK-LABEL: setccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp false float %0, %1 ret i1 %3 } define zeroext i1 @setccat(float, float) { ; CHECK-LABEL: setccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp true float %0, %1 ret i1 %3 } define zeroext i1 @setccoeq(float, float) { ; CHECK-LABEL: setccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oeq float %0, %1 ret i1 %3 } define zeroext i1 @setccone(float, float) { ; CHECK-LABEL: setccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp one float %0, %1 ret i1 %3 } define zeroext i1 @setccogt(float, float) { ; CHECK-LABEL: setccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ogt float %0, %1 ret i1 %3 } define zeroext i1 @setccoge(float, float) { ; CHECK-LABEL: setccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oge float %0, %1 ret i1 %3 } define zeroext i1 @setccolt(float, float) { ; CHECK-LABEL: setccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp olt float %0, %1 ret i1 %3 } define zeroext i1 @setccole(float, float) { ; CHECK-LABEL: setccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ole float %0, %1 ret i1 %3 } define zeroext i1 @setccord(float, float) { ; CHECK-LABEL: setccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ord float %0, %1 ret i1 %3 } define zeroext i1 @setccuno(float, float) { ; CHECK-LABEL: setccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uno float %0, %1 ret i1 %3 } define zeroext i1 @setccueq(float, float) { ; CHECK-LABEL: setccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ueq float %0, %1 ret i1 %3 } define zeroext i1 @setccune(float, float) { ; CHECK-LABEL: setccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp une float %0, %1 ret i1 %3 } define zeroext i1 @setccugt(float, float) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ugt float %0, %1 ret i1 %3 } define zeroext i1 @setccuge(float, float) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uge float %0, %1 ret i1 %3 } define zeroext i1 @setccult(float, float) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ult float %0, %1 ret i1 %3 } define zeroext i1 @setccule(float, float) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ule float %0, %1 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setccf32i.ll b/llvm/test/CodeGen/VE/Scalar/setccf32i.ll --- a/llvm/test/CodeGen/VE/Scalar/setccf32i.ll +++ b/llvm/test/CodeGen/VE/Scalar/setccf32i.ll @@ -2,198 +2,198 @@ define zeroext i1 @setccaf(float, float) { ; CHECK-LABEL: setccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp false float %0, 0.0 ret i1 %3 } define zeroext i1 @setccat(float, float) { ; CHECK-LABEL: setccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp true float %0, 0.0 ret i1 %3 } define zeroext i1 @setccoeq(float, float) { ; CHECK-LABEL: setccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oeq float %0, 0.0 ret i1 %3 } define zeroext i1 @setccone(float, float) { ; CHECK-LABEL: setccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp one float %0, 0.0 ret i1 %3 } define zeroext i1 @setccogt(float, float) { ; CHECK-LABEL: setccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ogt float %0, 0.0 ret i1 %3 } define zeroext i1 @setccoge(float, float) { ; CHECK-LABEL: setccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oge float %0, 0.0 ret i1 %3 } define zeroext i1 @setccolt(float, float) { ; CHECK-LABEL: setccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp olt float %0, 0.0 ret i1 %3 } define zeroext i1 @setccole(float, float) { ; CHECK-LABEL: setccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ole float %0, 0.0 ret i1 %3 } define zeroext i1 @setccord(float, float) { ; CHECK-LABEL: setccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ord float %0, 0.0 ret i1 %3 } define zeroext i1 @setccuno(float, float) { ; CHECK-LABEL: setccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uno float %0, 0.0 ret i1 %3 } define zeroext i1 @setccueq(float, float) { ; CHECK-LABEL: setccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ueq float %0, 0.0 ret i1 %3 } define zeroext i1 @setccune(float, float) { ; CHECK-LABEL: setccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp une float %0, 0.0 ret i1 %3 } define zeroext i1 @setccugt(float, float) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ugt float %0, 0.0 ret i1 %3 } define zeroext i1 @setccuge(float, float) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uge float %0, 0.0 ret i1 %3 } define zeroext i1 @setccult(float, float) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ult float %0, 0.0 ret i1 %3 } define zeroext i1 @setccule(float, float) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ule float %0, 0.0 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setccf64.ll b/llvm/test/CodeGen/VE/Scalar/setccf64.ll --- a/llvm/test/CodeGen/VE/Scalar/setccf64.ll +++ b/llvm/test/CodeGen/VE/Scalar/setccf64.ll @@ -2,186 +2,186 @@ define zeroext i1 @setccaf(double, double) { ; CHECK-LABEL: setccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp false double %0, %1 ret i1 %3 } define zeroext i1 @setccat(double, double) { ; CHECK-LABEL: setccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp true double %0, %1 ret i1 %3 } define zeroext i1 @setccoeq(double, double) { ; CHECK-LABEL: setccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oeq double %0, %1 ret i1 %3 } define zeroext i1 @setccone(double, double) { ; CHECK-LABEL: setccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp one double %0, %1 ret i1 %3 } define zeroext i1 @setccogt(double, double) { ; CHECK-LABEL: setccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ogt double %0, %1 ret i1 %3 } define zeroext i1 @setccoge(double, double) { ; CHECK-LABEL: setccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oge double %0, %1 ret i1 %3 } define zeroext i1 @setccolt(double, double) { ; CHECK-LABEL: setccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp olt double %0, %1 ret i1 %3 } define zeroext i1 @setccole(double, double) { ; CHECK-LABEL: setccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ole double %0, %1 ret i1 %3 } define zeroext i1 @setccord(double, double) { ; CHECK-LABEL: setccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ord double %0, %1 ret i1 %3 } define zeroext i1 @setccuno(double, double) { ; CHECK-LABEL: setccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uno double %0, %1 ret i1 %3 } define zeroext i1 @setccueq(double, double) { ; CHECK-LABEL: setccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ueq double %0, %1 ret i1 %3 } define zeroext i1 @setccune(double, double) { ; CHECK-LABEL: setccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp une double %0, %1 ret i1 %3 } define zeroext i1 @setccugt(double, double) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ugt double %0, %1 ret i1 %3 } define zeroext i1 @setccuge(double, double) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uge double %0, %1 ret i1 %3 } define zeroext i1 @setccult(double, double) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ult double %0, %1 ret i1 %3 } define zeroext i1 @setccule(double, double) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ule double %0, %1 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setccf64i.ll b/llvm/test/CodeGen/VE/Scalar/setccf64i.ll --- a/llvm/test/CodeGen/VE/Scalar/setccf64i.ll +++ b/llvm/test/CodeGen/VE/Scalar/setccf64i.ll @@ -2,198 +2,198 @@ define zeroext i1 @setccaf(double, double) { ; CHECK-LABEL: setccaf: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp false double %0, 0.0 ret i1 %3 } define zeroext i1 @setccat(double, double) { ; CHECK-LABEL: setccat: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp true double %0, 0.0 ret i1 %3 } define zeroext i1 @setccoeq(double, double) { ; CHECK-LABEL: setccoeq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oeq double %0, 0.0 ret i1 %3 } define zeroext i1 @setccone(double, double) { ; CHECK-LABEL: setccone: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp one double %0, 0.0 ret i1 %3 } define zeroext i1 @setccogt(double, double) { ; CHECK-LABEL: setccogt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ogt double %0, 0.0 ret i1 %3 } define zeroext i1 @setccoge(double, double) { ; CHECK-LABEL: setccoge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp oge double %0, 0.0 ret i1 %3 } define zeroext i1 @setccolt(double, double) { ; CHECK-LABEL: setccolt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp olt double %0, 0.0 ret i1 %3 } define zeroext i1 @setccole(double, double) { ; CHECK-LABEL: setccole: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ole double %0, 0.0 ret i1 %3 } define zeroext i1 @setccord(double, double) { ; CHECK-LABEL: setccord: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ord double %0, 0.0 ret i1 %3 } define zeroext i1 @setccuno(double, double) { ; CHECK-LABEL: setccuno: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uno double %0, 0.0 ret i1 %3 } define zeroext i1 @setccueq(double, double) { ; CHECK-LABEL: setccueq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ueq double %0, 0.0 ret i1 %3 } define zeroext i1 @setccune(double, double) { ; CHECK-LABEL: setccune: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp une double %0, 0.0 ret i1 %3 } define zeroext i1 @setccugt(double, double) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ugt double %0, 0.0 ret i1 %3 } define zeroext i1 @setccuge(double, double) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp uge double %0, 0.0 ret i1 %3 } define zeroext i1 @setccult(double, double) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ult double %0, 0.0 ret i1 %3 } define zeroext i1 @setccule(double, double) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = fcmp ule double %0, 0.0 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setcci32.ll b/llvm/test/CodeGen/VE/Scalar/setcci32.ll --- a/llvm/test/CodeGen/VE/Scalar/setcci32.ll +++ b/llvm/test/CodeGen/VE/Scalar/setcci32.ll @@ -2,120 +2,120 @@ define zeroext i1 @setcceq(i32, i32) { ; CHECK-LABEL: setcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i32 %0, %1 ret i1 %3 } define zeroext i1 @setccne(i32, i32) { ; CHECK-LABEL: setccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ne i32 %0, %1 ret i1 %3 } define zeroext i1 @setccugt(i32, i32) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ugt i32 %0, %1 ret i1 %3 } define zeroext i1 @setccuge(i32, i32) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp uge i32 %0, %1 ret i1 %3 } define zeroext i1 @setccult(i32, i32) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ult i32 %0, %1 ret i1 %3 } define zeroext i1 @setccule(i32, i32) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ule i32 %0, %1 ret i1 %3 } define zeroext i1 @setccsgt(i32, i32) { ; CHECK-LABEL: setccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sgt i32 %0, %1 ret i1 %3 } define zeroext i1 @setccsge(i32, i32) { ; CHECK-LABEL: setccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sge i32 %0, %1 ret i1 %3 } define zeroext i1 @setccslt(i32, i32) { ; CHECK-LABEL: setccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp slt i32 %0, %1 ret i1 %3 } define zeroext i1 @setccsle(i32, i32) { ; CHECK-LABEL: setccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sle i32 %0, %1 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setcci32i.ll b/llvm/test/CodeGen/VE/Scalar/setcci32i.ll --- a/llvm/test/CodeGen/VE/Scalar/setcci32i.ll +++ b/llvm/test/CodeGen/VE/Scalar/setcci32i.ll @@ -2,130 +2,130 @@ define zeroext i1 @setcceq(i32, i32) { ; CHECK-LABEL: setcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i32 %0, 12 ret i1 %3 } define zeroext i1 @setccne(i32, i32) { ; CHECK-LABEL: setccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ne i32 %0, 12 ret i1 %3 } define zeroext i1 @setccugt(i32, i32) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ugt i32 %0, 12 ret i1 %3 } define zeroext i1 @setccuge(i32, i32) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp uge i32 %0, 12 ret i1 %3 } define zeroext i1 @setccult(i32, i32) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ult i32 %0, 12 ret i1 %3 } define zeroext i1 @setccule(i32, i32) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ule i32 %0, 12 ret i1 %3 } define zeroext i1 @setccsgt(i32, i32) { ; CHECK-LABEL: setccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sgt i32 %0, 12 ret i1 %3 } define zeroext i1 @setccsge(i32, i32) { ; CHECK-LABEL: setccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sge i32 %0, 12 ret i1 %3 } define zeroext i1 @setccslt(i32, i32) { ; CHECK-LABEL: setccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp slt i32 %0, 12 ret i1 %3 } define zeroext i1 @setccsle(i32, i32) { ; CHECK-LABEL: setccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sle i32 %0, 12 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setcci64.ll b/llvm/test/CodeGen/VE/Scalar/setcci64.ll --- a/llvm/test/CodeGen/VE/Scalar/setcci64.ll +++ b/llvm/test/CodeGen/VE/Scalar/setcci64.ll @@ -2,120 +2,120 @@ define zeroext i1 @setcceq(i64, i64) { ; CHECK-LABEL: setcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i64 %0, %1 ret i1 %3 } define zeroext i1 @setccne(i64, i64) { ; CHECK-LABEL: setccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ne i64 %0, %1 ret i1 %3 } define zeroext i1 @setccugt(i64, i64) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ugt i64 %0, %1 ret i1 %3 } define zeroext i1 @setccuge(i64, i64) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp uge i64 %0, %1 ret i1 %3 } define zeroext i1 @setccult(i64, i64) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ult i64 %0, %1 ret i1 %3 } define zeroext i1 @setccule(i64, i64) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ule i64 %0, %1 ret i1 %3 } define zeroext i1 @setccsgt(i64, i64) { ; CHECK-LABEL: setccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sgt i64 %0, %1 ret i1 %3 } define zeroext i1 @setccsge(i64, i64) { ; CHECK-LABEL: setccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sge i64 %0, %1 ret i1 %3 } define zeroext i1 @setccslt(i64, i64) { ; CHECK-LABEL: setccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp slt i64 %0, %1 ret i1 %3 } define zeroext i1 @setccsle(i64, i64) { ; CHECK-LABEL: setccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sle i64 %0, %1 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/setcci64i.ll b/llvm/test/CodeGen/VE/Scalar/setcci64i.ll --- a/llvm/test/CodeGen/VE/Scalar/setcci64i.ll +++ b/llvm/test/CodeGen/VE/Scalar/setcci64i.ll @@ -2,130 +2,130 @@ define zeroext i1 @setcceq(i64, i64) { ; CHECK-LABEL: setcceq: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp eq i64 %0, 12 ret i1 %3 } define zeroext i1 @setccne(i64, i64) { ; CHECK-LABEL: setccne: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ne i64 %0, 12 ret i1 %3 } define zeroext i1 @setccugt(i64, i64) { ; CHECK-LABEL: setccugt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ugt i64 %0, 12 ret i1 %3 } define zeroext i1 @setccuge(i64, i64) { ; CHECK-LABEL: setccuge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp uge i64 %0, 12 ret i1 %3 } define zeroext i1 @setccult(i64, i64) { ; CHECK-LABEL: setccult: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ult i64 %0, 12 ret i1 %3 } define zeroext i1 @setccule(i64, i64) { ; CHECK-LABEL: setccule: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp ule i64 %0, 12 ret i1 %3 } define zeroext i1 @setccsgt(i64, i64) { ; CHECK-LABEL: setccsgt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sgt i64 %0, 12 ret i1 %3 } define zeroext i1 @setccsge(i64, i64) { ; CHECK-LABEL: setccsge: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sge i64 %0, 12 ret i1 %3 } define zeroext i1 @setccslt(i64, i64) { ; CHECK-LABEL: setccslt: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp slt i64 %0, 12 ret i1 %3 } define zeroext i1 @setccsle(i64, i64) { ; CHECK-LABEL: setccsle: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = icmp sle i64 %0, 12 ret i1 %3 } diff --git a/llvm/test/CodeGen/VE/Scalar/shl.ll b/llvm/test/CodeGen/VE/Scalar/shl.ll --- a/llvm/test/CodeGen/VE/Scalar/shl.ll +++ b/llvm/test/CodeGen/VE/Scalar/shl.ll @@ -42,12 +42,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: shl_i8_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s1, %s1, (56)0 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i8 %0 to i32 %4 = zext i8 %1 to i32 %5 = shl i32 %3, %4 @@ -58,10 +58,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: shl_u8_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i8 %0 to i32 %4 = zext i8 %1 to i32 %5 = shl i32 %3, %4 @@ -72,12 +72,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: shl_i16_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s1, %s1, (48)0 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i16 %0 to i32 %4 = zext i16 %1 to i32 %5 = shl i32 %3, %4 @@ -88,10 +88,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: shl_u16_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i16 %0 to i32 %4 = zext i16 %1 to i32 %5 = shl i32 %3, %4 @@ -102,10 +102,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: shl_i32_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i32 %0, %1 ret i32 %3 } @@ -113,10 +113,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: shl_u32_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i32 %0, %1 ret i32 %3 } @@ -124,9 +124,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_i64_var(i64 %0, i64 %1) { ; CHECK-LABEL: shl_i64_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i64 %0, %1 ret i64 %3 } @@ -134,9 +134,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_u64_var(i64 %0, i64 %1) { ; CHECK-LABEL: shl_u64_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = shl i64 %0, %1 ret i64 %3 } @@ -172,12 +172,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @shl_const_i8(i8 signext %0) { ; CHECK-LABEL: shl_const_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i32 %3 = shl i32 -4, %2 %4 = trunc i32 %3 to i8 @@ -187,11 +187,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @shl_const_u8(i8 zeroext %0) { ; CHECK-LABEL: shl_const_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: lea %s1, 252 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i32 %3 = shl i32 -4, %2 %4 = trunc i32 %3 to i8 @@ -201,12 +201,12 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @shl_const_i16(i16 signext %0) { ; CHECK-LABEL: shl_const_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i32 %3 = shl i32 -4, %2 %4 = trunc i32 %3 to i16 @@ -216,11 +216,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @shl_const_u16(i16 zeroext %0) { ; CHECK-LABEL: shl_const_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: lea %s1, 65532 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i32 %3 = shl i32 -4, %2 %4 = trunc i32 %3 to i16 @@ -230,10 +230,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @shl_const_i32(i32 signext %0) { ; CHECK-LABEL: shl_const_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i32 -4, %0 ret i32 %2 } @@ -241,10 +241,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @shl_const_u32(i32 zeroext %0) { ; CHECK-LABEL: shl_const_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i32 -4, %0 ret i32 %2 } @@ -252,9 +252,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_const_i64(i64 %0) { ; CHECK-LABEL: shl_const_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, (62)1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i64 -4, %0 ret i64 %2 } @@ -262,9 +262,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_const_u64(i64 %0) { ; CHECK-LABEL: shl_const_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, (62)1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i64 -4, %0 ret i64 %2 } @@ -304,11 +304,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @shl_i8_const(i8 signext %0) { ; CHECK-LABEL: shl_i8_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 3 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i8 %0, 3 ret i8 %2 } @@ -316,11 +316,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @shl_u8_const(i8 zeroext %0) { ; CHECK-LABEL: shl_u8_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 3 ; CHECK-NEXT: lea %s1, 248 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i8 %0, 3 ret i8 %2 } @@ -328,11 +328,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @shl_i16_const(i16 signext %0) { ; CHECK-LABEL: shl_i16_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 7 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i16 %0, 7 ret i16 %2 } @@ -340,11 +340,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @shl_u16_const(i16 zeroext %0) { ; CHECK-LABEL: shl_u16_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 7 ; CHECK-NEXT: lea %s1, 65408 ; CHECK-NEXT: and %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i16 %0, 7 ret i16 %2 } @@ -352,10 +352,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @shl_i32_const(i32 signext %0) { ; CHECK-LABEL: shl_i32_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 15 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i32 %0, 15 ret i32 %2 } @@ -363,10 +363,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @shl_u32_const(i32 zeroext %0) { ; CHECK-LABEL: shl_u32_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sla.w.sx %s0, %s0, 15 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i32 %0, 15 ret i32 %2 } @@ -374,9 +374,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_i64_const(i64 %0) { ; CHECK-LABEL: shl_i64_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i64 %0, 63 ret i64 %2 } @@ -384,9 +384,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_u64_const(i64 %0) { ; CHECK-LABEL: shl_u64_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s0, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i64 %0, 63 ret i64 %2 } @@ -394,10 +394,10 @@ ; Function Attrs: norecurse nounwind readnone define i128 @shl_i128_const(i128 %0) { ; CHECK-LABEL: shl_i128_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s0, 63 ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i128 %0, 127 ret i128 %2 } @@ -405,10 +405,10 @@ ; Function Attrs: norecurse nounwind readnone define i128 @shl_u128_const(i128 %0) { ; CHECK-LABEL: shl_u128_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sll %s1, %s0, 63 ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = shl i128 %0, 127 ret i128 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/shr.ll b/llvm/test/CodeGen/VE/Scalar/shr.ll --- a/llvm/test/CodeGen/VE/Scalar/shr.ll +++ b/llvm/test/CodeGen/VE/Scalar/shr.ll @@ -76,11 +76,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: shl_i8_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s1, %s1, (56)0 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i8 %0 to i32 %4 = zext i8 %1 to i32 %5 = ashr i32 %3, %4 @@ -91,11 +91,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: shl_u8_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i8 %0 to i32 %4 = zext i8 %1 to i32 %5 = lshr i32 %3, %4 @@ -106,11 +106,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: shl_i16_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s1, %s1, (48)0 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sext i16 %0 to i32 %4 = zext i16 %1 to i32 %5 = ashr i32 %3, %4 @@ -121,11 +121,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: shl_u16_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = zext i16 %0 to i32 %4 = zext i16 %1 to i32 %5 = lshr i32 %3, %4 @@ -136,10 +136,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: shl_i32_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = ashr i32 %0, %1 ret i32 %3 } @@ -147,11 +147,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: shl_u32_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = lshr i32 %0, %1 ret i32 %3 } @@ -159,9 +159,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_i64_var(i64 %0, i64 %1) { ; CHECK-LABEL: shl_i64_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = ashr i64 %0, %1 ret i64 %3 } @@ -169,9 +169,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_u64_var(i64 %0, i64 %1) { ; CHECK-LABEL: shl_u64_var: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = lshr i64 %0, %1 ret i64 %3 } @@ -207,11 +207,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @shl_const_i8(i8 signext %0) { ; CHECK-LABEL: shl_const_i8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i32 %3 = ashr i32 -4, %2 %4 = trunc i32 %3 to i8 @@ -221,10 +221,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @shl_const_u8(i8 zeroext %0) { ; CHECK-LABEL: shl_const_u8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i8 %0 to i32 %3 = ashr i32 -4, %2 %4 = trunc i32 %3 to i8 @@ -234,11 +234,11 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @shl_const_i16(i16 signext %0) { ; CHECK-LABEL: shl_const_i16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i32 %3 = ashr i32 -4, %2 %4 = trunc i32 %3 to i16 @@ -248,10 +248,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @shl_const_u16(i16 zeroext %0) { ; CHECK-LABEL: shl_const_u16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = zext i16 %0 to i32 %3 = ashr i32 -4, %2 %4 = trunc i32 %3 to i16 @@ -261,10 +261,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @shl_const_i32(i32 signext %0) { ; CHECK-LABEL: shl_const_i32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i32 -4, %0 ret i32 %2 } @@ -272,10 +272,10 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @shl_const_u32(i32 zeroext %0) { ; CHECK-LABEL: shl_const_u32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i32 -4, %0 ret i32 %2 } @@ -283,9 +283,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_const_i64(i64 %0) { ; CHECK-LABEL: shl_const_i64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, (62)1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i64 -4, %0 ret i64 %2 } @@ -293,9 +293,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_const_u64(i64 %0) { ; CHECK-LABEL: shl_const_u64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, (62)1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i64 -4, %0 ret i64 %2 } @@ -335,10 +335,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i8 @shl_i8_const(i8 signext %0) { ; CHECK-LABEL: shl_i8_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, 3 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i8 %0, 3 ret i8 %2 } @@ -346,11 +346,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i8 @shl_u8_const(i8 zeroext %0) { ; CHECK-LABEL: shl_u8_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 3 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i8 %0, 3 ret i8 %2 } @@ -358,10 +358,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i16 @shl_i16_const(i16 signext %0) { ; CHECK-LABEL: shl_i16_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, 7 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i16 %0, 7 ret i16 %2 } @@ -369,11 +369,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i16 @shl_u16_const(i16 zeroext %0) { ; CHECK-LABEL: shl_u16_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 7 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i16 %0, 7 ret i16 %2 } @@ -381,10 +381,10 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @shl_i32_const(i32 signext %0) { ; CHECK-LABEL: shl_i32_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.w.sx %s0, %s0, 15 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i32 %0, 15 ret i32 %2 } @@ -392,11 +392,11 @@ ; Function Attrs: norecurse nounwind readnone define zeroext i32 @shl_u32_const(i32 zeroext %0) { ; CHECK-LABEL: shl_u32_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: srl %s0, %s0, 15 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i32 %0, 15 ret i32 %2 } @@ -404,9 +404,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_i64_const(i64 %0) { ; CHECK-LABEL: shl_i64_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i64 %0, 63 ret i64 %2 } @@ -414,9 +414,9 @@ ; Function Attrs: norecurse nounwind readnone define i64 @shl_u64_const(i64 %0) { ; CHECK-LABEL: shl_u64_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s0, %s0, 63 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i64 %0, 63 ret i64 %2 } @@ -424,10 +424,10 @@ ; Function Attrs: norecurse nounwind readnone define i128 @shl_i128_const(i128 %0) { ; CHECK-LABEL: shl_i128_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: sra.l %s0, %s1, 63 ; CHECK-NEXT: or %s1, 0, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = ashr i128 %0, 127 ret i128 %2 } @@ -435,10 +435,10 @@ ; Function Attrs: norecurse nounwind readnone define i128 @shl_u128_const(i128 %0) { ; CHECK-LABEL: shl_u128_const: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: srl %s0, %s1, 63 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = lshr i128 %0, 127 ret i128 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/simple_prologue_epilogue.ll b/llvm/test/CodeGen/VE/Scalar/simple_prologue_epilogue.ll deleted file mode 100644 --- a/llvm/test/CodeGen/VE/Scalar/simple_prologue_epilogue.ll +++ /dev/null @@ -1,95 +0,0 @@ -; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s - -define void @func() { -; CHECK-LABEL: func: -; CHECK: # %bb.0: -; CHECK-NEXT: st %s9, (, %s11) -; CHECK-NEXT: st %s10, 8(, %s11) -; CHECK-NEXT: st %s15, 24(, %s11) -; CHECK-NEXT: st %s16, 32(, %s11) -; CHECK-NEXT: or %s9, 0, %s11 -; CHECK-NEXT: lea %s13, -176 -; CHECK-NEXT: and %s13, %s13, (32)0 -; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: ld %s61, 24(, %s14) -; CHECK-NEXT: or %s62, 0, %s0 -; CHECK-NEXT: lea %s63, 315 -; CHECK-NEXT: shm.l %s63, (%s61) -; CHECK-NEXT: shm.l %s8, 8(%s61) -; CHECK-NEXT: shm.l %s11, 16(%s61) -; CHECK-NEXT: monc -; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: or %s11, 0, %s9 -; CHECK-NEXT: ld %s16, 32(, %s11) -; CHECK-NEXT: ld %s15, 24(, %s11) -; CHECK-NEXT: ld %s10, 8(, %s11) -; CHECK-NEXT: ld %s9, (, %s11) -; CHECK-NEXT: b.l.t (, %s10) - ret void -} - -define i64 @func1(i64) { -; CHECK-LABEL: func1: -; CHECK: # %bb.0: -; CHECK-NEXT: st %s9, (, %s11) -; CHECK-NEXT: st %s10, 8(, %s11) -; CHECK-NEXT: st %s15, 24(, %s11) -; CHECK-NEXT: st %s16, 32(, %s11) -; CHECK-NEXT: or %s9, 0, %s11 -; CHECK-NEXT: lea %s13, -176 -; CHECK-NEXT: and %s13, %s13, (32)0 -; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: ld %s61, 24(, %s14) -; CHECK-NEXT: or %s62, 0, %s0 -; CHECK-NEXT: lea %s63, 315 -; CHECK-NEXT: shm.l %s63, (%s61) -; CHECK-NEXT: shm.l %s8, 8(%s61) -; CHECK-NEXT: shm.l %s11, 16(%s61) -; CHECK-NEXT: monc -; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB1_2: -; CHECK-NEXT: or %s11, 0, %s9 -; CHECK-NEXT: ld %s16, 32(, %s11) -; CHECK-NEXT: ld %s15, 24(, %s11) -; CHECK-NEXT: ld %s10, 8(, %s11) -; CHECK-NEXT: ld %s9, (, %s11) -; CHECK-NEXT: b.l.t (, %s10) - ret i64 %0 -} - -define i64 @func2(i64, i64, i64, i64, i64) { -; CHECK-LABEL: func2: -; CHECK: # %bb.0: -; CHECK-NEXT: st %s9, (, %s11) -; CHECK-NEXT: st %s10, 8(, %s11) -; CHECK-NEXT: st %s15, 24(, %s11) -; CHECK-NEXT: st %s16, 32(, %s11) -; CHECK-NEXT: or %s9, 0, %s11 -; CHECK-NEXT: lea %s13, -176 -; CHECK-NEXT: and %s13, %s13, (32)0 -; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: ld %s61, 24(, %s14) -; CHECK-NEXT: or %s62, 0, %s0 -; CHECK-NEXT: lea %s63, 315 -; CHECK-NEXT: shm.l %s63, (%s61) -; CHECK-NEXT: shm.l %s8, 8(%s61) -; CHECK-NEXT: shm.l %s11, 16(%s61) -; CHECK-NEXT: monc -; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB2_2: -; CHECK-NEXT: or %s0, 0, %s4 -; CHECK-NEXT: or %s11, 0, %s9 -; CHECK-NEXT: ld %s16, 32(, %s11) -; CHECK-NEXT: ld %s15, 24(, %s11) -; CHECK-NEXT: ld %s10, 8(, %s11) -; CHECK-NEXT: ld %s9, (, %s11) -; CHECK-NEXT: b.l.t (, %s10) - ret i64 %4 -} diff --git a/llvm/test/CodeGen/VE/Scalar/store-align1.ll b/llvm/test/CodeGen/VE/Scalar/store-align1.ll --- a/llvm/test/CodeGen/VE/Scalar/store-align1.ll +++ b/llvm/test/CodeGen/VE/Scalar/store-align1.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef64com(double %0) { ; CHECK-LABEL: storef64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store double %0, double* @vf64, align 1 ret void } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef32com(float %0) { ; CHECK-LABEL: storef32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: stu %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store float %0, float* @vf32, align 1 ret void } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei64com(i64 %0) { ; CHECK-LABEL: storei64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i64 %0, i64* @vi64, align 1 ret void } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32com(i32 %0) { ; CHECK-LABEL: storei32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i32 %0, i32* @vi32, align 1 ret void } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16com(i16 %0) { ; CHECK-LABEL: storei16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: st2b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i16 %0, i16* @vi16, align 1 ret void } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8com(i8 %0) { ; CHECK-LABEL: storei8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: st1b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i8 %0, i8* @vi8, align 1 ret void } diff --git a/llvm/test/CodeGen/VE/Scalar/store-align2.ll b/llvm/test/CodeGen/VE/Scalar/store-align2.ll --- a/llvm/test/CodeGen/VE/Scalar/store-align2.ll +++ b/llvm/test/CodeGen/VE/Scalar/store-align2.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef64com(double %0) { ; CHECK-LABEL: storef64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store double %0, double* @vf64, align 2 ret void } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef32com(float %0) { ; CHECK-LABEL: storef32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: stu %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store float %0, float* @vf32, align 2 ret void } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei64com(i64 %0) { ; CHECK-LABEL: storei64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i64 %0, i64* @vi64, align 2 ret void } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32com(i32 %0) { ; CHECK-LABEL: storei32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i32 %0, i32* @vi32, align 2 ret void } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16com(i16 %0) { ; CHECK-LABEL: storei16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: st2b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i16 %0, i16* @vi16, align 2 ret void } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8com(i8 %0) { ; CHECK-LABEL: storei8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: st1b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i8 %0, i8* @vi8, align 2 ret void } diff --git a/llvm/test/CodeGen/VE/Scalar/store-align4.ll b/llvm/test/CodeGen/VE/Scalar/store-align4.ll --- a/llvm/test/CodeGen/VE/Scalar/store-align4.ll +++ b/llvm/test/CodeGen/VE/Scalar/store-align4.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef64com(double %0) { ; CHECK-LABEL: storef64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store double %0, double* @vf64, align 4 ret void } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef32com(float %0) { ; CHECK-LABEL: storef32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: stu %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store float %0, float* @vf32, align 4 ret void } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei64com(i64 %0) { ; CHECK-LABEL: storei64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i64 %0, i64* @vi64, align 4 ret void } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32com(i32 %0) { ; CHECK-LABEL: storei32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i32 %0, i32* @vi32, align 4 ret void } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16com(i16 %0) { ; CHECK-LABEL: storei16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: st2b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i16 %0, i16* @vi16, align 4 ret void } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8com(i8 %0) { ; CHECK-LABEL: storei8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: st1b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i8 %0, i8* @vi8, align 4 ret void } diff --git a/llvm/test/CodeGen/VE/Scalar/store-align8.ll b/llvm/test/CodeGen/VE/Scalar/store-align8.ll --- a/llvm/test/CodeGen/VE/Scalar/store-align8.ll +++ b/llvm/test/CodeGen/VE/Scalar/store-align8.ll @@ -76,12 +76,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef64com(double %0) { ; CHECK-LABEL: storef64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store double %0, double* @vf64, align 8 ret void } @@ -89,12 +89,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef32com(float %0) { ; CHECK-LABEL: storef32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: stu %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store float %0, float* @vf32, align 8 ret void } @@ -102,12 +102,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei64com(i64 %0) { ; CHECK-LABEL: storei64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i64 %0, i64* @vi64, align 8 ret void } @@ -115,12 +115,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32com(i32 %0) { ; CHECK-LABEL: storei32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i32 %0, i32* @vi32, align 8 ret void } @@ -128,12 +128,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16com(i16 %0) { ; CHECK-LABEL: storei16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: st2b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i16 %0, i16* @vi16, align 8 ret void } @@ -141,12 +141,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8com(i8 %0) { ; CHECK-LABEL: storei8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: st1b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i8 %0, i8* @vi8, align 8 ret void } diff --git a/llvm/test/CodeGen/VE/Scalar/store.ll b/llvm/test/CodeGen/VE/Scalar/store.ll --- a/llvm/test/CodeGen/VE/Scalar/store.ll +++ b/llvm/test/CodeGen/VE/Scalar/store.ll @@ -3,10 +3,10 @@ ; Function Attrs: norecurse nounwind readonly define void @storef128(fp128* nocapture %0, fp128 %1) { ; CHECK-LABEL: storef128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s2, 8(, %s0) ; CHECK-NEXT: st %s3, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store fp128 %1, fp128* %0, align 16 ret void } @@ -14,9 +14,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storef64(double* nocapture %0, double %1) { ; CHECK-LABEL: storef64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store double %1, double* %0, align 16 ret void } @@ -24,9 +24,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storef32(float* nocapture %0, float %1) { ; CHECK-LABEL: storef32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stu %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store float %1, float* %0, align 16 ret void } @@ -34,10 +34,10 @@ ; Function Attrs: norecurse nounwind readonly define void @storei128(i128* nocapture %0, i128 %1) { ; CHECK-LABEL: storei128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s2, 8(, %s0) ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i128 %1, i128* %0, align 16 ret void } @@ -45,9 +45,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei64(i64* nocapture %0, i64 %1) { ; CHECK-LABEL: storei64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i64 %1, i64* %0, align 16 ret void } @@ -55,9 +55,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32(i32* nocapture %0, i32 %1) { ; CHECK-LABEL: storei32: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i32 %1, i32* %0, align 16 ret void } @@ -65,9 +65,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32tr(i32* nocapture %0, i64 %1) { ; CHECK-LABEL: storei32tr: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = trunc i64 %1 to i32 store i32 %3, i32* %0, align 16 ret void @@ -76,9 +76,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16(i16* nocapture %0, i16 %1) { ; CHECK-LABEL: storei16: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i16 %1, i16* %0, align 16 ret void } @@ -86,9 +86,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16tr(i16* nocapture %0, i64 %1) { ; CHECK-LABEL: storei16tr: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = trunc i64 %1 to i16 store i16 %3, i16* %0, align 16 ret void @@ -97,9 +97,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8(i8* nocapture %0, i8 %1) { ; CHECK-LABEL: storei8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i8 %1, i8* %0, align 16 ret void } @@ -107,9 +107,9 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8tr(i8* nocapture %0, i64 %1) { ; CHECK-LABEL: storei8tr: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = trunc i64 %1 to i8 store i8 %3, i8* %0, align 16 ret void diff --git a/llvm/test/CodeGen/VE/Scalar/store_gv.ll b/llvm/test/CodeGen/VE/Scalar/store_gv.ll --- a/llvm/test/CodeGen/VE/Scalar/store_gv.ll +++ b/llvm/test/CodeGen/VE/Scalar/store_gv.ll @@ -12,13 +12,13 @@ ; Function Attrs: norecurse nounwind readonly define void @storef128com(fp128 %0) { ; CHECK-LABEL: storef128com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, vf128@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s2) ; CHECK-NEXT: st %s0, 8(, %s2) ; CHECK-NEXT: st %s1, (, %s2) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store fp128 %0, fp128* @vf128, align 16 ret void } @@ -26,12 +26,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef64com(double %0) { ; CHECK-LABEL: storef64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store double %0, double* @vf64, align 8 ret void } @@ -39,12 +39,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storef32com(float %0) { ; CHECK-LABEL: storef32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: stu %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store float %0, float* @vf32, align 4 ret void } @@ -52,13 +52,13 @@ ; Function Attrs: norecurse nounwind readonly define void @storei128com(i128 %0) { ; CHECK-LABEL: storei128com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, vi128@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, vi128@hi(, %s2) ; CHECK-NEXT: st %s1, 8(, %s2) ; CHECK-NEXT: st %s0, (, %s2) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i128 %0, i128* @vi128, align 16 ret void } @@ -66,12 +66,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei64com(i64 %0) { ; CHECK-LABEL: storei64com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i64 %0, i64* @vi64, align 8 ret void } @@ -79,12 +79,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei32com(i32 %0) { ; CHECK-LABEL: storei32com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i32 %0, i32* @vi32, align 4 ret void } @@ -92,12 +92,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei16com(i16 %0) { ; CHECK-LABEL: storei16com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: st2b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i16 %0, i16* @vi16, align 2 ret void } @@ -105,12 +105,12 @@ ; Function Attrs: norecurse nounwind readonly define void @storei8com(i8 %0) { ; CHECK-LABEL: storei8com: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: st1b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) store i8 %0, i8* @vi8, align 1 ret void } diff --git a/llvm/test/CodeGen/VE/Scalar/subtraction.ll b/llvm/test/CodeGen/VE/Scalar/subtraction.ll --- a/llvm/test/CodeGen/VE/Scalar/subtraction.ll +++ b/llvm/test/CodeGen/VE/Scalar/subtraction.ll @@ -2,48 +2,48 @@ define signext i8 @func8s(i8 signext %0, i8 signext %1) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i8 %0, %1 ret i8 %3 } define signext i16 @func16s(i16 signext %0, i16 signext %1) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i16 %0, %1 ret i16 %3 } define signext i32 @func32s(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub nsw i32 %0, %1 ret i32 %3 } define i64 @func64s(i64 %0, i64 %1) { ; CHECK-LABEL: func64s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub nsw i64 %0, %1 ret i64 %3 } define i128 @func128s(i128 %0, i128 %1) { ; CHECK-LABEL: func128s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: cmpu.l %s3, %s0, %s2 ; CHECK-NEXT: or %s4, 0, (0)1 @@ -51,53 +51,53 @@ ; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1 ; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: subs.l %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub nsw i128 %0, %1 ret i128 %3 } define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i8 %0, %1 ret i8 %3 } define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i16 %0, %1 ret i16 %3 } define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i32 %0, %1 ret i32 %3 } define i64 @func64z(i64 %0, i64 %1) { ; CHECK-LABEL: func64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.l %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i64 %0, %1 ret i64 %3 } define i128 @func128z(i128 %0, i128 %1) { ; CHECK-LABEL: func128z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: cmpu.l %s3, %s0, %s2 ; CHECK-NEXT: or %s4, 0, (0)1 @@ -105,55 +105,55 @@ ; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1 ; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: subs.l %s0, %s0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = sub i128 %0, %1 ret i128 %3 } define signext i8 @funci8s(i8 signext %a) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i8 %a, -5 ret i8 %ret } define signext i16 @funci16s(i16 signext %a) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i16 %a, -5 ret i16 %ret } define signext i32 @funci32s(i32 signext %a) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i32 %a, -5 ret i32 %ret } define i64 @funci64s(i64 %a) { ; CHECK-LABEL: funci64s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -5(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add nsw i64 %a, -5 ret i64 %ret } define i128 @funci128s(i128 %0) { ; CHECK-LABEL: funci128s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, -5(, %s0) ; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -161,53 +161,53 @@ ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: lea %s1, -1(%s0, %s1) ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i128 %0, -5 ret i128 %2 } define zeroext i8 @funci8z(i8 zeroext %a) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: and %s0, %s0, (56)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i8 %a, -5 ret i8 %ret } define zeroext i16 @funci16z(i16 zeroext %a) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: and %s0, %s0, (48)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i16 %a, -5 ret i16 %ret } define zeroext i32 @funci32z(i32 zeroext %a) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i32 %a, -5 ret i32 %ret } define i64 @funci64z(i64 %a) { ; CHECK-LABEL: funci64z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -5(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add i64 %a, -5 ret i64 %ret } define i128 @funci128z(i128 %0) { ; CHECK-LABEL: funci128z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, -5(, %s0) ; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -215,23 +215,23 @@ ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: lea %s1, -1(%s0, %s1) ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add i128 %0, -5 ret i128 %2 } define i64 @funci64_2(i64 %a) { ; CHECK-LABEL: funci64_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s0, -2147483648(, %s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %ret = add nsw i64 %a, -2147483648 ret i64 %ret } define i128 @funci128_2(i128 %0) { ; CHECK-LABEL: funci128_2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, -2147483648(, %s0) ; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: or %s3, 0, (0)1 @@ -239,7 +239,7 @@ ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: lea %s1, -1(%s0, %s1) ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = add nsw i128 %0, -2147483648 ret i128 %2 } diff --git a/llvm/test/CodeGen/VE/Scalar/symbol_relocation_tls.ll b/llvm/test/CodeGen/VE/Scalar/symbol_relocation_tls.ll --- a/llvm/test/CodeGen/VE/Scalar/symbol_relocation_tls.ll +++ b/llvm/test/CodeGen/VE/Scalar/symbol_relocation_tls.ll @@ -104,7 +104,7 @@ ; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: stl %s18, (, %s0) -; GENDYN-NEXT: ld %s18, 48(, %s9) +; GENDYN-NEXT: ld %s18, 288(, %s11) ; GENDYN-NEXT: or %s11, 0, %s9 ; ; GENDYNPIC: lea %s15, (-24) @@ -126,7 +126,7 @@ ; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: stl %s18, (, %s0) -; GENDYNPIC-NEXT: ld %s18, 48(, %s9) +; GENDYNPIC-NEXT: ld %s18, 288(, %s11) ; GENDYNPIC-NEXT: or %s11, 0, %s9 entry: store i32 %v, i32* @x, align 4 @@ -148,7 +148,7 @@ ; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: stl %s18, (, %s0) -; GENDYN-NEXT: ld %s18, 48(, %s9) +; GENDYN-NEXT: ld %s18, 288(, %s11) ; GENDYN-NEXT: or %s11, 0, %s9 ; ; GENDYNPIC: lea %s15, (-24) @@ -170,7 +170,7 @@ ; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: stl %s18, (, %s0) -; GENDYNPIC-NEXT: ld %s18, 48(, %s9) +; GENDYNPIC-NEXT: ld %s18, 288(, %s11) ; GENDYNPIC-NEXT: or %s11, 0, %s9 entry: store i32 %v, i32* @y, align 4 diff --git a/llvm/test/CodeGen/VE/Scalar/tls.ll b/llvm/test/CodeGen/VE/Scalar/tls.ll --- a/llvm/test/CodeGen/VE/Scalar/tls.ll +++ b/llvm/test/CodeGen/VE/Scalar/tls.ll @@ -37,6 +37,7 @@ ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: or %s11, 0, %s9 +; ; LOCAL-LABEL: get_global: ; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL-NEXT: lea %s34, x@tpoff_lo @@ -77,6 +78,7 @@ ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: or %s11, 0, %s9 +; ; LOCAL-LABEL: get_local: ; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL-NEXT: lea %s34, y@tpoff_lo @@ -92,7 +94,7 @@ define void @set_global(i32 %v) { ; GENDYN-LABEL: set_global: ; GENDYN: .LBB{{[0-9]+}}_2: -; GENDYN-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; GENDYN-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; GENDYN-NEXT: or %s18, 0, %s0 ; GENDYN-NEXT: lea %s0, x@tls_gd_lo(-24) ; GENDYN-NEXT: and %s0, %s0, (32)0 @@ -103,12 +105,12 @@ ; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: stl %s18, (, %s0) -; GENDYN-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; GENDYN-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; GENDYN-NEXT: or %s11, 0, %s9 ; ; GENDYNPIC-LABEL: set_global: ; GENDYNPIC: .LBB{{[0-9]+}}_2: -; GENDYNPIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; GENDYNPIC-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; GENDYNPIC-NEXT: or %s18, 0, %s0 ; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; GENDYNPIC-NEXT: and %s15, %s15, (32)0 @@ -123,8 +125,9 @@ ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: stl %s18, (, %s0) -; GENDYNPIC-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; GENDYNPIC-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; GENDYNPIC-NEXT: or %s11, 0, %s9 +; ; LOCAL-LABEL: set_global: ; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL-NEXT: lea %s34, x@tpoff_lo @@ -142,7 +145,7 @@ define void @set_local(i32 %v) { ; GENDYN-LABEL: set_local: ; GENDYN: .LBB{{[0-9]+}}_2: -; GENDYN-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; GENDYN-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; GENDYN-NEXT: or %s18, 0, %s0 ; GENDYN-NEXT: lea %s0, y@tls_gd_lo(-24) ; GENDYN-NEXT: and %s0, %s0, (32)0 @@ -153,12 +156,12 @@ ; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: stl %s18, (, %s0) -; GENDYN-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; GENDYN-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; GENDYN-NEXT: or %s11, 0, %s9 ; ; GENDYNPIC-LABEL: set_local: ; GENDYNPIC: .LBB{{[0-9]+}}_2: -; GENDYNPIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill +; GENDYNPIC-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill ; GENDYNPIC-NEXT: or %s18, 0, %s0 ; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; GENDYNPIC-NEXT: and %s15, %s15, (32)0 @@ -173,8 +176,9 @@ ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: stl %s18, (, %s0) -; GENDYNPIC-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload +; GENDYNPIC-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload ; GENDYNPIC-NEXT: or %s11, 0, %s9 +; ; LOCAL-LABEL: set_local: ; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL-NEXT: lea %s34, y@tpoff_lo diff --git a/llvm/test/CodeGen/VE/Scalar/truncstore.ll b/llvm/test/CodeGen/VE/Scalar/truncstore.ll --- a/llvm/test/CodeGen/VE/Scalar/truncstore.ll +++ b/llvm/test/CodeGen/VE/Scalar/truncstore.ll @@ -2,9 +2,9 @@ define void @func0(i1 signext %p, i8* %a) { ; CHECK-LABEL: func0: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st1b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i1 %p to i8 store i8 %p.conv, i8* %a, align 2 ret void @@ -12,9 +12,9 @@ define void @func1(i8 signext %p, i16* %a) { ; CHECK-LABEL: func1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st2b %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i8 %p to i16 store i16 %p.conv, i16* %a, align 2 ret void @@ -22,9 +22,9 @@ define void @func2(i8 signext %p, i32* %a) { ; CHECK-LABEL: func2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i8 %p to i32 store i32 %p.conv, i32* %a, align 4 ret void @@ -32,9 +32,9 @@ define void @func3(i8 signext %p, i64* %a) { ; CHECK-LABEL: func3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i8 %p to i64 store i64 %p.conv, i64* %a, align 8 ret void @@ -42,9 +42,9 @@ define void @func5(i16 signext %p, i32* %a) { ; CHECK-LABEL: func5: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: stl %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i16 %p to i32 store i32 %p.conv, i32* %a, align 4 ret void @@ -52,9 +52,9 @@ define void @func6(i16 signext %p, i64* %a) { ; CHECK-LABEL: func6: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i16 %p to i64 store i64 %p.conv, i64* %a, align 8 ret void @@ -62,10 +62,10 @@ define void @func8(i32 %p, i64* %a) { ; CHECK-LABEL: func8: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: st %s0, (, %s1) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %p.conv = sext i32 %p to i64 store i64 %p.conv, i64* %a, align 8 ret void diff --git a/llvm/test/CodeGen/VE/Scalar/xor.ll b/llvm/test/CodeGen/VE/Scalar/xor.ll --- a/llvm/test/CodeGen/VE/Scalar/xor.ll +++ b/llvm/test/CodeGen/VE/Scalar/xor.ll @@ -2,120 +2,120 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: func8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i8 %a, %b ret i8 %res } define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: func8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i8 %b, %a ret i8 %res } define signext i8 @funci8s(i8 signext %a) { ; CHECK-LABEL: funci8s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i8 %a, 5 ret i8 %res } define zeroext i8 @funci8z(i8 zeroext %a) { ; CHECK-LABEL: funci8z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i8 -5, %a ret i8 %res } define signext i16 @func16s(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: func16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i16 %a, %b ret i16 %res } define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: func16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i16 %b, %a ret i16 %res } define signext i16 @funci16s(i16 signext %a) { ; CHECK-LABEL: funci16s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, -1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i16 %a, 65535 ret i16 %res } define zeroext i16 @funci16z(i16 zeroext %a) { ; CHECK-LABEL: funci16z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, (52)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i16 4095, %a ret i16 %res } define signext i32 @func32s(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: func32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i32 %a, %b ret i32 %res } define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: func32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i32 %a, %b ret i32 %res } define signext i32 @funci32s(i32 signext %a) { ; CHECK-LABEL: funci32s: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i32 %a, 268435455 ret i32 %res } define zeroext i32 @funci32z(i32 zeroext %a) { ; CHECK-LABEL: funci32z: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, (36)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i32 %a, 268435455 ret i32 %res } define i32 @funci32_another(i32 %0) { ; CHECK-LABEL: funci32_another: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = xor i32 %0, -2147483648 ret i32 %2 } @@ -123,37 +123,37 @@ define i64 @func64(i64 %a, i64 %b) { ; CHECK-LABEL: func64: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i64 %a, %b ret i64 %res } define i64 @func64i(i64 %a) { ; CHECK-LABEL: func64i: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s0, (24)0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i64 %a, 1099511627775 ret i64 %res } define i128 @func128(i128 %a, i128 %b) { ; CHECK-LABEL: func128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, %s2, %s0 ; CHECK-NEXT: xor %s1, %s3, %s1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i128 %b, %a ret i128 %res } define i128 @funci128(i128 %a) { ; CHECK-LABEL: funci128: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: xor %s0, 5, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %res = xor i128 %a, 5 ret i128 %res } diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll b/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll --- a/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll +++ b/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll @@ -8,14 +8,14 @@ ; Function Attrs: nounwind define void @lsv_vvss(i8* %0, i64 %1, i32 signext %2) { ; CHECK-LABEL: lsv_vvss: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1 ; CHECK-NEXT: lsv %v0(%s2), %s1 ; CHECK-NEXT: vst %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.lsv.vvss(<256 x double> %4, i32 %2, i64 %1) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %5, i64 8, i8* %0, i32 256) @@ -34,13 +34,13 @@ ; Function Attrs: nounwind readonly define i64 @lvsl_vssl_imm(i8* readonly %0, i32 signext %1) { ; CHECK-LABEL: lvsl_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: lvs %s0, %v0(%s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %4 = tail call i64 @llvm.ve.vl.lvsl.svs(<256 x double> %3, i32 %1) ret i64 %4 @@ -52,13 +52,13 @@ ; Function Attrs: nounwind readonly define double @lvsd_vssl_imm(i8* readonly %0, i32 signext %1) { ; CHECK-LABEL: lvsd_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: lvs %s0, %v0(%s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %4 = tail call fast double @llvm.ve.vl.lvsd.svs(<256 x double> %3, i32 %1) ret double %4 @@ -70,13 +70,13 @@ ; Function Attrs: nounwind readonly define float @lvss_vssl_imm(i8* readonly %0, i32 signext %1) { ; CHECK-LABEL: lvss_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: lvs %s0, %v0(%s0) -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %4 = tail call fast float @llvm.ve.vl.lvss.svs(<256 x double> %3, i32 %1) ret float %4 diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll b/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll --- a/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll +++ b/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll @@ -12,7 +12,7 @@ ; Function Attrs: nounwind define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) { ; CHECK-LABEL: switching_vl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s4, 256 ; CHECK-NEXT: lvl %s4 ; CHECK-NEXT: vld %v0, 8, %s2 @@ -29,7 +29,7 @@ ; CHECK-NEXT: vld %v0, 8, %s2 ; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: vst %v0, 16, %s3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 256) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl) %l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 128) @@ -46,7 +46,7 @@ ; Function Attrs: nounwind define void @stable_vl(i32 %evl, i8* %P, i8* %Q) { ; CHECK-LABEL: stable_vl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: vld %v0, 8, %s1 @@ -55,7 +55,7 @@ ; CHECK-NEXT: vst %v0, 16, %s2 ; CHECK-NEXT: vld %v0, 8, %s1 ; CHECK-NEXT: vst %v0, 16, %s2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl) %l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 %evl) diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll b/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll --- a/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll +++ b/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll @@ -8,11 +8,11 @@ ; Function Attrs: nounwind define void @pfchv_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: pfchv_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: pfchv %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256) ret void } @@ -23,11 +23,11 @@ ; Function Attrs: nounwind define void @pfchv_vssl_imm(i8* %0) { ; CHECK-LABEL: pfchv_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: pfchv 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256) ret void } @@ -35,11 +35,11 @@ ; Function Attrs: nounwind define void @pfchvnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: pfchvnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: pfchv.nc %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256) ret void } @@ -50,11 +50,11 @@ ; Function Attrs: nounwind define void @pfchvnc_vssl_imm(i8* %0) { ; CHECK-LABEL: pfchvnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: pfchv.nc 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256) ret void } diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll b/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll --- a/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll +++ b/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll @@ -8,14 +8,14 @@ ; Function Attrs: nounwind define void @vld_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vld_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -27,7 +27,7 @@ ; Function Attrs: nounwind define void @vld_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vld_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vld %v0, %s1, %s2 @@ -35,7 +35,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -48,14 +48,14 @@ ; Function Attrs: nounwind define void @vld_vssl_imm(i8* %0) { ; CHECK-LABEL: vld_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -64,7 +64,7 @@ ; Function Attrs: nounwind define void @vld_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vld_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, 8, %s1 @@ -72,7 +72,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -82,14 +82,14 @@ ; Function Attrs: nounwind define void @vldnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -101,7 +101,7 @@ ; Function Attrs: nounwind define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vld.nc %v0, %s1, %s2 @@ -109,7 +109,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -122,14 +122,14 @@ ; Function Attrs: nounwind define void @vldnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -138,7 +138,7 @@ ; Function Attrs: nounwind define void @vldnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld.nc %v0, 8, %s1 @@ -146,7 +146,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -156,14 +156,14 @@ ; Function Attrs: nounwind define void @vldu_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldu_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -175,7 +175,7 @@ ; Function Attrs: nounwind define void @vldu_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldu_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldu %v0, %s1, %s2 @@ -183,7 +183,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -196,14 +196,14 @@ ; Function Attrs: nounwind define void @vldu_vssl_imm(i8* %0) { ; CHECK-LABEL: vldu_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldu %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -212,7 +212,7 @@ ; Function Attrs: nounwind define void @vldu_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldu_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu %v0, 8, %s1 @@ -220,7 +220,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -230,14 +230,14 @@ ; Function Attrs: nounwind define void @vldunc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldunc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -249,7 +249,7 @@ ; Function Attrs: nounwind define void @vldunc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldunc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldu.nc %v0, %s1, %s2 @@ -257,7 +257,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -270,14 +270,14 @@ ; Function Attrs: nounwind define void @vldunc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldunc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldu.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -286,7 +286,7 @@ ; Function Attrs: nounwind define void @vldunc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldunc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu.nc %v0, 8, %s1 @@ -294,7 +294,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -304,14 +304,14 @@ ; Function Attrs: nounwind define void @vldlsx_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldlsx_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.sx %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -323,7 +323,7 @@ ; Function Attrs: nounwind define void @vldlsx_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldlsx_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl.sx %v0, %s1, %s2 @@ -331,7 +331,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -344,14 +344,14 @@ ; Function Attrs: nounwind define void @vldlsx_vssl_imm(i8* %0) { ; CHECK-LABEL: vldlsx_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl.sx %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -360,7 +360,7 @@ ; Function Attrs: nounwind define void @vldlsx_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldlsx_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.sx %v0, 8, %s1 @@ -368,7 +368,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -378,14 +378,14 @@ ; Function Attrs: nounwind define void @vldlsxnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldlsxnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -397,7 +397,7 @@ ; Function Attrs: nounwind define void @vldlsxnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldlsxnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s2 @@ -405,7 +405,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -418,14 +418,14 @@ ; Function Attrs: nounwind define void @vldlsxnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldlsxnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -434,7 +434,7 @@ ; Function Attrs: nounwind define void @vldlsxnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldlsxnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s1 @@ -442,7 +442,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -452,14 +452,14 @@ ; Function Attrs: nounwind define void @vldlzx_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldlzx_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.zx %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -471,7 +471,7 @@ ; Function Attrs: nounwind define void @vldlzx_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldlzx_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl.zx %v0, %s1, %s2 @@ -479,7 +479,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -492,14 +492,14 @@ ; Function Attrs: nounwind define void @vldlzx_vssl_imm(i8* %0) { ; CHECK-LABEL: vldlzx_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl.zx %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -508,7 +508,7 @@ ; Function Attrs: nounwind define void @vldlzx_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldlzx_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.zx %v0, 8, %s1 @@ -516,7 +516,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -526,14 +526,14 @@ ; Function Attrs: nounwind define void @vldlzxnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldlzxnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -545,7 +545,7 @@ ; Function Attrs: nounwind define void @vldlzxnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldlzxnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s2 @@ -553,7 +553,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -566,14 +566,14 @@ ; Function Attrs: nounwind define void @vldlzxnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldlzxnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -582,7 +582,7 @@ ; Function Attrs: nounwind define void @vldlzxnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldlzxnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s1 @@ -590,7 +590,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -600,14 +600,14 @@ ; Function Attrs: nounwind define void @vld2d_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vld2d_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld2d %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -619,7 +619,7 @@ ; Function Attrs: nounwind define void @vld2d_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vld2d_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vld2d %v0, %s1, %s2 @@ -627,7 +627,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -640,14 +640,14 @@ ; Function Attrs: nounwind define void @vld2d_vssl_imm(i8* %0) { ; CHECK-LABEL: vld2d_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld2d %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -656,7 +656,7 @@ ; Function Attrs: nounwind define void @vld2d_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vld2d_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld2d %v0, 8, %s1 @@ -664,7 +664,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -674,14 +674,14 @@ ; Function Attrs: nounwind define void @vld2dnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vld2dnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -693,7 +693,7 @@ ; Function Attrs: nounwind define void @vld2dnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vld2dnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s2 @@ -701,7 +701,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -714,14 +714,14 @@ ; Function Attrs: nounwind define void @vld2dnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vld2dnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld2d.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -730,7 +730,7 @@ ; Function Attrs: nounwind define void @vld2dnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vld2dnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld2d.nc %v0, 8, %s1 @@ -738,7 +738,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -748,14 +748,14 @@ ; Function Attrs: nounwind define void @vldu2d_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldu2d_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu2d %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -767,7 +767,7 @@ ; Function Attrs: nounwind define void @vldu2d_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldu2d_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldu2d %v0, %s1, %s2 @@ -775,7 +775,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -788,14 +788,14 @@ ; Function Attrs: nounwind define void @vldu2d_vssl_imm(i8* %0) { ; CHECK-LABEL: vldu2d_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldu2d %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -804,7 +804,7 @@ ; Function Attrs: nounwind define void @vldu2d_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldu2d_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu2d %v0, 8, %s1 @@ -812,7 +812,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -822,14 +822,14 @@ ; Function Attrs: nounwind define void @vldu2dnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldu2dnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -841,7 +841,7 @@ ; Function Attrs: nounwind define void @vldu2dnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldu2dnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s2 @@ -849,7 +849,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -862,14 +862,14 @@ ; Function Attrs: nounwind define void @vldu2dnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldu2dnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -878,7 +878,7 @@ ; Function Attrs: nounwind define void @vldu2dnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldu2dnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s1 @@ -886,7 +886,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -896,14 +896,14 @@ ; Function Attrs: nounwind define void @vldl2dsx_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldl2dsx_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -915,7 +915,7 @@ ; Function Attrs: nounwind define void @vldl2dsx_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldl2dsx_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s2 @@ -923,7 +923,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -936,14 +936,14 @@ ; Function Attrs: nounwind define void @vldl2dsx_vssl_imm(i8* %0) { ; CHECK-LABEL: vldl2dsx_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -952,7 +952,7 @@ ; Function Attrs: nounwind define void @vldl2dsx_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldl2dsx_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s1 @@ -960,7 +960,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -970,14 +970,14 @@ ; Function Attrs: nounwind define void @vldl2dsxnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldl2dsxnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -989,7 +989,7 @@ ; Function Attrs: nounwind define void @vldl2dsxnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldl2dsxnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s2 @@ -997,7 +997,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -1010,14 +1010,14 @@ ; Function Attrs: nounwind define void @vldl2dsxnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldl2dsxnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -1026,7 +1026,7 @@ ; Function Attrs: nounwind define void @vldl2dsxnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldl2dsxnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s1 @@ -1034,7 +1034,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -1044,14 +1044,14 @@ ; Function Attrs: nounwind define void @vldl2dzx_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldl2dzx_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -1063,7 +1063,7 @@ ; Function Attrs: nounwind define void @vldl2dzx_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldl2dzx_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s2 @@ -1071,7 +1071,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -1084,14 +1084,14 @@ ; Function Attrs: nounwind define void @vldl2dzx_vssl_imm(i8* %0) { ; CHECK-LABEL: vldl2dzx_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -1100,7 +1100,7 @@ ; Function Attrs: nounwind define void @vldl2dzx_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldl2dzx_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s1 @@ -1108,7 +1108,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) @@ -1118,14 +1118,14 @@ ; Function Attrs: nounwind define void @vldl2dzxnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vldl2dzxnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %0, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) ret void @@ -1137,7 +1137,7 @@ ; Function Attrs: nounwind define void @vldl2dzxnc_vssvl(i8* %0, i64 %1, i8* %2) { ; CHECK-LABEL: vldl2dzxnc_vssvl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s2 @@ -1145,7 +1145,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %2, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) @@ -1158,14 +1158,14 @@ ; Function Attrs: nounwind define void @vldl2dzxnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vldl2dzxnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0 ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %0, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) ret void @@ -1174,7 +1174,7 @@ ; Function Attrs: nounwind define void @vldl2dzxnc_vssvl_imm(i8* %0, i8* %1) { ; CHECK-LABEL: vldl2dzxnc_vssvl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s1 @@ -1182,7 +1182,7 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %1, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vst.ll b/llvm/test/CodeGen/VE/VELIntrinsics/vst.ll --- a/llvm/test/CodeGen/VE/VELIntrinsics/vst.ll +++ b/llvm/test/CodeGen/VE/VELIntrinsics/vst.ll @@ -8,12 +8,12 @@ ; Function Attrs: nounwind define void @vst_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vst_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -28,12 +28,12 @@ ; Function Attrs: nounwind define void @vst_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vst_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -45,12 +45,12 @@ ; Function Attrs: nounwind define void @vst_vssl_imm(i8* %0) { ; CHECK-LABEL: vst_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -59,12 +59,12 @@ ; Function Attrs: nounwind define void @vst_vssml_imm(i8* %0) { ; CHECK-LABEL: vst_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -73,12 +73,12 @@ ; Function Attrs: nounwind define void @vstnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst.nc %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -90,12 +90,12 @@ ; Function Attrs: nounwind define void @vstnc_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstnc_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst.nc %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -107,12 +107,12 @@ ; Function Attrs: nounwind define void @vstnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vstnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst.nc %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -121,12 +121,12 @@ ; Function Attrs: nounwind define void @vstnc_vssml_imm(i8* %0) { ; CHECK-LABEL: vstnc_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst.nc %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -135,12 +135,12 @@ ; Function Attrs: nounwind define void @vstot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -152,12 +152,12 @@ ; Function Attrs: nounwind define void @vstot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -169,12 +169,12 @@ ; Function Attrs: nounwind define void @vstot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -183,12 +183,12 @@ ; Function Attrs: nounwind define void @vstot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -197,12 +197,12 @@ ; Function Attrs: nounwind define void @vstncot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstncot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -214,12 +214,12 @@ ; Function Attrs: nounwind define void @vstncot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstncot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -231,12 +231,12 @@ ; Function Attrs: nounwind define void @vstncot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstncot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst.nc.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -245,12 +245,12 @@ ; Function Attrs: nounwind define void @vstncot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstncot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst.nc.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -259,12 +259,12 @@ ; Function Attrs: nounwind define void @vstu_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstu_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -276,12 +276,12 @@ ; Function Attrs: nounwind define void @vstu_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstu_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -293,12 +293,12 @@ ; Function Attrs: nounwind define void @vstu_vssl_imm(i8* %0) { ; CHECK-LABEL: vstu_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -307,12 +307,12 @@ ; Function Attrs: nounwind define void @vstu_vssml_imm(i8* %0) { ; CHECK-LABEL: vstu_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -321,12 +321,12 @@ ; Function Attrs: nounwind define void @vstunc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstunc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu.nc %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -338,12 +338,12 @@ ; Function Attrs: nounwind define void @vstunc_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstunc_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu.nc %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -355,12 +355,12 @@ ; Function Attrs: nounwind define void @vstunc_vssl_imm(i8* %0) { ; CHECK-LABEL: vstunc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu.nc %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -369,12 +369,12 @@ ; Function Attrs: nounwind define void @vstunc_vssml_imm(i8* %0) { ; CHECK-LABEL: vstunc_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu.nc %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -383,12 +383,12 @@ ; Function Attrs: nounwind define void @vstuot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstuot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -400,12 +400,12 @@ ; Function Attrs: nounwind define void @vstuot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstuot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -417,12 +417,12 @@ ; Function Attrs: nounwind define void @vstuot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstuot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -431,12 +431,12 @@ ; Function Attrs: nounwind define void @vstuot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstuot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -445,12 +445,12 @@ ; Function Attrs: nounwind define void @vstuncot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstuncot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -462,12 +462,12 @@ ; Function Attrs: nounwind define void @vstuncot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstuncot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -479,12 +479,12 @@ ; Function Attrs: nounwind define void @vstuncot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstuncot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -493,12 +493,12 @@ ; Function Attrs: nounwind define void @vstuncot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstuncot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -507,12 +507,12 @@ ; Function Attrs: nounwind define void @vstl_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstl_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -524,12 +524,12 @@ ; Function Attrs: nounwind define void @vstl_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstl_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -541,12 +541,12 @@ ; Function Attrs: nounwind define void @vstl_vssl_imm(i8* %0) { ; CHECK-LABEL: vstl_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -555,12 +555,12 @@ ; Function Attrs: nounwind define void @vstl_vssml_imm(i8* %0) { ; CHECK-LABEL: vstl_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -569,12 +569,12 @@ ; Function Attrs: nounwind define void @vstlnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstlnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl.nc %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -586,12 +586,12 @@ ; Function Attrs: nounwind define void @vstlnc_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstlnc_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl.nc %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -603,12 +603,12 @@ ; Function Attrs: nounwind define void @vstlnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vstlnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl.nc %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -617,12 +617,12 @@ ; Function Attrs: nounwind define void @vstlnc_vssml_imm(i8* %0) { ; CHECK-LABEL: vstlnc_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl.nc %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -631,12 +631,12 @@ ; Function Attrs: nounwind define void @vstlot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstlot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -648,12 +648,12 @@ ; Function Attrs: nounwind define void @vstlot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstlot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -665,12 +665,12 @@ ; Function Attrs: nounwind define void @vstlot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstlot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -679,12 +679,12 @@ ; Function Attrs: nounwind define void @vstlot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstlot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -693,12 +693,12 @@ ; Function Attrs: nounwind define void @vstlncot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstlncot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -710,12 +710,12 @@ ; Function Attrs: nounwind define void @vstlncot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstlncot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -727,12 +727,12 @@ ; Function Attrs: nounwind define void @vstlncot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstlncot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -741,12 +741,12 @@ ; Function Attrs: nounwind define void @vstlncot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstlncot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -755,12 +755,12 @@ ; Function Attrs: nounwind define void @vst2d_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vst2d_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -772,12 +772,12 @@ ; Function Attrs: nounwind define void @vst2d_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vst2d_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -789,12 +789,12 @@ ; Function Attrs: nounwind define void @vst2d_vssl_imm(i8* %0) { ; CHECK-LABEL: vst2d_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -803,12 +803,12 @@ ; Function Attrs: nounwind define void @vst2d_vssml_imm(i8* %0) { ; CHECK-LABEL: vst2d_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -817,12 +817,12 @@ ; Function Attrs: nounwind define void @vst2dnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vst2dnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d.nc %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -834,12 +834,12 @@ ; Function Attrs: nounwind define void @vst2dnc_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vst2dnc_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d.nc %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -851,12 +851,12 @@ ; Function Attrs: nounwind define void @vst2dnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vst2dnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d.nc %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -865,12 +865,12 @@ ; Function Attrs: nounwind define void @vst2dnc_vssml_imm(i8* %0) { ; CHECK-LABEL: vst2dnc_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d.nc %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -879,12 +879,12 @@ ; Function Attrs: nounwind define void @vst2dot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vst2dot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -896,12 +896,12 @@ ; Function Attrs: nounwind define void @vst2dot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vst2dot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -913,12 +913,12 @@ ; Function Attrs: nounwind define void @vst2dot_vssl_imm(i8* %0) { ; CHECK-LABEL: vst2dot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -927,12 +927,12 @@ ; Function Attrs: nounwind define void @vst2dot_vssml_imm(i8* %0) { ; CHECK-LABEL: vst2dot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -941,12 +941,12 @@ ; Function Attrs: nounwind define void @vst2dncot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vst2dncot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -958,12 +958,12 @@ ; Function Attrs: nounwind define void @vst2dncot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vst2dncot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -975,12 +975,12 @@ ; Function Attrs: nounwind define void @vst2dncot_vssl_imm(i8* %0) { ; CHECK-LABEL: vst2dncot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -989,12 +989,12 @@ ; Function Attrs: nounwind define void @vst2dncot_vssml_imm(i8* %0) { ; CHECK-LABEL: vst2dncot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1003,12 +1003,12 @@ ; Function Attrs: nounwind define void @vstu2d_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2d_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1020,12 +1020,12 @@ ; Function Attrs: nounwind define void @vstu2d_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2d_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1037,12 +1037,12 @@ ; Function Attrs: nounwind define void @vstu2d_vssl_imm(i8* %0) { ; CHECK-LABEL: vstu2d_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1051,12 +1051,12 @@ ; Function Attrs: nounwind define void @vstu2d_vssml_imm(i8* %0) { ; CHECK-LABEL: vstu2d_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1065,12 +1065,12 @@ ; Function Attrs: nounwind define void @vstu2dnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2dnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1082,12 +1082,12 @@ ; Function Attrs: nounwind define void @vstu2dnc_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2dnc_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1099,12 +1099,12 @@ ; Function Attrs: nounwind define void @vstu2dnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vstu2dnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d.nc %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1113,12 +1113,12 @@ ; Function Attrs: nounwind define void @vstu2dnc_vssml_imm(i8* %0) { ; CHECK-LABEL: vstu2dnc_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d.nc %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1127,12 +1127,12 @@ ; Function Attrs: nounwind define void @vstu2dot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2dot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1144,12 +1144,12 @@ ; Function Attrs: nounwind define void @vstu2dot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2dot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1161,12 +1161,12 @@ ; Function Attrs: nounwind define void @vstu2dot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstu2dot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1175,12 +1175,12 @@ ; Function Attrs: nounwind define void @vstu2dot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstu2dot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1189,12 +1189,12 @@ ; Function Attrs: nounwind define void @vstu2dncot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2dncot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1206,12 +1206,12 @@ ; Function Attrs: nounwind define void @vstu2dncot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstu2dncot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1223,12 +1223,12 @@ ; Function Attrs: nounwind define void @vstu2dncot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstu2dncot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1237,12 +1237,12 @@ ; Function Attrs: nounwind define void @vstu2dncot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstu2dncot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1251,12 +1251,12 @@ ; Function Attrs: nounwind define void @vstl2d_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2d_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1268,12 +1268,12 @@ ; Function Attrs: nounwind define void @vstl2d_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2d_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1285,12 +1285,12 @@ ; Function Attrs: nounwind define void @vstl2d_vssl_imm(i8* %0) { ; CHECK-LABEL: vstl2d_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1299,12 +1299,12 @@ ; Function Attrs: nounwind define void @vstl2d_vssml_imm(i8* %0) { ; CHECK-LABEL: vstl2d_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1313,12 +1313,12 @@ ; Function Attrs: nounwind define void @vstl2dnc_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2dnc_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1330,12 +1330,12 @@ ; Function Attrs: nounwind define void @vstl2dnc_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2dnc_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1347,12 +1347,12 @@ ; Function Attrs: nounwind define void @vstl2dnc_vssl_imm(i8* %0) { ; CHECK-LABEL: vstl2dnc_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d.nc %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1361,12 +1361,12 @@ ; Function Attrs: nounwind define void @vstl2dnc_vssml_imm(i8* %0) { ; CHECK-LABEL: vstl2dnc_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d.nc %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1375,12 +1375,12 @@ ; Function Attrs: nounwind define void @vstl2dot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2dot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1392,12 +1392,12 @@ ; Function Attrs: nounwind define void @vstl2dot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2dot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1409,12 +1409,12 @@ ; Function Attrs: nounwind define void @vstl2dot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstl2dot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1423,12 +1423,12 @@ ; Function Attrs: nounwind define void @vstl2dot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstl2dot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1437,12 +1437,12 @@ ; Function Attrs: nounwind define void @vstl2dncot_vssl(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2dncot_vssl: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) ret void @@ -1454,12 +1454,12 @@ ; Function Attrs: nounwind define void @vstl2dncot_vssml(i8* %0, i64 %1) { ; CHECK-LABEL: vstl2dncot_vssml: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) ret void @@ -1471,12 +1471,12 @@ ; Function Attrs: nounwind define void @vstl2dncot_vssl_imm(i8* %0) { ; CHECK-LABEL: vstl2dncot_vssl_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) ret void @@ -1485,12 +1485,12 @@ ; Function Attrs: nounwind define void @vstl2dncot_vssml_imm(i8* %0) { ; CHECK-LABEL: vstl2dncot_vssml_imm: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0, %vm0 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) ret void diff --git a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll --- a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll +++ b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll @@ -47,68 +47,68 @@ ; v0-to-v0 passthrough case without vreg copy. define fastcc <256 x i32> @vreg_arg_v256i32_r0(<256 x i32> %p0) { ; CHECK-LABEL: vreg_arg_v256i32_r0: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p0 } define fastcc <256 x i32> @vreg_arg_v256i32_r1(<256 x i32> %p0, <256 x i32> %p1) { ; CHECK-LABEL: vreg_arg_v256i32_r1: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s16, 256 ; CHECK-NEXT: lvl %s16 ; CHECK-NEXT: vor %v0, (0)1, %v1 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p1 } define fastcc <256 x i32> @vreg_arg_v256i32_r2(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2) { ; CHECK-LABEL: vreg_arg_v256i32_r2: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s16, 256 ; CHECK-NEXT: lvl %s16 ; CHECK-NEXT: vor %v0, (0)1, %v2 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p2 } define fastcc <256 x i32> @vreg_arg_v256i32_r3(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3) { ; CHECK-LABEL: vreg_arg_v256i32_r3: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s16, 256 ; CHECK-NEXT: lvl %s16 ; CHECK-NEXT: vor %v0, (0)1, %v3 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p3 } define fastcc <256 x i32> @vreg_arg_v256i32_r4(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4) { ; CHECK-LABEL: vreg_arg_v256i32_r4: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s16, 256 ; CHECK-NEXT: lvl %s16 ; CHECK-NEXT: vor %v0, (0)1, %v4 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p4 } define fastcc <256 x i32> @vreg_arg_v256i32_r5(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5) { ; CHECK-LABEL: vreg_arg_v256i32_r5: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s16, 256 ; CHECK-NEXT: lvl %s16 ; CHECK-NEXT: vor %v0, (0)1, %v5 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p5 } define fastcc <256 x i32> @vreg_arg_v256i32_r6(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6) { ; CHECK-LABEL: vreg_arg_v256i32_r6: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: ; CHECK-NEXT: lea %s16, 256 ; CHECK-NEXT: lvl %s16 ; CHECK-NEXT: vor %v0, (0)1, %v6 -; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: b.l.t (, %s10) ret <256 x i32> %p6 }