diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -34,6 +34,8 @@ [IntrArgMemOnly, NoCapture>, ImmArg>]>; def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>; def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>; + def int_ppc_dcbfps : Intrinsic<[], [llvm_ptr_ty], []>; + def int_ppc_dcbstps: Intrinsic<[], [llvm_ptr_ty], []>; // Population Count in each Byte. def int_ppc_popcntb : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>; diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -779,12 +779,18 @@ } case PPC::DCBFx: case PPC::DCBFL: - case PPC::DCBFLP: { + case PPC::DCBFLP: + case PPC::DCBFPS: + case PPC::DCBSTPS: { int L = 0; if (Opcode == PPC::DCBFL) L = 1; else if (Opcode == PPC::DCBFLP) L = 3; + else if (Opcode == PPC::DCBFPS) + L = 4; + else if (Opcode == PPC::DCBSTPS) + L = 6; MCInst TmpInst; TmpInst.setOpcode(PPC::DCBF); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -184,12 +184,18 @@ if (MI->getOpcode() == PPC::DCBF) { unsigned char L = MI->getOperand(0).getImm(); - if (!L || L == 1 || L == 3) { - O << "\tdcbf"; - if (L == 1 || L == 3) + if (!L || L == 1 || L == 3 || L == 4 || L == 6) { + O << "\tdcb"; + if (L != 6) + O << "f"; + if (L == 1) O << "l"; if (L == 3) - O << "p"; + O << "lp"; + if (L == 4) + O << "ps"; + if (L == 6) + O << "stps"; O << " "; printOperand(MI, 1, O); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -4573,6 +4573,16 @@ def : Pat<(int_ppc_dcbflp xoaddr:$dst), (DCBF 3, xoaddr:$dst)>; +let Predicates = [IsISA3_1] in { + def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; + def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; + + def : Pat<(int_ppc_dcbfps xoaddr:$dst), + (DCBF 4, xoaddr:$dst)>; + def : Pat<(int_ppc_dcbstps xoaddr:$dst), + (DCBF 6, xoaddr:$dst)>; +} + def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; diff --git a/llvm/test/CodeGen/PowerPC/dcbf-p10.ll b/llvm/test/CodeGen/PowerPC/dcbf-p10.ll --- a/llvm/test/CodeGen/PowerPC/dcbf-p10.ll +++ b/llvm/test/CodeGen/PowerPC/dcbf-p10.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \ +; RUN: -ppc-vsr-nums-as-vr -mcpu=pwr10 | FileCheck %s + +; Function Attrs: nounwind +define void @dcbfps_test(i8* %a) { +; CHECK-LABEL: dcbfps_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r3, r3, 3 +; CHECK-NEXT: dcbfps 0, r3 +; CHECK-NEXT: blr +entry: + %add.a = getelementptr inbounds i8, i8* %a, i64 3 + tail call void @llvm.ppc.dcbfps(i8* %add.a) +ret void +} + +declare void @llvm.ppc.dcbfps(i8*) + +; Function Attrs: nounwind +define void @dcbstps_test(i8* %a) { +; CHECK-LABEL: dcbstps_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r3, r3, 3 +; CHECK-NEXT: dcbstps 0, r3 +; CHECK-NEXT: blr +entry: + %add.a = getelementptr inbounds i8, i8* %a, i64 3 + tail call void @llvm.ppc.dcbstps(i8* %add.a) +ret void +} + +declare void @llvm.ppc.dcbstps(i8*)