diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8413,6 +8413,13 @@
   if (LD->getMemoryVT() != MemVT)
     return false;
 
+  // If the result of the load is an illegal type, then we can't build a
+  // valid chain for reuse since the legalised loads and token factor node that
+  // ties the legalised loads together uses a different output chain then the
+  // illegal load.
+  if (!isTypeLegal(LD->getValueType(0)))
+    return false;
+
   RLI.Ptr = LD->getBasePtr();
   if (LD->isIndexed() && !LD->getOffset().isUndef()) {
     assert(LD->getAddressingMode() == ISD::PRE_INC &&
diff --git a/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:  llc --verify-machineinstrs -mtriple powerpc-unknown-freebsd \
+; RUN:      -mcpu=pwr4 < %s | FileCheck %s
+
+define double @postinctodbl(i64* nocapture %llp) #0 {
+; CHECK-LABEL: postinctodbl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    lwz 4, 4(3)
+; CHECK-NEXT:    stw 4, 12(1)
+; CHECK-NEXT:    addic 4, 4, 1
+; CHECK-NEXT:    lwz 5, 0(3)
+; CHECK-NEXT:    stw 5, 8(1)
+; CHECK-NEXT:    addze 5, 5
+; CHECK-NEXT:    lfd 0, 8(1)
+; CHECK-NEXT:    stw 5, 0(3)
+; CHECK-NEXT:    fcfid 1, 0
+; CHECK-NEXT:    stw 4, 4(3)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i64, i64* %llp, align 8
+  %inc = add nsw i64 %0, 1
+  store i64 %inc, i64* %llp, align 8
+  %conv = sitofp i64 %0 to double
+  ret double %conv
+}