diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8350,6 +8350,13 @@
   if (LD->getMemoryVT() != MemVT)
     return false;
 
+  // If the result of the load is an illegal type, then we can't build a
+  // valid chain for reuse since the legalised loads and token factor node that
+  // ties the legalised loads together uses a different output chain then the
+  // illegal load.
+  if (!isTypeLegal(LD->getValueType(0)))
+    return false;
+
   RLI.Ptr = LD->getBasePtr();
   if (LD->isIndexed() && !LD->getOffset().isUndef()) {
     assert(LD->getAddressingMode() == ISD::PRE_INC &&
diff --git a/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
@@ -0,0 +1,30 @@
+; RUN:  llc  --verify-machineinstrs -mtriple powerpc-unknown-aix-xcoff \
+; RUN:       -mcpu=pwr4 < %s | FileCheck --check-prefix=AIX %s
+; RUN:  llc --verify-machineinstrs -mtriple powerpc-unknown-freebsd \
+; RUN:      -mcpu=pwr4 < %s | FileCheck --check-prefix=SVR4 %s
+
+define double @postinctodbl(i64* nocapture %llp) #0 {
+entry:
+  %0 = load i64, i64* %llp, align 8
+  %inc = add nsw i64 %0, 1
+  store i64 %inc, i64* %llp, align 8
+  %conv = sitofp i64 %0 to double
+  ret double %conv
+}
+
+; AIX-LABEL: .postinctodbl:
+; AIX:  lwz [[MSW:[0-9]+]], 4(3)
+; AIX:  stw [[MSW]], -4(1)
+; AIX:  lwz [[LSW:[0-9]+]], 0(3)
+; AIX:  stw [[LSW]], -8(1)
+; AIX:  lfd [[FPR:[0-9]+]], -8(1)
+; AIX:  fcfid 1, [[FPR]]
+
+; SVR4-LABEL: postinctodbl
+; SVR4:  stwu 1, -16(1)
+; SVR4:  lwz [[MSW:[0-9]+]], 4(3)
+; SVR4:  stw [[MSW]], 12(1)
+; SVR4:  lwz [[LSW:[0-9]+]], 0(3)
+; SVR4:  stw [[LSW]], 8(1)
+; SVR4:  lfd [[FPR:[0-9]+]], 8(1)
+; SVR4:  fcfid 1, [[FPR]]