diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt --- a/llvm/lib/Target/PowerPC/CMakeLists.txt +++ b/llvm/lib/Target/PowerPC/CMakeLists.txt @@ -26,6 +26,7 @@ PPCBranchCoalescing.cpp PPCCallingConv.cpp PPCCCState.cpp + PPCConstantPoolValue.cpp PPCCTRLoops.cpp PPCHazardRecognizers.cpp PPCInstrInfo.cpp @@ -41,6 +42,7 @@ PPCMacroFusion.cpp PPCMIPeephole.cpp PPCRegisterInfo.cpp + PPCSelectionDAGInfo.cpp PPCSubtarget.cpp PPCTargetMachine.cpp PPCTargetObjectFile.cpp diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -20,6 +20,7 @@ #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCPredicates.h" #include "PPC.h" +#include "PPCConstantPoolValue.h" #include "PPCInstrInfo.h" #include "PPCMachineFunctionInfo.h" #include "PPCSubtarget.h" @@ -138,6 +139,7 @@ return "Linux PPC Assembly Printer"; } + void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; void emitStartOfAsmFile(Module &M) override; void emitEndOfAsmFile(Module &) override; @@ -888,7 +890,8 @@ const bool GlobalToc = MO.isGlobal() && Subtarget->isGVIndirectSymbol(MO.getGlobal()); if (GlobalToc || MO.isJTI() || MO.isBlockAddress() || - (MO.isCPI() && TM.getCodeModel() == CodeModel::Large)) + (MO.isCPI() && ((MO.getTargetFlags() & PPCII::MO_GOT_FLAG) || + TM.getCodeModel() == CodeModel::Large))) MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); const MCSymbolRefExpr::VariantKind VK = @@ -929,7 +932,8 @@ const MCSymbol *MOSymbol = getMCSymbolForTOCPseudoMO(MO, *this); - if (!MO.isCPI() || TM.getCodeModel() == CodeModel::Large) + if (!MO.isCPI() || (MO.getTargetFlags() & PPCII::MO_GOT_FLAG) || + TM.getCodeModel() == CodeModel::Large) MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); const MCSymbolRefExpr::VariantKind VK = @@ -1519,6 +1523,14 @@ PPCAsmPrinter::emitEndOfAsmFile(M); } +void PPCLinuxAsmPrinter::emitMachineConstantPoolValue( + MachineConstantPoolValue *MCPV) { + PPCConstantPoolValue *PCPV = static_cast(MCPV); + const DataLayout &DL = getDataLayout(); + for (const auto *C : PCPV->getConstants()) + emitGlobalConstant(DL, C); +} + /// EmitFunctionBodyStart - Emit a global entry point prefix for ELFv2. void PPCLinuxAsmPrinter::emitFunctionBodyStart() { // In the ELFv2 ABI, in functions that use the TOC register, we need to diff --git a/llvm/lib/Target/PowerPC/PPCConstantPoolValue.h b/llvm/lib/Target/PowerPC/PPCConstantPoolValue.h new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/PowerPC/PPCConstantPoolValue.h @@ -0,0 +1,50 @@ +//===- PPCConstantPoolValue.h - PPC constantpool value ----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the PowerPC specific constantpool value class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_PPC_PPCCONSTANTPOOLVALUE_H +#define LLVM_LIB_TARGET_PPC_PPCCONSTANTPOOLVALUE_H + +#include "llvm/CodeGen/MachineConstantPool.h" + +namespace llvm { +class ConstantFP; +class PPCConstantPoolValue : public MachineConstantPoolValue { + // Lump all the constants into the same constant pool if they have the + // same type. + SmallVector ConstantValues; + +public: + PPCConstantPoolValue(Type *Ty); + + const SmallVector &getConstants() const { + return ConstantValues; + } + + unsigned getSizeInBytes(const DataLayout &DL) const override; + + /// Create a new entry in the constant pool or return an existing one for the + /// constant. + unsigned getConstantIndex(const Constant *C); + + static PPCConstantPoolValue *Create(Type *Ty); + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// print - Implement operator<< + void print(raw_ostream &O) const override; +}; + +} // end namespace llvm +#endif // LLVM_LIB_TARGET_PPC_PPCCONSTANTPOOLVALUE_H diff --git a/llvm/lib/Target/PowerPC/PPCConstantPoolValue.cpp b/llvm/lib/Target/PowerPC/PPCConstantPoolValue.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/PowerPC/PPCConstantPoolValue.cpp @@ -0,0 +1,61 @@ +//===- PPCConstantPoolValue.cpp - PPC constantpool value ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the PowerPC specific constantpool value class. +// +//===----------------------------------------------------------------------===// + +#include "PPCConstantPoolValue.h" +#include "llvm/ADT/FoldingSet.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Support/Debug.h" + +using namespace llvm; + +PPCConstantPoolValue::PPCConstantPoolValue(Type *Ty) + : MachineConstantPoolValue(Ty) {} + +PPCConstantPoolValue *PPCConstantPoolValue::Create(Type *Ty) { + return new PPCConstantPoolValue(Ty); +} + +unsigned PPCConstantPoolValue::getSizeInBytes(const DataLayout &DL) const { + return DL.getTypeAllocSize(getType()) * ConstantValues.size(); +} + +unsigned PPCConstantPoolValue::getConstantIndex(const Constant *C) { + for (unsigned I = 0, E = ConstantValues.size(); I != E; ++I) + if (ConstantValues[I] == C) + return I; + ConstantValues.push_back(C); + return ConstantValues.size() - 1; +} + +int PPCConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + const std::vector &Constants = CP->getConstants(); + for (unsigned I = 0, E = Constants.size(); I != E; ++I) { + if (Constants[I].isMachineConstantPoolEntry() && + Constants[I].getAlign() >= Alignment) { + auto *PCPV = + static_cast(Constants[I].Val.MachineCPVal); + if (PCPV->getType() == getType()) + return I; + } + } + return -1; +} + +void PPCConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddPointer(getType()); +} + +void PPCConstantPoolValue::print(raw_ostream &O) const { + O << ConstantValues.size() << " x " << *getType(); +} diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -6762,9 +6762,15 @@ ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, Offset, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast(ImmOpnd)) { - const Constant *C = CP->getConstVal(); - ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlign(), - Offset, Flags); + if (CP->isMachineConstantPoolEntry()) { + MachineConstantPoolValue *V = CP->getMachineCPVal(); + ImmOpnd = CurDAG->getTargetConstantPool(V, MVT::i64, CP->getAlign(), + Offset, Flags); + } else { + const Constant *C = CP->getConstVal(); + ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlign(), + Offset, Flags); + } } } diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -15,6 +15,7 @@ #include "PPC.h" #include "PPCCCState.h" #include "PPCCallingConv.h" +#include "PPCConstantPoolValue.h" #include "PPCFrameLowering.h" #include "PPCInstrInfo.h" #include "PPCMachineFunctionInfo.h" @@ -1645,8 +1646,9 @@ else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { // Maybe this has already been legalized into the constant pool? if (ConstantPoolSDNode *CP = dyn_cast(Op.getOperand(1))) - if (const ConstantFP *CFP = dyn_cast(CP->getConstVal())) - return CFP->getValueAPF().isZero(); + if (!CP->isMachineConstantPoolEntry()) + if (const ConstantFP *CFP = dyn_cast(CP->getConstVal())) + return CFP->getValueAPF().isZero(); } return false; } @@ -2980,6 +2982,14 @@ SelectionDAG &DAG) const { EVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); + if (CP->isMachineConstantPoolEntry()) { + unsigned TargetFlags = isAccessedAsGotIndirect(Op) ? PPCII::MO_GOT_FLAG : 0; + SDValue GA = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, + CP->getAlign(), 0, TargetFlags); + setUsesTOCBasePtr(DAG); + return getTOCEntry(DAG, SDLoc(CP), GA); + } + const Constant *C = CP->getConstVal(); // 64-bit SVR4 ABI and AIX ABI code are always position-independent. @@ -16039,6 +16049,11 @@ if (isa(GA) || isa(GA)) return true; + // Constant is accessed as got-indirect if it is lumped. + if (ConstantPoolSDNode *CPN = dyn_cast(GA)) + if (CPN->isMachineConstantPoolEntry()) + return true; + if (GlobalAddressSDNode *G = dyn_cast(GA)) return Subtarget.isGVIndirectSymbol(G->getGlobal()); diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h @@ -0,0 +1,33 @@ +//===-- PPCSelectionDAGInfo.h - PPC SelectionDAG Info -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the PPC subclass for SelectionDAGTargetInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_PPC_PPCSELECTIONDAGINFO_H +#define LLVM_LIB_TARGET_PPC_PPCSELECTIONDAGINFO_H + +#include "llvm/CodeGen/SelectionDAGTargetInfo.h" + +namespace llvm { + +class PPCSelectionDAGInfo : public SelectionDAGTargetInfo { +public: + explicit PPCSelectionDAGInfo() = default; + + SDValue EmitTargetCodeForConstantPool(SelectionDAG &DAG, const Constant *C, + EVT VT, Align Alignment, + Align &NewAlign, int Offset, + bool isTarget, + unsigned TargetFlags) const override; +}; + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_PPC_PPCSELECTIONDAGINFO_H diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp @@ -0,0 +1,74 @@ +//===-- PPCSelectionDAGInfo.cpp - PPC SelectionDAG Info -------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the PPCSelectionDAGInfo class. +// +//===----------------------------------------------------------------------===// + +#include "PPCSelectionDAGInfo.h" +#include "PPCConstantPoolValue.h" +#include "PPCSubtarget.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/Support/CommandLine.h" + +using namespace llvm; + +#define DEBUG_TYPE "ppc-selectiondag-info" + +static cl::opt + ConstantLump("ppc-const-lump", + cl::desc("enable/disable constant lump on ppc"), cl::Hidden, + cl::init(true)); +STATISTIC(NumConstantLump, "Number of constant lumped"); + +SDValue PPCSelectionDAGInfo::EmitTargetCodeForConstantPool( + SelectionDAG &DAG, const Constant *C, EVT VT, Align Alignment, + Align &NewAlign, int Offset, bool isTarget, unsigned TargetFlags) const { + const PPCSubtarget &Subtarget = + DAG.getMachineFunction().getSubtarget(); + + // Lump the constant pool for each function into ONE pic object, and reference + // pieces of it as offsets from the start. Only do it for 64bit ELF ABI. And + // we won't get benefit if PCREL is enabled. + if (!Subtarget.is64BitELFABI() || Subtarget.isUsingPCRelativeCalls() || + !ConstantLump) + return SDValue(); + + // The liveness of MachineConstantPoolValue is per function. We need to query + // the right constant pool value from MachineConstantPool. + MachineConstantPool *MCP = DAG.getMachineFunction().getConstantPool(); + unsigned CPIdx = MCP->getConstantPoolIndex( + PPCConstantPoolValue::Create(C->getType()), + DAG.getDataLayout().getPrefTypeAlign(C->getType())); + PPCConstantPoolValue *GAVal = static_cast( + MCP->getConstants()[CPIdx].Val.MachineCPVal); + + // Lump each constant into one constant pool if they have the same type. + SDValue GA = + DAG.getConstantPool(GAVal, VT, Alignment, Offset, isTarget, TargetFlags); + // TODO - Don't assume that GA must be ConstantPoolSDNode. + NewAlign = std::max(Alignment, cast(GA)->getAlign()); + + // Get the offset from the constant pool and give up if it is not 16-bit as + // we won't have benefit if the offset doesn't fit the D-Form load imm field. + unsigned OffsetInsideCP = GAVal->getConstantIndex(C) * NewAlign.value(); + if (!isInt<16>(OffsetInsideCP)) + return SDValue(); + + if (OffsetInsideCP) + ++NumConstantLump; + + // The address of the constant is the sum of constant pool and the offset + // inside it. + SDLoc Loc(GA); + return DAG.getNode( + ISD::ADD, Loc, GA->getValueType(0), GA, + DAG.getConstant(OffsetInsideCP, Loc, + Subtarget.isPPC64() ? MVT::i64 : MVT::i32)); +} diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -16,6 +16,7 @@ #include "PPCFrameLowering.h" #include "PPCISelLowering.h" #include "PPCInstrInfo.h" +#include "PPCSelectionDAGInfo.h" #include "llvm/ADT/Triple.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" @@ -159,7 +160,7 @@ PPCFrameLowering FrameLowering; PPCInstrInfo InstrInfo; PPCTargetLowering TLInfo; - SelectionDAGTargetInfo TSInfo; + PPCSelectionDAGInfo TSInfo; /// GlobalISel related APIs. std::unique_ptr CallLoweringInfo; diff --git a/llvm/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll b/llvm/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll --- a/llvm/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll +++ b/llvm/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -code-model=small < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -ppc-const-lump=false -code-model=small < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll --- a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll +++ b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll @@ -11,11 +11,11 @@ ; CHECK-NEXT: cmplwi 6, 0 ; CHECK-NEXT: beq 0, .LBB0_2 ; CHECK-NEXT: # %bb.1: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: xxlxor 2, 2, 2 -; CHECK-NEXT: lfd 1, .LCPI0_0@toc@l(3) -; CHECK-NEXT: lfd 3, .LCPI0_1@toc@l(4) +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: lfd 1, 8(3) +; CHECK-NEXT: lfdx 3, 0, 3 ; CHECK-NEXT: .LBB0_2: # %entry ; CHECK-NEXT: xsadddp 0, 1, 2 ; CHECK-NEXT: xsadddp 1, 0, 3 @@ -23,22 +23,22 @@ ; ; CHECK-NOCOALESCE-LABEL: testBranchCoal: ; CHECK-NOCOALESCE: # %bb.0: # %entry +; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0 +; CHECK-NOCOALESCE-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5 ; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6 ; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry ; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4 ; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry -; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha -; CHECK-NOCOALESCE-NEXT: lfd 3, .LCPI0_1@toc@l(3) +; CHECK-NOCOALESCE-NEXT: lfdx 3, 0, 3 ; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry ; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2 ; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3 ; CHECK-NOCOALESCE-NEXT: blr ; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry -; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-NOCOALESCE-NEXT: lfd 1, .LCPI0_0@toc@l(3) +; CHECK-NOCOALESCE-NEXT: lfd 1, 8(3) ; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2 ; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry ; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2 diff --git a/llvm/test/CodeGen/PowerPC/build-vector-allones.ll b/llvm/test/CodeGen/PowerPC/build-vector-allones.ll --- a/llvm/test/CodeGen/PowerPC/build-vector-allones.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-allones.ll @@ -33,8 +33,8 @@ define <2 x i64> @One2i64() { ; P7BE-LABEL: One2i64: ; P7BE: # %bb.0: # %entry -; P7BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; P7BE-NEXT: addi r3, r3, .LCPI1_0@toc@l +; P7BE-NEXT: addis r3, r2, .LC0@toc@ha +; P7BE-NEXT: ld r3, .LC0@toc@l(r3) ; P7BE-NEXT: lxvd2x vs34, 0, r3 ; P7BE-NEXT: blr ; diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll --- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll @@ -856,29 +856,29 @@ define <4 x i32> @fromDiffConstsi() { ; P9BE-LABEL: fromDiffConstsi: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC0@toc@ha +; P9BE-NEXT: ld r3, .LC0@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsi: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC0@toc@ha +; P9LE-NEXT: ld r3, .LC0@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsi: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC0@toc@ha +; P8BE-NEXT: ld r3, .LC0@toc@l(r3) ; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsi: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC0@toc@ha +; P8LE-NEXT: ld r3, .LC0@toc@l(r3) ; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: blr entry: @@ -925,8 +925,8 @@ ; P9BE-LABEL: fromDiffMemConsDi: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: lxv v2, 0(r3) -; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC1@toc@ha +; P9BE-NEXT: ld r3, .LC1@toc@l(r3) ; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr @@ -938,20 +938,20 @@ ; ; P8BE-LABEL: fromDiffMemConsDi: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha +; P8BE-NEXT: addis r4, r2, .LC1@toc@ha ; P8BE-NEXT: lxvw4x v2, 0, r3 -; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l +; P8BE-NEXT: ld r4, .LC1@toc@l(r4) ; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffMemConsDi: ; P8LE: # %bb.0: # %entry +; P8LE-NEXT: addis r4, r2, .LC1@toc@ha ; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha -; P8LE-NEXT: addi r3, r4, .LCPI7_0@toc@l -; P8LE-NEXT: lvx v2, 0, r3 +; P8LE-NEXT: ld r4, .LC1@toc@l(r4) ; P8LE-NEXT: xxswapd v3, vs0 +; P8LE-NEXT: lvx v2, 0, r4 ; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: blr entry: @@ -1024,8 +1024,8 @@ ; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: addi r3, r3, -12 ; P9BE-NEXT: lxvx v2, 0, r3 -; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC2@toc@ha +; P9BE-NEXT: ld r3, .LC2@toc@l(r3) ; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr @@ -1036,34 +1036,34 @@ ; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: addi r3, r3, -12 ; P9LE-NEXT: lxvx v2, 0, r3 -; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC1@toc@ha +; P9LE-NEXT: ld r3, .LC1@toc@l(r3) ; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffMemVarDi: ; P8BE: # %bb.0: # %entry +; P8BE-NEXT: addis r5, r2, .LC2@toc@ha ; P8BE-NEXT: sldi r4, r4, 2 -; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha +; P8BE-NEXT: ld r5, .LC2@toc@l(r5) ; P8BE-NEXT: add r3, r3, r4 -; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l ; P8BE-NEXT: addi r3, r3, -12 -; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v2, 0, r3 +; P8BE-NEXT: lxvw4x v3, 0, r5 ; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffMemVarDi: ; P8LE: # %bb.0: # %entry ; P8LE-NEXT: sldi r4, r4, 2 -; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha +; P8LE-NEXT: addis r5, r2, .LC2@toc@ha ; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: addi r3, r3, -12 ; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: addi r3, r5, .LCPI9_0@toc@l -; P8LE-NEXT: lvx v3, 0, r3 +; P8LE-NEXT: ld r3, .LC2@toc@l(r5) ; P8LE-NEXT: xxswapd v2, vs0 +; P8LE-NEXT: lvx v3, 0, r3 ; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: blr entry: @@ -1382,29 +1382,29 @@ define <4 x i32> @fromDiffConstsConvftoi() { ; P9BE-LABEL: fromDiffConstsConvftoi: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC3@toc@ha +; P9BE-NEXT: ld r3, .LC3@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoi: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC2@toc@ha +; P9LE-NEXT: ld r3, .LC2@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoi: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC3@toc@ha +; P8BE-NEXT: ld r3, .LC3@toc@l(r3) ; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvftoi: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC3@toc@ha +; P8LE-NEXT: ld r3, .LC3@toc@l(r3) ; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: blr entry: @@ -1447,8 +1447,8 @@ ; P9BE-LABEL: fromDiffMemConsDConvftoi: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: lxv v2, 0(r3) -; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC4@toc@ha +; P9BE-NEXT: ld r3, .LC4@toc@l(r3) ; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: xvcvspsxws v2, v2 @@ -1457,8 +1457,8 @@ ; P9LE-LABEL: fromDiffMemConsDConvftoi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: lxv v2, 0(r3) -; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC3@toc@ha +; P9LE-NEXT: ld r3, .LC3@toc@l(r3) ; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: xvcvspsxws v2, v2 @@ -1466,9 +1466,9 @@ ; ; P8BE-LABEL: fromDiffMemConsDConvftoi: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha +; P8BE-NEXT: addis r4, r2, .LC4@toc@ha ; P8BE-NEXT: lxvw4x v2, 0, r3 -; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l +; P8BE-NEXT: ld r4, .LC4@toc@l(r4) ; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: xvcvspsxws v2, v2 @@ -1476,11 +1476,11 @@ ; ; P8LE-LABEL: fromDiffMemConsDConvftoi: ; P8LE: # %bb.0: # %entry +; P8LE-NEXT: addis r4, r2, .LC4@toc@ha ; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha -; P8LE-NEXT: addi r3, r4, .LCPI18_0@toc@l -; P8LE-NEXT: lvx v2, 0, r3 +; P8LE-NEXT: ld r4, .LC4@toc@l(r4) ; P8LE-NEXT: xxswapd v3, vs0 +; P8LE-NEXT: lvx v2, 0, r4 ; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: xvcvspsxws v2, v2 ; P8LE-NEXT: blr @@ -1834,29 +1834,29 @@ define <4 x i32> @fromDiffConstsConvdtoi() { ; P9BE-LABEL: fromDiffConstsConvdtoi: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC5@toc@ha +; P9BE-NEXT: ld r3, .LC5@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoi: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC4@toc@ha +; P9LE-NEXT: ld r3, .LC4@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoi: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC5@toc@ha +; P8BE-NEXT: ld r3, .LC5@toc@l(r3) ; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvdtoi: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC5@toc@ha +; P8LE-NEXT: ld r3, .LC5@toc@l(r3) ; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: blr entry: @@ -2374,29 +2374,29 @@ define <4 x i32> @fromDiffConstsui() { ; P9BE-LABEL: fromDiffConstsui: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC6@toc@ha +; P9BE-NEXT: ld r3, .LC6@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsui: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC5@toc@ha +; P9LE-NEXT: ld r3, .LC5@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsui: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC6@toc@ha +; P8BE-NEXT: ld r3, .LC6@toc@l(r3) ; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsui: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC6@toc@ha +; P8LE-NEXT: ld r3, .LC6@toc@l(r3) ; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: blr entry: @@ -2443,8 +2443,8 @@ ; P9BE-LABEL: fromDiffMemConsDui: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: lxv v2, 0(r3) -; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC7@toc@ha +; P9BE-NEXT: ld r3, .LC7@toc@l(r3) ; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr @@ -2456,20 +2456,20 @@ ; ; P8BE-LABEL: fromDiffMemConsDui: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha +; P8BE-NEXT: addis r4, r2, .LC7@toc@ha ; P8BE-NEXT: lxvw4x v2, 0, r3 -; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l +; P8BE-NEXT: ld r4, .LC7@toc@l(r4) ; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffMemConsDui: ; P8LE: # %bb.0: # %entry +; P8LE-NEXT: addis r4, r2, .LC7@toc@ha ; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha -; P8LE-NEXT: addi r3, r4, .LCPI39_0@toc@l -; P8LE-NEXT: lvx v2, 0, r3 +; P8LE-NEXT: ld r4, .LC7@toc@l(r4) ; P8LE-NEXT: xxswapd v3, vs0 +; P8LE-NEXT: lvx v2, 0, r4 ; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: blr entry: @@ -2542,8 +2542,8 @@ ; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: addi r3, r3, -12 ; P9BE-NEXT: lxvx v2, 0, r3 -; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC8@toc@ha +; P9BE-NEXT: ld r3, .LC8@toc@l(r3) ; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr @@ -2554,34 +2554,34 @@ ; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: addi r3, r3, -12 ; P9LE-NEXT: lxvx v2, 0, r3 -; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC6@toc@ha +; P9LE-NEXT: ld r3, .LC6@toc@l(r3) ; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffMemVarDui: ; P8BE: # %bb.0: # %entry +; P8BE-NEXT: addis r5, r2, .LC8@toc@ha ; P8BE-NEXT: sldi r4, r4, 2 -; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha +; P8BE-NEXT: ld r5, .LC8@toc@l(r5) ; P8BE-NEXT: add r3, r3, r4 -; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l ; P8BE-NEXT: addi r3, r3, -12 -; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v2, 0, r3 +; P8BE-NEXT: lxvw4x v3, 0, r5 ; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffMemVarDui: ; P8LE: # %bb.0: # %entry ; P8LE-NEXT: sldi r4, r4, 2 -; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha +; P8LE-NEXT: addis r5, r2, .LC8@toc@ha ; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: addi r3, r3, -12 ; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: addi r3, r5, .LCPI41_0@toc@l -; P8LE-NEXT: lvx v3, 0, r3 +; P8LE-NEXT: ld r3, .LC8@toc@l(r5) ; P8LE-NEXT: xxswapd v2, vs0 +; P8LE-NEXT: lvx v3, 0, r3 ; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: blr entry: @@ -2900,29 +2900,29 @@ define <4 x i32> @fromDiffConstsConvftoui() { ; P9BE-LABEL: fromDiffConstsConvftoui: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC9@toc@ha +; P9BE-NEXT: ld r3, .LC9@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoui: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC7@toc@ha +; P9LE-NEXT: ld r3, .LC7@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoui: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC9@toc@ha +; P8BE-NEXT: ld r3, .LC9@toc@l(r3) ; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvftoui: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC9@toc@ha +; P8LE-NEXT: ld r3, .LC9@toc@l(r3) ; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: blr entry: @@ -2965,8 +2965,8 @@ ; P9BE-LABEL: fromDiffMemConsDConvftoui: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: lxv v2, 0(r3) -; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC10@toc@ha +; P9BE-NEXT: ld r3, .LC10@toc@l(r3) ; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: xvcvspuxws v2, v2 @@ -2975,8 +2975,8 @@ ; P9LE-LABEL: fromDiffMemConsDConvftoui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: lxv v2, 0(r3) -; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC8@toc@ha +; P9LE-NEXT: ld r3, .LC8@toc@l(r3) ; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: xvcvspuxws v2, v2 @@ -2984,9 +2984,9 @@ ; ; P8BE-LABEL: fromDiffMemConsDConvftoui: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha +; P8BE-NEXT: addis r4, r2, .LC10@toc@ha ; P8BE-NEXT: lxvw4x v2, 0, r3 -; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l +; P8BE-NEXT: ld r4, .LC10@toc@l(r4) ; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: xvcvspuxws v2, v2 @@ -2994,11 +2994,11 @@ ; ; P8LE-LABEL: fromDiffMemConsDConvftoui: ; P8LE: # %bb.0: # %entry +; P8LE-NEXT: addis r4, r2, .LC10@toc@ha ; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha -; P8LE-NEXT: addi r3, r4, .LCPI50_0@toc@l -; P8LE-NEXT: lvx v2, 0, r3 +; P8LE-NEXT: ld r4, .LC10@toc@l(r4) ; P8LE-NEXT: xxswapd v3, vs0 +; P8LE-NEXT: lvx v2, 0, r4 ; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: xvcvspuxws v2, v2 ; P8LE-NEXT: blr @@ -3353,29 +3353,29 @@ define <4 x i32> @fromDiffConstsConvdtoui() { ; P9BE-LABEL: fromDiffConstsConvdtoui: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC11@toc@ha +; P9BE-NEXT: ld r3, .LC11@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoui: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC9@toc@ha +; P9LE-NEXT: ld r3, .LC9@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoui: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC11@toc@ha +; P8BE-NEXT: ld r3, .LC11@toc@l(r3) ; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvdtoui: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC11@toc@ha +; P8LE-NEXT: ld r3, .LC11@toc@l(r3) ; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: blr entry: @@ -3773,29 +3773,29 @@ define <2 x i64> @spltConst1ll() { ; P9BE-LABEL: spltConst1ll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC12@toc@ha +; P9BE-NEXT: ld r3, .LC12@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst1ll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC10@toc@ha +; P9LE-NEXT: ld r3, .LC10@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst1ll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC12@toc@ha +; P8BE-NEXT: ld r3, .LC12@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltConst1ll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC12@toc@ha +; P8LE-NEXT: ld r3, .LC12@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -3806,29 +3806,29 @@ define <2 x i64> @spltConst16kll() { ; P9BE-LABEL: spltConst16kll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC13@toc@ha +; P9BE-NEXT: ld r3, .LC13@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst16kll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC11@toc@ha +; P9LE-NEXT: ld r3, .LC11@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst16kll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC13@toc@ha +; P8BE-NEXT: ld r3, .LC13@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltConst16kll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC13@toc@ha +; P8LE-NEXT: ld r3, .LC13@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -3839,29 +3839,29 @@ define <2 x i64> @spltConst32kll() { ; P9BE-LABEL: spltConst32kll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC14@toc@ha +; P9BE-NEXT: ld r3, .LC14@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst32kll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC12@toc@ha +; P9LE-NEXT: ld r3, .LC12@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst32kll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC14@toc@ha +; P8BE-NEXT: ld r3, .LC14@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltConst32kll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC14@toc@ha +; P8LE-NEXT: ld r3, .LC14@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -3902,29 +3902,29 @@ define <2 x i64> @fromDiffConstsll() { ; P9BE-LABEL: fromDiffConstsll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC15@toc@ha +; P9BE-NEXT: ld r3, .LC15@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC13@toc@ha +; P9LE-NEXT: ld r3, .LC13@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC15@toc@ha +; P8BE-NEXT: ld r3, .LC15@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC15@toc@ha +; P8LE-NEXT: ld r3, .LC15@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -4236,29 +4236,29 @@ define <2 x i64> @spltCnstConvftoll() { ; P9BE-LABEL: spltCnstConvftoll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC16@toc@ha +; P9BE-NEXT: ld r3, .LC16@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvftoll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC14@toc@ha +; P9LE-NEXT: ld r3, .LC14@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvftoll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC16@toc@ha +; P8BE-NEXT: ld r3, .LC16@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltCnstConvftoll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC16@toc@ha +; P8LE-NEXT: ld r3, .LC16@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -4309,29 +4309,29 @@ define <2 x i64> @fromDiffConstsConvftoll() { ; P9BE-LABEL: fromDiffConstsConvftoll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC17@toc@ha +; P9BE-NEXT: ld r3, .LC17@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC15@toc@ha +; P9LE-NEXT: ld r3, .LC15@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC17@toc@ha +; P8BE-NEXT: ld r3, .LC17@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvftoll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC17@toc@ha +; P8LE-NEXT: ld r3, .LC17@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -4598,29 +4598,29 @@ define <2 x i64> @spltCnstConvdtoll() { ; P9BE-LABEL: spltCnstConvdtoll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC18@toc@ha +; P9BE-NEXT: ld r3, .LC18@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvdtoll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC16@toc@ha +; P9LE-NEXT: ld r3, .LC16@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvdtoll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC18@toc@ha +; P8BE-NEXT: ld r3, .LC18@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltCnstConvdtoll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC18@toc@ha +; P8LE-NEXT: ld r3, .LC18@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -4671,29 +4671,29 @@ define <2 x i64> @fromDiffConstsConvdtoll() { ; P9BE-LABEL: fromDiffConstsConvdtoll: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC19@toc@ha +; P9BE-NEXT: ld r3, .LC19@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoll: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC17@toc@ha +; P9LE-NEXT: ld r3, .LC17@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC19@toc@ha +; P8BE-NEXT: ld r3, .LC19@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvdtoll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC19@toc@ha +; P8LE-NEXT: ld r3, .LC19@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -4961,29 +4961,29 @@ define <2 x i64> @spltConst1ull() { ; P9BE-LABEL: spltConst1ull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC20@toc@ha +; P9BE-NEXT: ld r3, .LC20@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst1ull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC18@toc@ha +; P9LE-NEXT: ld r3, .LC18@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst1ull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC20@toc@ha +; P8BE-NEXT: ld r3, .LC20@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltConst1ull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC20@toc@ha +; P8LE-NEXT: ld r3, .LC20@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -4994,29 +4994,29 @@ define <2 x i64> @spltConst16kull() { ; P9BE-LABEL: spltConst16kull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC21@toc@ha +; P9BE-NEXT: ld r3, .LC21@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst16kull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC19@toc@ha +; P9LE-NEXT: ld r3, .LC19@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst16kull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC21@toc@ha +; P8BE-NEXT: ld r3, .LC21@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltConst16kull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC21@toc@ha +; P8LE-NEXT: ld r3, .LC21@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -5027,29 +5027,29 @@ define <2 x i64> @spltConst32kull() { ; P9BE-LABEL: spltConst32kull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC22@toc@ha +; P9BE-NEXT: ld r3, .LC22@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst32kull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC20@toc@ha +; P9LE-NEXT: ld r3, .LC20@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst32kull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC22@toc@ha +; P8BE-NEXT: ld r3, .LC22@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltConst32kull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC22@toc@ha +; P8LE-NEXT: ld r3, .LC22@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -5090,29 +5090,29 @@ define <2 x i64> @fromDiffConstsull() { ; P9BE-LABEL: fromDiffConstsull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC23@toc@ha +; P9BE-NEXT: ld r3, .LC23@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC21@toc@ha +; P9LE-NEXT: ld r3, .LC21@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC23@toc@ha +; P8BE-NEXT: ld r3, .LC23@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC23@toc@ha +; P8LE-NEXT: ld r3, .LC23@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -5424,29 +5424,29 @@ define <2 x i64> @spltCnstConvftoull() { ; P9BE-LABEL: spltCnstConvftoull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC24@toc@ha +; P9BE-NEXT: ld r3, .LC24@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvftoull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC22@toc@ha +; P9LE-NEXT: ld r3, .LC22@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvftoull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC24@toc@ha +; P8BE-NEXT: ld r3, .LC24@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltCnstConvftoull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC24@toc@ha +; P8LE-NEXT: ld r3, .LC24@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -5497,29 +5497,29 @@ define <2 x i64> @fromDiffConstsConvftoull() { ; P9BE-LABEL: fromDiffConstsConvftoull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC25@toc@ha +; P9BE-NEXT: ld r3, .LC25@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC23@toc@ha +; P9LE-NEXT: ld r3, .LC23@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC25@toc@ha +; P8BE-NEXT: ld r3, .LC25@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvftoull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC25@toc@ha +; P8LE-NEXT: ld r3, .LC25@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -5786,29 +5786,29 @@ define <2 x i64> @spltCnstConvdtoull() { ; P9BE-LABEL: spltCnstConvdtoull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC26@toc@ha +; P9BE-NEXT: ld r3, .LC26@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvdtoull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC24@toc@ha +; P9LE-NEXT: ld r3, .LC24@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvdtoull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC26@toc@ha +; P8BE-NEXT: ld r3, .LC26@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: spltCnstConvdtoull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC26@toc@ha +; P8LE-NEXT: ld r3, .LC26@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr @@ -5859,29 +5859,29 @@ define <2 x i64> @fromDiffConstsConvdtoull() { ; P9BE-LABEL: fromDiffConstsConvdtoull: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l +; P9BE-NEXT: addis r3, r2, .LC27@toc@ha +; P9BE-NEXT: ld r3, .LC27@toc@l(r3) ; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoull: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha -; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l +; P9LE-NEXT: addis r3, r2, .LC25@toc@ha +; P9LE-NEXT: ld r3, .LC25@toc@l(r3) ; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha -; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l +; P8BE-NEXT: addis r3, r2, .LC27@toc@ha +; P8BE-NEXT: ld r3, .LC27@toc@l(r3) ; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffConstsConvdtoull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha -; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l +; P8LE-NEXT: addis r3, r2, .LC27@toc@ha +; P8LE-NEXT: ld r3, .LC27@toc@l(r3) ; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll --- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll +++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll @@ -41,8 +41,8 @@ ; ; CHECK-NOVSX-LABEL: testmrghb2: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: blr @@ -82,8 +82,8 @@ ; ; CHECK-NOVSX-LABEL: testmrghh2: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI3_0@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI3_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: blr @@ -123,8 +123,8 @@ ; ; CHECK-NOVSX-LABEL: testmrglb2: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: blr @@ -164,8 +164,8 @@ ; ; CHECK-NOVSX-LABEL: testmrglh2: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI7_0@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI7_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: blr @@ -205,8 +205,8 @@ ; ; CHECK-NOVSX-LABEL: testmrghw2: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI9_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: blr @@ -246,8 +246,8 @@ ; ; CHECK-NOVSX-LABEL: testmrglw2: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI11_0@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI11_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC5@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC5@toc@l(r3) ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: blr @@ -274,13 +274,13 @@ ; ; CHECK-NOVSX-LABEL: testmrglb3: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: vxor v2, v2, v2 +; CHECK-NOVSX-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NOVSX-NEXT: ld r3, 0(r3) -; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI12_0@toc@ha -; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI12_0@toc@l -; CHECK-NOVSX-NEXT: lvx v3, 0, r4 +; CHECK-NOVSX-NEXT: vxor v2, v2, v2 +; CHECK-NOVSX-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-NOVSX-NEXT: std r3, -16(r1) ; CHECK-NOVSX-NEXT: addi r3, r1, -16 +; CHECK-NOVSX-NEXT: lvx v3, 0, r4 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3 ; CHECK-NOVSX-NEXT: blr @@ -356,10 +356,10 @@ ; ; CHECK-NOVSX-LABEL: no_crash_bitcast: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI14_0@toc@ha +; CHECK-NOVSX-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-NOVSX-NEXT: stw r3, -16(r1) ; CHECK-NOVSX-NEXT: addi r3, r1, -16 -; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI14_0@toc@l +; CHECK-NOVSX-NEXT: ld r4, .LC7@toc@l(r4) ; CHECK-NOVSX-NEXT: lvx v3, 0, r3 ; CHECK-NOVSX-NEXT: lvx v2, 0, r4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2 @@ -373,28 +373,28 @@ define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 { ; CHECK-P8-LABEL: replace_undefs_in_splat: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vmrgow v2, v3, v2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: replace_undefs_in_splat: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vmrgow v2, v3, v2 ; CHECK-P9-NEXT: blr ; ; CHECK-NOVSX-LABEL: replace_undefs_in_splat: ; CHECK-NOVSX: # %bb.0: # %entry -; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI15_1@toc@ha -; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI15_0@toc@l +; CHECK-NOVSX-NEXT: addis r3, r2, .LC8@toc@ha +; CHECK-NOVSX-NEXT: addis r4, r2, .LC9@toc@ha +; CHECK-NOVSX-NEXT: ld r3, .LC8@toc@l(r3) +; CHECK-NOVSX-NEXT: ld r4, .LC9@toc@l(r4) ; CHECK-NOVSX-NEXT: lvx v3, 0, r3 -; CHECK-NOVSX-NEXT: addi r3, r4, .LCPI15_1@toc@l -; CHECK-NOVSX-NEXT: lvx v4, 0, r3 +; CHECK-NOVSX-NEXT: lvx v4, 0, r4 ; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3 ; CHECK-NOVSX-NEXT: blr entry: @@ -405,10 +405,10 @@ define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture readonly %ptr, i32 signext %offset) local_unnamed_addr #0 { ; CHECK-P8-LABEL: no_RAUW_in_combine_during_legalize: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI16_0@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC1@toc@ha ; CHECK-P8-NEXT: sldi r4, r4, 2 ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI16_0@toc@l +; CHECK-P8-NEXT: ld r5, .LC1@toc@l(r5) ; CHECK-P8-NEXT: lxsiwzx v2, r3, r4 ; CHECK-P8-NEXT: lvx v3, 0, r5 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3 @@ -419,8 +419,8 @@ ; CHECK-P9-NEXT: sldi r4, r4, 2 ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: lxsiwzx v2, r3, r4 -; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: blr @@ -518,12 +518,12 @@ ; ; CHECK-NOVSX-LABEL: testSplat8: ; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: addis r4, r2, .LC10@toc@ha ; CHECK-NOVSX-NEXT: ld r3, 0(r3) -; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI19_0@toc@ha -; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI19_0@toc@l -; CHECK-NOVSX-NEXT: lvx v2, 0, r4 +; CHECK-NOVSX-NEXT: ld r4, .LC10@toc@l(r4) ; CHECK-NOVSX-NEXT: std r3, -16(r1) ; CHECK-NOVSX-NEXT: addi r3, r1, -16 +; CHECK-NOVSX-NEXT: lvx v2, 0, r4 ; CHECK-NOVSX-NEXT: lvx v3, 0, r3 ; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2 ; CHECK-NOVSX-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/combine-fneg.ll b/llvm/test/CodeGen/PowerPC/combine-fneg.ll --- a/llvm/test/CodeGen/PowerPC/combine-fneg.ll +++ b/llvm/test/CodeGen/PowerPC/combine-fneg.ll @@ -5,12 +5,12 @@ define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) { ; CHECK-LABEL: fneg_fdiv_splat: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; CHECK-NEXT: xxspltd 0, 1, 0 -; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l -; CHECK-NEXT: lxvd2x 1, 0, 3 +; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: xvredp 2, 0 +; CHECK-NEXT: lxvd2x 1, 0, 3 ; CHECK-NEXT: xxswapd 1, 1 ; CHECK-NEXT: xxlor 3, 1, 1 ; CHECK-NEXT: xvnmsubadp 3, 0, 2 diff --git a/llvm/test/CodeGen/PowerPC/constant-pool.ll b/llvm/test/CodeGen/PowerPC/constant-pool.ll --- a/llvm/test/CodeGen/PowerPC/constant-pool.ll +++ b/llvm/test/CodeGen/PowerPC/constant-pool.ll @@ -5,6 +5,13 @@ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-P9 +; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \ +; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-P8 + +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 2 +; CHECK-P9-LABEL: .LCPI0_0: +; CHECK-P9: .long 0x007fffe1 define float @FloatConstantPool() { ; CHECK-LABEL: FloatConstantPool: @@ -14,13 +21,26 @@ ; ; CHECK-P9-LABEL: FloatConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-P9-NEXT: lfs f1, .LCPI0_0@toc@l(r3) +; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-P9-NEXT: lfs f1, 0(r3) ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: FloatConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-P8-NEXT: lfsx f1, 0, r3 +; CHECK-P8-NEXT: blr entry: ret float 0x380FFFF840000000 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 3 +; CHECK-P9-LABEL: .LCPI1_0: +; CHECK-P9: .quad 0x000ffffe2e8159d0 + define double @DoubleConstantPool() { ; CHECK-LABEL: DoubleConstantPool: ; CHECK: # %bb.0: # %entry @@ -29,13 +49,27 @@ ; ; CHECK-P9-LABEL: DoubleConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-P9-NEXT: lfd f1, .LCPI1_0@toc@l(r3) +; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 0(r3) ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: DoubleConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-P8-NEXT: ld r3, .LC1@toc@l(r3) +; CHECK-P8-NEXT: lfdx f1, 0, r3 +; CHECK-P8-NEXT: blr entry: ret double 2.225070e-308 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 3 +; CHECK-P9-LABEL: .LCPI2_0: +; CHECK-P9: .quad 0x800d16974fd9d27b +; CHECK-P9: .quad 0x03600000dba876cc + define ppc_fp128 @LongDoubleConstantPool() { ; CHECK-LABEL: LongDoubleConstantPool: ; CHECK: # %bb.0: # %entry @@ -45,15 +79,29 @@ ; ; CHECK-P9-LABEL: LongDoubleConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-P9-NEXT: lfd f1, .LCPI2_0@toc@l(r3) -; CHECK-P9-NEXT: addis r3, r2, .LCPI2_1@toc@ha -; CHECK-P9-NEXT: lfd f2, .LCPI2_1@toc@l(r3) +; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 8(r3) +; CHECK-P9-NEXT: lfd f2, 0(r3) ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: LongDoubleConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-P8-NEXT: ld r3, .LC2@toc@l(r3) +; CHECK-P8-NEXT: lfd f1, 8(r3) +; CHECK-P8-NEXT: lfdx f2, 0, r3 +; CHECK-P8-NEXT: blr entry: ret ppc_fp128 0xM03600000DBA876CC800D16974FD9D27B } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI3_0: +; CHECK-P9: .quad 0x3c00ffffc5d02b3a +; CHECK-P9: .quad 0x0000000000000000 + define fp128 @__Float128ConstantPool() { ; CHECK-LABEL: __Float128ConstantPool: ; CHECK: # %bb.0: # %entry @@ -62,14 +110,43 @@ ; ; CHECK-P9-LABEL: __Float128ConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-P9-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: __Float128ConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: lis r3, 15360 +; CHECK-P8-NEXT: li r4, 0 +; CHECK-P8-NEXT: ori r3, r3, 65535 +; CHECK-P8-NEXT: sldi r3, r3, 32 +; CHECK-P8-NEXT: oris r3, r3, 50640 +; CHECK-P8-NEXT: ori r3, r3, 11066 +; CHECK-P8-NEXT: blr entry: ret fp128 0xL00000000000000003C00FFFFC5D02B3A } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI4_0: +; CHECK-P9-NEXT: .byte 128 +; CHECK-P9-NEXT: .byte 129 +; CHECK-P9-NEXT: .byte 130 +; CHECK-P9-NEXT: .byte 131 +; CHECK-P9-NEXT: .byte 132 +; CHECK-P9-NEXT: .byte 133 +; CHECK-P9-NEXT: .byte 134 +; CHECK-P9-NEXT: .byte 135 +; CHECK-P9-NEXT: .byte 136 +; CHECK-P9-NEXT: .byte 137 +; CHECK-P9-NEXT: .byte 138 +; CHECK-P9-NEXT: .byte 139 +; CHECK-P9-NEXT: .byte 140 +; CHECK-P9-NEXT: .byte 141 +; CHECK-P9-NEXT: .byte 142 +; CHECK-P9-NEXT: .byte 143 define <16 x i8> @VectorCharConstantPool() { ; CHECK-LABEL: VectorCharConstantPool: ; CHECK: # %bb.0: # %entry @@ -78,14 +155,32 @@ ; ; CHECK-P9-LABEL: VectorCharConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-P9-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorCharConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-P8-NEXT: ld r3, .LC3@toc@l(r3) +; CHECK-P8-NEXT: lxvw4x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <16 x i8> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI5_0: +; CHECK-P9-NEXT: .short 32768 +; CHECK-P9-NEXT: .short 32769 +; CHECK-P9-NEXT: .short 32770 +; CHECK-P9-NEXT: .short 32771 +; CHECK-P9-NEXT: .short 32772 +; CHECK-P9-NEXT: .short 32773 +; CHECK-P9-NEXT: .short 32774 +; CHECK-P9-NEXT: .short 32775 define <8 x i16> @VectorShortConstantPool() { ; CHECK-LABEL: VectorShortConstantPool: ; CHECK: # %bb.0: # %entry @@ -94,14 +189,28 @@ ; ; CHECK-P9-LABEL: VectorShortConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC5@toc@ha +; CHECK-P9-NEXT: ld r3, .LC5@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorShortConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-P8-NEXT: ld r3, .LC4@toc@l(r3) +; CHECK-P8-NEXT: lxvw4x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <8 x i16> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: p2align 4 +; CHECK-P9-LABEL:.LCPI6_0: +; CHECK-P9-NEXT:.long 2147483648 +; CHECK-P9-NEXT:.long 2147483649 +; CHECK-P9-NEXT:.long 2147483650 +; CHECK-P9-NEXT:.long 2147483651 define <4 x i32> @VectorIntConstantPool() { ; CHECK-LABEL: VectorIntConstantPool: ; CHECK: # %bb.0: # %entry @@ -110,14 +219,26 @@ ; ; CHECK-P9-LABEL: VectorIntConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC6@toc@ha +; CHECK-P9-NEXT: ld r3, .LC6@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorIntConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC5@toc@ha +; CHECK-P8-NEXT: ld r3, .LC5@toc@l(r3) +; CHECK-P8-NEXT: lxvw4x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <4 x i32> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI7_0: +; CHECK-P9-NEXT: .quad -9223372036854775808 +; CHECK-P9-NEXT: .quad -9223372036854775807 define <2 x i64> @VectorLongLongConstantPool() { ; CHECK-LABEL: VectorLongLongConstantPool: ; CHECK: # %bb.0: # %entry @@ -126,14 +247,26 @@ ; ; CHECK-P9-LABEL: VectorLongLongConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI7_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC7@toc@ha +; CHECK-P9-NEXT: ld r3, .LC7@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorLongLongConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC6@toc@ha +; CHECK-P8-NEXT: ld r3, .LC6@toc@l(r3) +; CHECK-P8-NEXT: lxvd2x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <2 x i64> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: p2align 4 +; CHECK-P9-LABEL: .LCPI8_0: +; CHECK-P9-NEXT: .quad -2 +; CHECK-P9-NEXT: .quad -9223372036854775808 define <1 x i128> @VectorInt128ConstantPool() { ; CHECK-LABEL: VectorInt128ConstantPool: ; CHECK: # %bb.0: # %entry @@ -142,14 +275,28 @@ ; ; CHECK-P9-LABEL: VectorInt128ConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI8_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI8_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC8@toc@ha +; CHECK-P9-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorInt128ConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC7@toc@ha +; CHECK-P8-NEXT: ld r3, .LC7@toc@l(r3) +; CHECK-P8-NEXT: lxvd2x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <1 x i128> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI9_0: +; CHECK-P9-NEXT: .long 0x007fffe1 +; CHECK-P9-NEXT: .long 0x007ffd5f +; CHECK-P9-NEXT: .long 0x021fffd9 +; CHECK-P9-NEXT: .long 0x021ffcb6 define <4 x float> @VectorFloatConstantPool() { ; CHECK-LABEL: VectorFloatConstantPool: ; CHECK: # %bb.0: # %entry @@ -158,14 +305,26 @@ ; ; CHECK-P9-LABEL: VectorFloatConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC9@toc@ha +; CHECK-P9-NEXT: ld r3, .LC9@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorFloatConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha +; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) +; CHECK-P8-NEXT: lxvw4x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <4 x float> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI10_0: +; CHECK-P9-NEXT: .quad 0x000ffffe2e8159d0 +; CHECK-P9-NEXT: .quad 0x000fffdd31a00c6d define <2 x double> @VectorDoubleConstantPool() { ; CHECK-LABEL: VectorDoubleConstantPool: ; CHECK: # %bb.0: # %entry @@ -174,14 +333,26 @@ ; ; CHECK-P9-LABEL: VectorDoubleConstantPool: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC10@toc@ha +; CHECK-P9-NEXT: ld r3, .LC10@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: VectorDoubleConstantPool: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC9@toc@ha +; CHECK-P8-NEXT: ld r3, .LC9@toc@l(r3) +; CHECK-P8-NEXT: lxvd2x vs34, 0, r3 +; CHECK-P8-NEXT: blr entry: ret <2 x double> } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 3 +; CHECK-P9-LABEL: .LCPI11_0: +; CHECK-P9-NEXT: .quad 0x4002c083126e978d +; CHECK-P9-NEXT: .quad 0x400ac083126e978d define double @two_constants(double %a) { ; CHECK-LABEL: two_constants: ; CHECK: # %bb.0: # %entry @@ -193,19 +364,34 @@ ; ; CHECK-P9-LABEL: two_constants: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI11_0@toc@ha -; CHECK-P9-NEXT: lfd f0, .LCPI11_0@toc@l(r3) -; CHECK-P9-NEXT: addis r3, r2, .LCPI11_1@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC11@toc@ha +; CHECK-P9-NEXT: ld r3, .LC11@toc@l(r3) +; CHECK-P9-NEXT: lfd f0, 8(r3) ; CHECK-P9-NEXT: xsadddp f0, f1, f0 -; CHECK-P9-NEXT: lfd f1, .LCPI11_1@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 0(r3) ; CHECK-P9-NEXT: xsadddp f1, f0, f1 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: two_constants: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC10@toc@ha +; CHECK-P8-NEXT: ld r3, .LC10@toc@l(r3) +; CHECK-P8-NEXT: lfd f0, 8(r3) +; CHECK-P8-NEXT: xsadddp f0, f1, f0 +; CHECK-P8-NEXT: lfdx f1, 0, r3 +; CHECK-P8-NEXT: xsadddp f1, f0, f1 +; CHECK-P8-NEXT: blr entry: %0 = fadd double %a, 3.344000e+00 %1 = fadd double %0, 2.344000e+00 ret double %1 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 3 +; CHECK-P9-LABEL: .LCPI12_0: +; CHECK-P9-NEXT: .quad 0x40123851eb851eb8 +; CHECK-P9-NEXT: .quad 0x4023c28f5c28f5c3 define double @two_constants_two_bb(i32 %m, double %a) { ; CHECK-LABEL: two_constants_two_bb: ; CHECK: # %bb.0: # %entry @@ -221,17 +407,31 @@ ; ; CHECK-P9-LABEL: two_constants_two_bb: ; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: addis r4, r2, .LC12@toc@ha ; CHECK-P9-NEXT: cmplwi r3, 0 +; CHECK-P9-NEXT: ld r4, .LC12@toc@l(r4) ; CHECK-P9-NEXT: beq cr0, .LBB12_2 ; CHECK-P9-NEXT: # %bb.1: -; CHECK-P9-NEXT: addis r3, r2, .LCPI12_0@toc@ha -; CHECK-P9-NEXT: lfd f1, .LCPI12_0@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 0(r4) ; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: .LBB12_2: # %if.end -; CHECK-P9-NEXT: addis r3, r2, .LCPI12_1@toc@ha -; CHECK-P9-NEXT: lfd f0, .LCPI12_1@toc@l(r3) +; CHECK-P9-NEXT: lfd f0, 8(r4) ; CHECK-P9-NEXT: xsadddp f1, f1, f0 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: two_constants_two_bb: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: cmplwi r3, 0 +; CHECK-P8-NEXT: addis r3, r2, .LC11@toc@ha +; CHECK-P8-NEXT: ld r3, .LC11@toc@l(r3) +; CHECK-P8-NEXT: beq cr0, .LBB12_2 +; CHECK-P8-NEXT: # %bb.1: +; CHECK-P8-NEXT: lfdx f1, 0, r3 +; CHECK-P8-NEXT: blr +; CHECK-P8-NEXT: .LBB12_2: # %if.end +; CHECK-P8-NEXT: lfd f0, 8(r3) +; CHECK-P8-NEXT: xsadddp f1, f1, f0 +; CHECK-P8-NEXT: blr entry: %tobool.not = icmp eq i32 %m, 0 br i1 %tobool.not, label %if.end, label %return @@ -245,6 +445,12 @@ ret double %retval.0 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 3 +; CHECK-P9-LABEL: .LCPI13_0: +; CHECK-P9-NEXT: .quad 0x400326e978d4fdf4 +; CHECK-P9-NEXT: .quad 0x4002c083126e978d +; CHECK-P9-NEXT: .quad 0x400ac083126e978d define double @three_constants_f64(double %a, double %c) { ; CHECK-LABEL: three_constants_f64: ; CHECK: # %bb.0: # %entry @@ -258,16 +464,27 @@ ; ; CHECK-P9-LABEL: three_constants_f64: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha -; CHECK-P9-NEXT: lfd f0, .LCPI13_0@toc@l(r3) -; CHECK-P9-NEXT: addis r3, r2, .LCPI13_1@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC13@toc@ha +; CHECK-P9-NEXT: ld r3, .LC13@toc@l(r3) +; CHECK-P9-NEXT: lfd f0, 16(r3) ; CHECK-P9-NEXT: xsadddp f0, f1, f0 -; CHECK-P9-NEXT: lfd f1, .LCPI13_1@toc@l(r3) -; CHECK-P9-NEXT: addis r3, r2, .LCPI13_2@toc@ha +; CHECK-P9-NEXT: lfd f1, 8(r3) ; CHECK-P9-NEXT: xsadddp f0, f0, f1 -; CHECK-P9-NEXT: lfd f1, .LCPI13_2@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 0(r3) ; CHECK-P9-NEXT: xsadddp f1, f0, f1 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: three_constants_f64: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC12@toc@ha +; CHECK-P8-NEXT: ld r3, .LC12@toc@l(r3) +; CHECK-P8-NEXT: lfd f0, 16(r3) +; CHECK-P8-NEXT: xsadddp f0, f1, f0 +; CHECK-P8-NEXT: lfd f1, 8(r3) +; CHECK-P8-NEXT: xsadddp f0, f0, f1 +; CHECK-P8-NEXT: lfdx f1, 0, r3 +; CHECK-P8-NEXT: xsadddp f1, f0, f1 +; CHECK-P8-NEXT: blr entry: %0 = fadd double %a, 3.344000e+00 %1 = fadd double %0, 2.344000e+00 @@ -275,6 +492,12 @@ ret double %2 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 2 +; CHECK-P9-LABEL: .LCPI14_0: +; CHECK-P9-NEXT: .long 0x4091bb8f +; CHECK-P9-NEXT: .long 0x4091cc8f +; CHECK-P9-NEXT: .long 0x4091c28f define float @three_constants_f32(float %a, float %c) { ; CHECK-LABEL: three_constants_f32: ; CHECK: # %bb.0: # %entry @@ -288,16 +511,27 @@ ; ; CHECK-P9-LABEL: three_constants_f32: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI14_0@toc@ha -; CHECK-P9-NEXT: lfs f0, .LCPI14_0@toc@l(r3) -; CHECK-P9-NEXT: addis r3, r2, .LCPI14_1@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC14@toc@ha +; CHECK-P9-NEXT: ld r3, .LC14@toc@l(r3) +; CHECK-P9-NEXT: lfs f0, 8(r3) ; CHECK-P9-NEXT: xsaddsp f0, f1, f0 -; CHECK-P9-NEXT: lfs f1, .LCPI14_1@toc@l(r3) -; CHECK-P9-NEXT: addis r3, r2, .LCPI14_2@toc@ha +; CHECK-P9-NEXT: lfs f1, 4(r3) ; CHECK-P9-NEXT: xsaddsp f0, f0, f1 -; CHECK-P9-NEXT: lfs f1, .LCPI14_2@toc@l(r3) +; CHECK-P9-NEXT: lfs f1, 0(r3) ; CHECK-P9-NEXT: xsaddsp f1, f0, f1 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: three_constants_f32: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC13@toc@ha +; CHECK-P8-NEXT: ld r3, .LC13@toc@l(r3) +; CHECK-P8-NEXT: lfs f0, 8(r3) +; CHECK-P8-NEXT: xsaddsp f0, f1, f0 +; CHECK-P8-NEXT: lfs f1, 4(r3) +; CHECK-P8-NEXT: xsaddsp f0, f0, f1 +; CHECK-P8-NEXT: lfsx f1, 0, r3 +; CHECK-P8-NEXT: xsaddsp f1, f0, f1 +; CHECK-P8-NEXT: blr entry: %0 = fadd float %a, 0x40123851E0000000 %1 = fadd float %0, 0x40123991E0000000 @@ -305,6 +539,15 @@ ret float %2 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI15_0: +; CHECK-P9-NEXT: .quad 0x400123851eb771eb +; CHECK-P9-NEXT: .quad 0x8000000000000000 +; CHECK-P9-NEXT: .quad 0x400123851eb991eb +; CHECK-P9-NEXT: .quad 0x8000000000000000 +; CHECK-P9-NEXT: .quad 0x400123851eb851eb +; CHECK-P9-NEXT: .quad 0x8000000000000000 define fp128 @three_constants_f128(fp128 %a, fp128 %c) { ; CHECK-LABEL: three_constants_f128: ; CHECK: # %bb.0: # %entry @@ -318,19 +561,53 @@ ; ; CHECK-P9-LABEL: three_constants_f128: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-NEXT: lxvx vs35, 0, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI15_1@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI15_1@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC15@toc@ha +; CHECK-P9-NEXT: ld r3, .LC15@toc@l(r3) +; CHECK-P9-NEXT: lxv vs35, 32(r3) ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 -; CHECK-P9-NEXT: lxvx vs35, 0, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI15_2@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI15_2@toc@l +; CHECK-P9-NEXT: lxv vs35, 16(r3) ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: three_constants_f128: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mflr r0 +; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: .cfi_offset r29, -24 +; CHECK-P8-NEXT: .cfi_offset r30, -16 +; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -64(r1) +; CHECK-P8-NEXT: lis r5, 16385 +; CHECK-P8-NEXT: ori r5, r5, 9093 +; CHECK-P8-NEXT: sldi r29, r5, 32 +; CHECK-P8-NEXT: li r5, 1 +; CHECK-P8-NEXT: oris r6, r29, 7864 +; CHECK-P8-NEXT: sldi r30, r5, 63 +; CHECK-P8-NEXT: ori r5, r6, 20971 +; CHECK-P8-NEXT: mr r6, r30 +; CHECK-P8-NEXT: bl __addkf3 +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: oris r5, r29, 7865 +; CHECK-P8-NEXT: mr r6, r30 +; CHECK-P8-NEXT: ori r5, r5, 37355 +; CHECK-P8-NEXT: bl __addkf3 +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: oris r5, r29, 7863 +; CHECK-P8-NEXT: mr r6, r30 +; CHECK-P8-NEXT: ori r5, r5, 29163 +; CHECK-P8-NEXT: bl __addkf3 +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: ld r0, 16(r1) +; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: mtlr r0 +; CHECK-P8-NEXT: blr entry: %0 = fadd fp128 %a, 0xL8000000000000000400123851EB851EB %1 = fadd fp128 %0, 0xL8000000000000000400123851EB991EB @@ -338,6 +615,12 @@ ret fp128 %2 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: p2align 3 +; CHECK-P9-LABEL: .LCPI16_0: +; CHECK-P9-NEXT: .quad 0x40123851eb851eb8 +; CHECK-P9-NEXT: .quad 0x4012385199851eb8 +; CHECK-P9-NEXT: .quad 0x4012385100851eb8 define ppc_fp128 @three_constants_ppcf128(ppc_fp128 %a, ppc_fp128 %c) { ; CHECK-LABEL: three_constants_ppcf128: ; CHECK: .localentry three_constants_ppcf128, 1 @@ -364,29 +647,60 @@ ; CHECK-P9-LABEL: three_constants_ppcf128: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mflr r0 -; CHECK-P9-NEXT: std r0, 16(r1) -; CHECK-P9-NEXT: stdu r1, -32(r1) -; CHECK-P9-NEXT: .cfi_def_cfa_offset 32 +; CHECK-P9-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P9-NEXT: .cfi_offset lr, 16 -; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; CHECK-P9-NEXT: .cfi_offset r30, -16 +; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; CHECK-P9-NEXT: std r0, 16(r1) +; CHECK-P9-NEXT: stdu r1, -48(r1) +; CHECK-P9-NEXT: addis r3, r2, .LC16@toc@ha ; CHECK-P9-NEXT: xxlxor f4, f4, f4 -; CHECK-P9-NEXT: lfd f3, .LCPI16_0@toc@l(r3) +; CHECK-P9-NEXT: ld r30, .LC16@toc@l(r3) +; CHECK-P9-NEXT: lfd f3, 0(r30) ; CHECK-P9-NEXT: bl __gcc_qadd ; CHECK-P9-NEXT: nop -; CHECK-P9-NEXT: addis r3, r2, .LCPI16_1@toc@ha +; CHECK-P9-NEXT: lfd f3, 8(r30) ; CHECK-P9-NEXT: xxlxor f4, f4, f4 -; CHECK-P9-NEXT: lfd f3, .LCPI16_1@toc@l(r3) ; CHECK-P9-NEXT: bl __gcc_qadd ; CHECK-P9-NEXT: nop -; CHECK-P9-NEXT: addis r3, r2, .LCPI16_2@toc@ha +; CHECK-P9-NEXT: lfd f3, 16(r30) ; CHECK-P9-NEXT: xxlxor f4, f4, f4 -; CHECK-P9-NEXT: lfd f3, .LCPI16_2@toc@l(r3) ; CHECK-P9-NEXT: bl __gcc_qadd ; CHECK-P9-NEXT: nop -; CHECK-P9-NEXT: addi r1, r1, 32 +; CHECK-P9-NEXT: addi r1, r1, 48 ; CHECK-P9-NEXT: ld r0, 16(r1) +; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: mtlr r0 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: three_constants_ppcf128: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mflr r0 +; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 +; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: .cfi_offset r30, -16 +; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -48(r1) +; CHECK-P8-NEXT: addis r3, r2, .LC14@toc@ha +; CHECK-P8-NEXT: xxlxor f4, f4, f4 +; CHECK-P8-NEXT: ld r30, .LC14@toc@l(r3) +; CHECK-P8-NEXT: lfdx f3, 0, r30 +; CHECK-P8-NEXT: bl __gcc_qadd +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: xxlxor f4, f4, f4 +; CHECK-P8-NEXT: lfd f3, 8(r30) +; CHECK-P8-NEXT: bl __gcc_qadd +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: xxlxor f4, f4, f4 +; CHECK-P8-NEXT: lfd f3, 16(r30) +; CHECK-P8-NEXT: bl __gcc_qadd +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: addi r1, r1, 48 +; CHECK-P8-NEXT: ld r0, 16(r1) +; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: mtlr r0 +; CHECK-P8-NEXT: blr entry: %0 = fadd ppc_fp128 %a, 0xM40123851EB851EB80000000000000000 %1 = fadd ppc_fp128 %0, 0xM4012385199851EB80000000000000000 @@ -394,6 +708,13 @@ ret ppc_fp128 %2 } +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI17_0: +; CHECK-P9-NEXT: .quad 0x40123851eb851eb8 +; CHECK-P9-NEXT: .quad 0x4023f5c28f5c28f6 +; CHECK-P9-NEXT: .quad 0x40123851eb851eb8 +; CHECK-P9-NEXT: .quad 0x4023c28f5c28f5c3 define <2 x double> @three_constants_vector(<2 x double> %a, <2 x double> %c) { ; CHECK-LABEL: three_constants_vector: ; CHECK: # %bb.0: # %entry @@ -406,19 +727,269 @@ ; ; CHECK-P9-LABEL: three_constants_vector: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI17_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI17_0@toc@l -; CHECK-P9-NEXT: lxvx vs0, 0, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI17_1@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI17_1@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC17@toc@ha +; CHECK-P9-NEXT: ld r3, .LC17@toc@l(r3) +; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxvx vs2, 0, r3 ; CHECK-P9-NEXT: xvadddp vs1, vs34, vs0 ; CHECK-P9-NEXT: xvadddp vs1, vs1, vs2 ; CHECK-P9-NEXT: xvadddp vs34, vs1, vs0 ; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: three_constants_vector: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addis r3, r2, .LC15@toc@ha +; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: ld r3, .LC15@toc@l(r3) +; CHECK-P8-NEXT: lxvd2x vs0, r3, r4 +; CHECK-P8-NEXT: lxvd2x vs2, 0, r3 +; CHECK-P8-NEXT: xvadddp vs1, vs34, vs0 +; CHECK-P8-NEXT: xvadddp vs1, vs1, vs2 +; CHECK-P8-NEXT: xvadddp vs34, vs1, vs0 +; CHECK-P8-NEXT: blr entry: %0 = fadd <2 x double> %a, %1 = fadd <2 x double> %0, %2 = fadd <2 x double> %1, ret <2 x double> %2 } + +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 4 +; CHECK-P9-LABEL: .LCPI18_0: +; CHECK-P9-NEXT: .quad 0x402871a9fbe76c8b +; CHECK-P9-NEXT: .quad 0x402871a9fbe76c8b +; CHECK-P9-NEXT: .quad 0x407563b2fec56d5d +; CHECK-P9-NEXT: .quad 0x412446e7f9db22d1 +; CHECK-P9-LABEL: .LCPI18_1: +; CHECK-P9-NEXT: .quad 0x40a2939884e831ad +; CHECK-P9-LABEL: .LCPI18_2: +; CHECK-P9-NEXT: .long 0x4457499a +; CHECK-P9-NEXT: .long 0x4479f852 +define void @constant_pool_mixed_type(<2 x double>* %ArrV, double* %ArrD, i16* %ArrS, float* %ArrF) { +; CHECK-P9-LABEL: constant_pool_mixed_type: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: lis r7, 12 +; CHECK-P9-NEXT: ori r7, r7, 44 +; CHECK-P9-NEXT: sldi r7, r7, 32 +; CHECK-P9-NEXT: oris r7, r7, 8 +; CHECK-P9-NEXT: ori r7, r7, 98 +; CHECK-P9-NEXT: std r7, 0(r5) +; CHECK-P9-NEXT: lis r7, 271 +; CHECK-P9-NEXT: ori r7, r7, 888 +; CHECK-P9-NEXT: stw r7, 8(r5) +; CHECK-P9-NEXT: li r7, 99 +; CHECK-P9-NEXT: sth r7, 12(r5) +; CHECK-P9-NEXT: addis r5, r2, .LC18@toc@ha +; CHECK-P9-NEXT: lfs f0, 0(r6) +; CHECK-P9-NEXT: ld r5, .LC18@toc@l(r5) +; CHECK-P9-NEXT: lfs f1, 4(r5) +; CHECK-P9-NEXT: xsaddsp f0, f0, f1 +; CHECK-P9-NEXT: lfs f1, 0(r5) +; CHECK-P9-NEXT: addis r5, r2, .LC19@toc@ha +; CHECK-P9-NEXT: ld r5, .LC19@toc@l(r5) +; CHECK-P9-NEXT: stfs f0, 0(r6) +; CHECK-P9-NEXT: lfs f0, 4(r6) +; CHECK-P9-NEXT: xsaddsp f0, f0, f1 +; CHECK-P9-NEXT: stfs f0, 4(r6) +; CHECK-P9-NEXT: lxv vs0, 16(r5) +; CHECK-P9-NEXT: stxv vs0, 0(r3) +; CHECK-P9-NEXT: lxvx vs0, 0, r5 +; CHECK-P9-NEXT: stxv vs0, 16(r3) +; CHECK-P9-NEXT: addis r3, r2, .LC20@toc@ha +; CHECK-P9-NEXT: lfd f0, 40(r4) +; CHECK-P9-NEXT: ld r3, .LC20@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 0(r3) +; CHECK-P9-NEXT: xsadddp f0, f0, f1 +; CHECK-P9-NEXT: stfd f0, 40(r4) +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: constant_pool_mixed_type: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: lis r7, 12 +; CHECK-P8-NEXT: addis r8, r2, .LC16@toc@ha +; CHECK-P8-NEXT: lis r9, 271 +; CHECK-P8-NEXT: li r10, 99 +; CHECK-P8-NEXT: ori r7, r7, 44 +; CHECK-P8-NEXT: ld r8, .LC16@toc@l(r8) +; CHECK-P8-NEXT: ori r9, r9, 888 +; CHECK-P8-NEXT: sth r10, 12(r5) +; CHECK-P8-NEXT: sldi r7, r7, 32 +; CHECK-P8-NEXT: stw r9, 8(r5) +; CHECK-P8-NEXT: oris r7, r7, 8 +; CHECK-P8-NEXT: ori r7, r7, 98 +; CHECK-P8-NEXT: lfsx f2, 0, r8 +; CHECK-P8-NEXT: std r7, 0(r5) +; CHECK-P8-NEXT: addis r7, r2, .LC17@toc@ha +; CHECK-P8-NEXT: lfs f0, 4(r8) +; CHECK-P8-NEXT: lfsx f1, 0, r6 +; CHECK-P8-NEXT: ld r7, .LC17@toc@l(r7) +; CHECK-P8-NEXT: li r8, 16 +; CHECK-P8-NEXT: lfs f3, 4(r6) +; CHECK-P8-NEXT: xsaddsp f0, f1, f0 +; CHECK-P8-NEXT: xsaddsp f1, f3, f2 +; CHECK-P8-NEXT: lxvd2x vs2, r7, r8 +; CHECK-P8-NEXT: lxvd2x vs3, 0, r7 +; CHECK-P8-NEXT: addis r7, r2, .LC18@toc@ha +; CHECK-P8-NEXT: ld r7, .LC18@toc@l(r7) +; CHECK-P8-NEXT: stfsx f0, 0, r6 +; CHECK-P8-NEXT: stfs f1, 4(r6) +; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 +; CHECK-P8-NEXT: lfdx f1, 0, r7 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r8 +; CHECK-P8-NEXT: lfd f0, 40(r4) +; CHECK-P8-NEXT: xsadddp f0, f0, f1 +; CHECK-P8-NEXT: stfd f0, 40(r4) +; CHECK-P8-NEXT: blr +entry: +; Ensure that these are still widened to 8b + 4b + 2b + store i16 12, i16* %ArrS, align 2 + %arrayidx1 = getelementptr inbounds i16, i16* %ArrS, i64 1 + store i16 44, i16* %arrayidx1, align 2 + %arrayidx2 = getelementptr inbounds i16, i16* %ArrS, i64 2 + store i16 8, i16* %arrayidx2, align 2 + %arrayidx3 = getelementptr inbounds i16, i16* %ArrS, i64 3 + store i16 98, i16* %arrayidx3, align 2 + %arrayidx4 = getelementptr inbounds i16, i16* %ArrS, i64 4 + store i16 271, i16* %arrayidx4, align 2 + %arrayidx5 = getelementptr inbounds i16, i16* %ArrS, i64 5 + store i16 888, i16* %arrayidx5, align 2 + %arrayidx6 = getelementptr inbounds i16, i16* %ArrS, i64 6 + store i16 99, i16* %arrayidx6, align 2 +; These are not vectorized, check 4b alignment + %0 = load float, float* %ArrF, align 4 + %add = fadd fast float %0, 0x408F3F0A40000000 + store float %add, float* %ArrF, align 4 + %arrayidx8 = getelementptr inbounds float, float* %ArrF, i64 1 + %1 = load float, float* %arrayidx8, align 4 + %add9 = fadd fast float %1, 0x408AE93340000000 + store float %add9, float* %arrayidx8, align 4 +; These are vectorized, check 16b alignment + store <2 x double> , <2 x double>* %ArrV, align 16 + %arrayidx12 = getelementptr inbounds <2 x double>, <2 x double>* %ArrV, i64 1 + store <2 x double> , <2 x double>* %arrayidx12, align 16 +; Check 8b alignment + %arrayidx13 = getelementptr inbounds double, double* %ArrD, i64 5 + %2 = load double, double* %arrayidx13, align 8 + %add14 = fadd fast double %2, 0x40A2939884E831AD + store double %add14, double* %arrayidx13, align 8 + ret void +} + +; CHECK-P9: .section .data.rel.ro,"aw",@progbits +; CHECK-P9: .p2align 3 +; CHECK-P9-LABEL: .LCPI19_0: +; CHECK-P9-NEXT: .long 0x42b5cccd +; CHECK-P9-NEXT: .space 4 +; CHECK-P9-LABEL: .LCPI19_1: +; CHECK-P9-NEXT: .quad 0x4012333333333333 +define void @constant_pool_padding() { +; CHECK-LABEL: constant_pool_padding: +; CHECK: .localentry constant_pool_padding, 1 +; CHECK-NEXT: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -32(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: plfd f1, .LCPI19_0@PCREL(0), 1 +; CHECK-NEXT: xxspltidp vs2, 1119210701 +; CHECK-NEXT: # kill: def $f2 killed $f2 killed $vsl2 +; CHECK-NEXT: bl bar@notoc +; CHECK-NEXT: addi r1, r1, 32 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +; +; CHECK-P9-LABEL: constant_pool_padding: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mflr r0 +; CHECK-P9-NEXT: std r0, 16(r1) +; CHECK-P9-NEXT: stdu r1, -32(r1) +; CHECK-P9-NEXT: .cfi_def_cfa_offset 32 +; CHECK-P9-NEXT: .cfi_offset lr, 16 +; CHECK-P9-NEXT: addis r3, r2, .LC21@toc@ha +; CHECK-P9-NEXT: ld r3, .LC21@toc@l(r3) +; CHECK-P9-NEXT: lfd f1, 0(r3) +; CHECK-P9-NEXT: addis r3, r2, .LC22@toc@ha +; CHECK-P9-NEXT: ld r3, .LC22@toc@l(r3) +; CHECK-P9-NEXT: lfs f2, 0(r3) +; CHECK-P9-NEXT: bl bar +; CHECK-P9-NEXT: nop +; CHECK-P9-NEXT: addi r1, r1, 32 +; CHECK-P9-NEXT: ld r0, 16(r1) +; CHECK-P9-NEXT: mtlr r0 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: constant_pool_padding: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mflr r0 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -32(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 +; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: addis r3, r2, .LC19@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC20@toc@ha +; CHECK-P8-NEXT: ld r3, .LC19@toc@l(r3) +; CHECK-P8-NEXT: ld r4, .LC20@toc@l(r4) +; CHECK-P8-NEXT: lfdx f1, 0, r3 +; CHECK-P8-NEXT: lfsx f2, 0, r4 +; CHECK-P8-NEXT: bl bar +; CHECK-P8-NEXT: nop +; CHECK-P8-NEXT: addi r1, r1, 32 +; CHECK-P8-NEXT: ld r0, 16(r1) +; CHECK-P8-NEXT: mtlr r0 +; CHECK-P8-NEXT: blr +entry: + call void @bar(double 4.550000e+00, float 0x4056B999A0000000) + ret void +} +declare void @bar(double, float) + +; CHECK-P9: .section .toc,"aw",@progbits +; CHECK-P9-LABEL: .LC0: +; CHECK-P9-NEXT: .tc .LCPI0_0[TC],.LCPI0_0 +; CHECK-P9-LABEL: .LC1: +; CHECK-P9-NEXT: .tc .LCPI1_0[TC],.LCPI1_0 +; CHECK-P9-LABEL: .LC2: +; CHECK-P9-NEXT: .tc .LCPI2_0[TC],.LCPI2_0 +; CHECK-P9-LABEL: .LC3: +; CHECK-P9-NEXT: .tc .LCPI3_0[TC],.LCPI3_0 +; CHECK-P9-LABEL: .LC4: +; CHECK-P9-NEXT: .tc .LCPI4_0[TC],.LCPI4_0 +; CHECK-P9-LABEL: .LC5: +; CHECK-P9-NEXT: .tc .LCPI5_0[TC],.LCPI5_0 +; CHECK-P9-LABEL: .LC6: +; CHECK-P9-NEXT: .tc .LCPI6_0[TC],.LCPI6_0 +; CHECK-P9-LABEL: .LC7: +; CHECK-P9-NEXT: .tc .LCPI7_0[TC],.LCPI7_0 +; CHECK-P9-LABEL: .LC8: +; CHECK-P9-NEXT: .tc .LCPI8_0[TC],.LCPI8_0 +; CHECK-P9-LABEL: .LC9: +; CHECK-P9-NEXT: .tc .LCPI9_0[TC],.LCPI9_0 +; CHECK-P9-LABEL: .LC10: +; CHECK-P9-NEXT: .tc .LCPI10_0[TC],.LCPI10_0 +; CHECK-P9-LABEL: .LC11: +; CHECK-P9-NEXT: .tc .LCPI11_0[TC],.LCPI11_0 +; CHECK-P9-LABEL: .LC12: +; CHECK-P9-NEXT: .tc .LCPI12_0[TC],.LCPI12_0 +; CHECK-P9-LABEL: .LC13: +; CHECK-P9-NEXT: .tc .LCPI13_0[TC],.LCPI13_0 +; CHECK-P9-LABEL: .LC14: +; CHECK-P9-NEXT: .tc .LCPI14_0[TC],.LCPI14_0 +; CHECK-P9-LABEL: .LC15: +; CHECK-P9-NEXT: .tc .LCPI15_0[TC],.LCPI15_0 +; CHECK-P9-LABEL: .LC16: +; CHECK-P9-NEXT: .tc .LCPI16_0[TC],.LCPI16_0 +; CHECK-P9-LABEL: .LC17: +; CHECK-P9-NEXT: .tc .LCPI17_0[TC],.LCPI17_0 +; CHECK-P9-LABEL: .LC18: +; CHECK-P9-NEXT: .tc .LCPI18_2[TC],.LCPI18_2 +; CHECK-P9-LABEL: .LC19: +; CHECK-P9-NEXT: .tc .LCPI18_0[TC],.LCPI18_0 +; CHECK-P9-LABEL: .LC20: +; CHECK-P9-NEXT: .tc .LCPI18_1[TC],.LCPI18_1 +; CHECK-P9-LABEL: .LC21: +; CHECK-P9-NEXT: .tc .LCPI19_1[TC],.LCPI19_1 +; CHECK-P9-LABEL: .LC22: +; CHECK-P9-NEXT: .tc .LCPI19_0[TC],.LCPI19_0 diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll --- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll +++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll @@ -569,10 +569,10 @@ define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture %b) local_unnamed_addr #0 { ; CHECK-LABEL: test_stores_exceed_vec_size: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-NEXT: xxsldwi vs1, vs34, vs34, 1 ; CHECK-NEXT: li r4, 20 -; CHECK-NEXT: addi r3, r3, .LCPI16_0@toc@l +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NEXT: lvx v3, 0, r3 ; CHECK-NEXT: li r3, 16 ; CHECK-NEXT: vperm v3, v2, v2, v3 @@ -596,9 +596,9 @@ ; ; CHECK-P9-LABEL: test_stores_exceed_vec_size: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1 -; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l +; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: li r3, 16 ; CHECK-P9-NEXT: stfiwx f0, r5, r3 diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -529,15 +529,15 @@ ; CHECK-LABEL: sum_float128: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: std r4, 40(r1) -; CHECK-NEXT: addis r4, r2, .LCPI17_0@toc@ha +; CHECK-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-NEXT: cmpwi r3, 1 ; CHECK-NEXT: std r5, 48(r1) -; CHECK-NEXT: addi r4, r4, .LCPI17_0@toc@l +; CHECK-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r8, 72(r1) -; CHECK-NEXT: lxvx v2, 0, r4 ; CHECK-NEXT: std r9, 80(r1) +; CHECK-NEXT: lxvx v2, 0, r4 ; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: # %bb.1: # %if.end @@ -553,15 +553,15 @@ ; CHECK-BE-LABEL: sum_float128: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: std r4, 56(r1) -; CHECK-BE-NEXT: addis r4, r2, .LCPI17_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-BE-NEXT: cmpwi r3, 1 ; CHECK-BE-NEXT: std r5, 64(r1) -; CHECK-BE-NEXT: addi r4, r4, .LCPI17_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-NEXT: std r8, 88(r1) -; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: std r9, 96(r1) +; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-NEXT: bltlr cr0 ; CHECK-BE-NEXT: # %bb.1: # %if.end diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll --- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll +++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll @@ -9,8 +9,8 @@ define fp128 @loadConstant() { ; CHECK-LABEL: loadConstant: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: blr ; @@ -30,8 +30,8 @@ ; CHECK-LABEL: loadConstant2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsaddqp v2, v2, v3 -; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/float-logic-ops.ll b/llvm/test/CodeGen/PowerPC/float-logic-ops.ll --- a/llvm/test/CodeGen/PowerPC/float-logic-ops.ll +++ b/llvm/test/CodeGen/PowerPC/float-logic-ops.ll @@ -53,8 +53,8 @@ define <4 x float> @absv4f32_invalid(<4 x float> %a) { ; CHECK-LABEL: absv4f32_invalid: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NEXT: lvx v3, 0, r3 ; CHECK-NEXT: xxland vs34, vs34, vs35 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/fma-combine.ll b/llvm/test/CodeGen/PowerPC/fma-combine.ll --- a/llvm/test/CodeGen/PowerPC/fma-combine.ll +++ b/llvm/test/CodeGen/PowerPC/fma-combine.ll @@ -141,13 +141,12 @@ define float @fma_combine_no_ice() { ; CHECK-FAST-LABEL: fma_combine_no_ice: ; CHECK-FAST: # %bb.0: -; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-FAST-NEXT: addis 4, 2, .LCPI4_1@toc@ha -; CHECK-FAST-NEXT: lfs 0, .LCPI4_0@toc@l(3) +; CHECK-FAST-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-FAST-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-FAST-NEXT: lfs 0, 8(3) ; CHECK-FAST-NEXT: lfsx 2, 0, 3 -; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_2@toc@ha -; CHECK-FAST-NEXT: lfs 3, .LCPI4_1@toc@l(4) -; CHECK-FAST-NEXT: lfs 1, .LCPI4_2@toc@l(3) +; CHECK-FAST-NEXT: lfs 3, 4(3) +; CHECK-FAST-NEXT: lfsx 1, 0, 3 ; CHECK-FAST-NEXT: xsmaddasp 3, 2, 0 ; CHECK-FAST-NEXT: xsmaddasp 1, 2, 3 ; CHECK-FAST-NEXT: xsnmsubasp 1, 3, 2 @@ -155,27 +154,25 @@ ; ; CHECK-FAST-NOVSX-LABEL: fma_combine_no_ice: ; CHECK-FAST-NOVSX: # %bb.0: -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfs 0, .LCPI4_0@toc@l(3) -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfs 1, 0(3) -; CHECK-FAST-NOVSX-NEXT: lfs 2, .LCPI4_1@toc@l(3) -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_2@toc@ha -; CHECK-FAST-NOVSX-NEXT: fmadds 0, 1, 2, 0 -; CHECK-FAST-NOVSX-NEXT: lfs 2, .LCPI4_2@toc@l(3) -; CHECK-FAST-NOVSX-NEXT: fmadds 2, 1, 0, 2 -; CHECK-FAST-NOVSX-NEXT: fnmsubs 1, 0, 1, 2 +; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-FAST-NOVSX-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: lfs 0, 0(3) +; CHECK-FAST-NOVSX-NEXT: lfs 1, 4(3) +; CHECK-FAST-NOVSX-NEXT: lfs 2, 8(3) +; CHECK-FAST-NOVSX-NEXT: fmadds 1, 0, 2, 1 +; CHECK-FAST-NOVSX-NEXT: lfs 2, 0(3) +; CHECK-FAST-NOVSX-NEXT: fmadds 2, 0, 1, 2 +; CHECK-FAST-NOVSX-NEXT: fnmsubs 1, 1, 0, 2 ; CHECK-FAST-NOVSX-NEXT: blr ; ; CHECK-LABEL: fma_combine_no_ice: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI4_1@toc@ha -; CHECK-NEXT: lfs 0, .LCPI4_0@toc@l(3) +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: lfs 0, 8(3) ; CHECK-NEXT: lfsx 2, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI4_2@toc@ha -; CHECK-NEXT: lfs 3, .LCPI4_1@toc@l(4) -; CHECK-NEXT: lfs 1, .LCPI4_2@toc@l(3) +; CHECK-NEXT: lfs 3, 4(3) +; CHECK-NEXT: lfsx 1, 0, 3 ; CHECK-NEXT: fmr 4, 3 ; CHECK-NEXT: xsmaddasp 3, 2, 0 ; CHECK-NEXT: xsnmaddasp 4, 2, 0 @@ -201,10 +198,10 @@ define double @getNegatedExpression_crash(double %x, double %y) { ; CHECK-FAST-LABEL: getNegatedExpression_crash: ; CHECK-FAST: # %bb.0: -; CHECK-FAST-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; CHECK-FAST-NEXT: addis 4, 2, .LCPI5_0@toc@ha -; CHECK-FAST-NEXT: lfs 3, .LCPI5_1@toc@l(3) -; CHECK-FAST-NEXT: lfs 4, .LCPI5_0@toc@l(4) +; CHECK-FAST-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-FAST-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-FAST-NEXT: lfs 3, 4(3) +; CHECK-FAST-NEXT: lfsx 4, 0, 3 ; CHECK-FAST-NEXT: xssubdp 0, 1, 3 ; CHECK-FAST-NEXT: xsmaddadp 3, 1, 4 ; CHECK-FAST-NEXT: xsmaddadp 0, 3, 2 @@ -213,10 +210,10 @@ ; ; CHECK-FAST-NOVSX-LABEL: getNegatedExpression_crash: ; CHECK-FAST-NOVSX: # %bb.0: -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-FAST-NOVSX-NEXT: addis 4, 2, .LCPI5_1@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfs 0, .LCPI5_0@toc@l(3) -; CHECK-FAST-NOVSX-NEXT: lfs 3, .LCPI5_1@toc@l(4) +; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-FAST-NOVSX-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: lfs 0, 4(3) +; CHECK-FAST-NOVSX-NEXT: lfs 3, 0(3) ; CHECK-FAST-NOVSX-NEXT: fmadd 3, 1, 3, 0 ; CHECK-FAST-NOVSX-NEXT: fsub 0, 1, 0 ; CHECK-FAST-NOVSX-NEXT: fmadd 1, 3, 2, 0 @@ -224,10 +221,10 @@ ; ; CHECK-LABEL: getNegatedExpression_crash: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI5_0@toc@ha -; CHECK-NEXT: lfs 3, .LCPI5_1@toc@l(3) -; CHECK-NEXT: lfs 4, .LCPI5_0@toc@l(4) +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-NEXT: lfs 3, 4(3) +; CHECK-NEXT: lfsx 4, 0, 3 ; CHECK-NEXT: xssubdp 0, 1, 3 ; CHECK-NEXT: xsmaddadp 3, 1, 4 ; CHECK-NEXT: xsmaddadp 0, 3, 2 @@ -248,8 +245,9 @@ ; ; CHECK-FAST-NOVSX-LABEL: fma_flag_propagation: ; CHECK-FAST-NOVSX: # %bb.0: # %entry -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfs 1, .LCPI6_0@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-FAST-NOVSX-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: lfs 1, 0(3) ; CHECK-FAST-NOVSX-NEXT: blr ; ; CHECK-LABEL: fma_flag_propagation: @@ -270,8 +268,9 @@ ; ; CHECK-FAST-NOVSX-LABEL: neg_fma_flag_propagation: ; CHECK-FAST-NOVSX: # %bb.0: # %entry -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfs 1, .LCPI7_0@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-FAST-NOVSX-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: lfs 1, 0(3) ; CHECK-FAST-NOVSX-NEXT: blr ; ; CHECK-LABEL: neg_fma_flag_propagation: @@ -286,8 +285,8 @@ define <2 x double> @vec_neg_fma_flag_propagation(<2 x double> %a) { ; CHECK-FAST-LABEL: vec_neg_fma_flag_propagation: ; CHECK-FAST: # %bb.0: # %entry -; CHECK-FAST-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; CHECK-FAST-NEXT: addi 3, 3, .LCPI8_0@toc@l +; CHECK-FAST-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-FAST-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-FAST-NEXT: lxvd2x 0, 0, 3 ; CHECK-FAST-NEXT: xxswapd 0, 0 ; CHECK-FAST-NEXT: xvmaddadp 34, 34, 0 @@ -295,15 +294,16 @@ ; ; CHECK-FAST-NOVSX-LABEL: vec_neg_fma_flag_propagation: ; CHECK-FAST-NOVSX: # %bb.0: # %entry -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfs 1, .LCPI8_0@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-FAST-NOVSX-NEXT: ld 3, .LC4@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: lfs 1, 0(3) ; CHECK-FAST-NOVSX-NEXT: fmr 2, 1 ; CHECK-FAST-NOVSX-NEXT: blr ; ; CHECK-LABEL: vec_neg_fma_flag_propagation: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI8_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-NEXT: lxvd2x 0, 0, 3 ; CHECK-NEXT: xxswapd 0, 0 ; CHECK-NEXT: xvmaddadp 34, 34, 0 @@ -316,25 +316,27 @@ define double @fma_combine_const(double %a, double %b) { ; CHECK-FAST-LABEL: fma_combine_const: ; CHECK-FAST: # %bb.0: # %entry -; CHECK-FAST-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; CHECK-FAST-NEXT: lfd 0, .LCPI9_0@toc@l(3) +; CHECK-FAST-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-FAST-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-FAST-NEXT: lfdx 0, 0, 3 ; CHECK-FAST-NEXT: xsmaddadp 2, 1, 0 ; CHECK-FAST-NEXT: fmr 1, 2 ; CHECK-FAST-NEXT: blr ; ; CHECK-FAST-NOVSX-LABEL: fma_combine_const: ; CHECK-FAST-NOVSX: # %bb.0: # %entry -; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; CHECK-FAST-NOVSX-NEXT: lfd 0, .LCPI9_0@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-FAST-NOVSX-NEXT: ld 3, .LC5@toc@l(3) +; CHECK-FAST-NOVSX-NEXT: lfd 0, 0(3) ; CHECK-FAST-NOVSX-NEXT: fmadd 1, 1, 0, 2 ; CHECK-FAST-NOVSX-NEXT: blr ; ; CHECK-LABEL: fma_combine_const: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; CHECK-NEXT: lfd 0, .LCPI9_0@toc@l(3) -; CHECK-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; CHECK-NEXT: lfd 3, .LCPI9_1@toc@l(3) +; CHECK-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-NEXT: lfd 0, 8(3) +; CHECK-NEXT: lfdx 3, 0, 3 ; CHECK-NEXT: xsmuldp 0, 1, 0 ; CHECK-NEXT: fmr 1, 2 ; CHECK-NEXT: xsmaddadp 1, 0, 3 diff --git a/llvm/test/CodeGen/PowerPC/fma-mutate.ll b/llvm/test/CodeGen/PowerPC/fma-mutate.ll --- a/llvm/test/CodeGen/PowerPC/fma-mutate.ll +++ b/llvm/test/CodeGen/PowerPC/fma-mutate.ll @@ -13,10 +13,10 @@ ; CHECK-NEXT: bc 12, 2, .LBB0_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: xsrsqrtedp 0, 1 -; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-NEXT: lfs 3, .LCPI0_0@toc@l(3) -; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha -; CHECK-NEXT: lfs 4, .LCPI0_1@toc@l(3) +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: lfs 3, 4(3) +; CHECK-NEXT: lfs 4, 0(3) ; CHECK-NEXT: xsmuldp 2, 1, 0 ; CHECK-NEXT: xsmaddmdp 2, 0, 3 ; CHECK-NEXT: xsmuldp 0, 0, 4 diff --git a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll --- a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll +++ b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll @@ -164,15 +164,17 @@ define float @fmul_fma_reassoc1(float %x) { ; FMF-LABEL: fmul_fma_reassoc1: ; FMF: # %bb.0: -; FMF-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; FMF-NEXT: lfs 0, .LCPI6_0@toc@l(3) +; FMF-NEXT: addis 3, 2, .LC0@toc@ha +; FMF-NEXT: ld 3, .LC0@toc@l(3) +; FMF-NEXT: lfsx 0, 0, 3 ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: blr ; ; GLOBAL-LABEL: fmul_fma_reassoc1: ; GLOBAL: # %bb.0: -; GLOBAL-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; GLOBAL-NEXT: lfs 0, .LCPI6_0@toc@l(3) +; GLOBAL-NEXT: addis 3, 2, .LC0@toc@ha +; GLOBAL-NEXT: ld 3, .LC0@toc@l(3) +; GLOBAL-NEXT: lfsx 0, 0, 3 ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: blr %mul = fmul float %x, 42.0 @@ -193,15 +195,17 @@ define float @fmul_fma_reassoc2(float %x) { ; FMF-LABEL: fmul_fma_reassoc2: ; FMF: # %bb.0: -; FMF-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; FMF-NEXT: lfs 0, .LCPI7_0@toc@l(3) +; FMF-NEXT: addis 3, 2, .LC1@toc@ha +; FMF-NEXT: ld 3, .LC1@toc@l(3) +; FMF-NEXT: lfsx 0, 0, 3 ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: blr ; ; GLOBAL-LABEL: fmul_fma_reassoc2: ; GLOBAL: # %bb.0: -; GLOBAL-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; GLOBAL-NEXT: lfs 0, .LCPI7_0@toc@l(3) +; GLOBAL-NEXT: addis 3, 2, .LC1@toc@ha +; GLOBAL-NEXT: ld 3, .LC1@toc@l(3) +; GLOBAL-NEXT: lfsx 0, 0, 3 ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: blr %mul = fmul reassoc float %x, 42.0 @@ -222,15 +226,17 @@ define float @fmul_fma_fast1(float %x) { ; FMF-LABEL: fmul_fma_fast1: ; FMF: # %bb.0: -; FMF-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; FMF-NEXT: lfs 0, .LCPI8_0@toc@l(3) +; FMF-NEXT: addis 3, 2, .LC2@toc@ha +; FMF-NEXT: ld 3, .LC2@toc@l(3) +; FMF-NEXT: lfsx 0, 0, 3 ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: blr ; ; GLOBAL-LABEL: fmul_fma_fast1: ; GLOBAL: # %bb.0: -; GLOBAL-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; GLOBAL-NEXT: lfs 0, .LCPI8_0@toc@l(3) +; GLOBAL-NEXT: addis 3, 2, .LC2@toc@ha +; GLOBAL-NEXT: ld 3, .LC2@toc@l(3) +; GLOBAL-NEXT: lfsx 0, 0, 3 ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: blr %mul = fmul float %x, 42.0 @@ -251,15 +257,17 @@ define float @fmul_fma_fast2(float %x) { ; FMF-LABEL: fmul_fma_fast2: ; FMF: # %bb.0: -; FMF-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; FMF-NEXT: lfs 0, .LCPI9_0@toc@l(3) +; FMF-NEXT: addis 3, 2, .LC3@toc@ha +; FMF-NEXT: ld 3, .LC3@toc@l(3) +; FMF-NEXT: lfsx 0, 0, 3 ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: blr ; ; GLOBAL-LABEL: fmul_fma_fast2: ; GLOBAL: # %bb.0: -; GLOBAL-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; GLOBAL-NEXT: lfs 0, .LCPI9_0@toc@l(3) +; GLOBAL-NEXT: addis 3, 2, .LC3@toc@ha +; GLOBAL-NEXT: ld 3, .LC3@toc@l(3) +; GLOBAL-NEXT: lfsx 0, 0, 3 ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: blr %mul = fmul reassoc float %x, 42.0 @@ -280,18 +288,17 @@ define float @sqrt_afn_ieee(float %x) #0 { ; FMF-LABEL: sqrt_afn_ieee: ; FMF: # %bb.0: +; FMF-NEXT: addis 3, 2, .LC4@toc@ha ; FMF-NEXT: xsabsdp 0, 1 -; FMF-NEXT: addis 3, 2, .LCPI10_2@toc@ha -; FMF-NEXT: lfs 2, .LCPI10_2@toc@l(3) +; FMF-NEXT: ld 3, .LC4@toc@l(3) +; FMF-NEXT: lfsx 2, 0, 3 ; FMF-NEXT: fcmpu 0, 0, 2 ; FMF-NEXT: xxlxor 0, 0, 0 ; FMF-NEXT: blt 0, .LBB10_2 ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 -; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI10_1@toc@ha -; FMF-NEXT: lfs 2, .LCPI10_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI10_1@toc@l(4) +; FMF-NEXT: lfs 2, 4(3) +; FMF-NEXT: lfs 3, 8(3) ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 2 @@ -303,18 +310,17 @@ ; ; GLOBAL-LABEL: sqrt_afn_ieee: ; GLOBAL: # %bb.0: +; GLOBAL-NEXT: addis 3, 2, .LC4@toc@ha ; GLOBAL-NEXT: xsabsdp 0, 1 -; GLOBAL-NEXT: addis 3, 2, .LCPI10_2@toc@ha -; GLOBAL-NEXT: lfs 2, .LCPI10_2@toc@l(3) +; GLOBAL-NEXT: ld 3, .LC4@toc@l(3) +; GLOBAL-NEXT: lfsx 2, 0, 3 ; GLOBAL-NEXT: fcmpu 0, 0, 2 ; GLOBAL-NEXT: xxlxor 0, 0, 0 ; GLOBAL-NEXT: blt 0, .LBB10_2 ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 -; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI10_1@toc@ha -; GLOBAL-NEXT: lfs 2, .LCPI10_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI10_1@toc@l(4) +; GLOBAL-NEXT: lfs 2, 8(3) +; GLOBAL-NEXT: lfs 3, 4(3) ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 @@ -356,14 +362,14 @@ ; FMF-NEXT: beq 0, .LBB12_2 ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 -; FMF-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI12_1@toc@ha -; FMF-NEXT: lfs 2, .LCPI12_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI12_1@toc@l(4) +; FMF-NEXT: addis 3, 2, .LC5@toc@ha +; FMF-NEXT: ld 3, .LC5@toc@l(3) +; FMF-NEXT: lfs 2, 4(3) +; FMF-NEXT: lfsx 3, 0, 3 ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0 -; FMF-NEXT: xsmulsp 1, 1, 2 -; FMF-NEXT: xsaddsp 0, 0, 3 +; FMF-NEXT: xsmulsp 1, 1, 3 +; FMF-NEXT: xsaddsp 0, 0, 2 ; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: .LBB12_2: ; FMF-NEXT: fmr 1, 0 @@ -376,10 +382,10 @@ ; GLOBAL-NEXT: beq 0, .LBB12_2 ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 -; GLOBAL-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI12_1@toc@ha -; GLOBAL-NEXT: lfs 2, .LCPI12_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI12_1@toc@l(4) +; GLOBAL-NEXT: addis 3, 2, .LC5@toc@ha +; GLOBAL-NEXT: ld 3, .LC5@toc@l(3) +; GLOBAL-NEXT: lfs 2, 4(3) +; GLOBAL-NEXT: lfsx 3, 0, 3 ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 @@ -418,18 +424,17 @@ define float @sqrt_fast_ieee(float %x) #0 { ; FMF-LABEL: sqrt_fast_ieee: ; FMF: # %bb.0: +; FMF-NEXT: addis 3, 2, .LC6@toc@ha ; FMF-NEXT: xsabsdp 0, 1 -; FMF-NEXT: addis 3, 2, .LCPI14_2@toc@ha -; FMF-NEXT: lfs 2, .LCPI14_2@toc@l(3) +; FMF-NEXT: ld 3, .LC6@toc@l(3) +; FMF-NEXT: lfsx 2, 0, 3 ; FMF-NEXT: fcmpu 0, 0, 2 ; FMF-NEXT: xxlxor 0, 0, 0 ; FMF-NEXT: blt 0, .LBB14_2 ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 -; FMF-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI14_1@toc@ha -; FMF-NEXT: lfs 2, .LCPI14_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI14_1@toc@l(4) +; FMF-NEXT: lfs 2, 8(3) +; FMF-NEXT: lfs 3, 4(3) ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmaddasp 2, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 3 @@ -440,18 +445,17 @@ ; ; GLOBAL-LABEL: sqrt_fast_ieee: ; GLOBAL: # %bb.0: +; GLOBAL-NEXT: addis 3, 2, .LC6@toc@ha ; GLOBAL-NEXT: xsabsdp 0, 1 -; GLOBAL-NEXT: addis 3, 2, .LCPI14_2@toc@ha -; GLOBAL-NEXT: lfs 2, .LCPI14_2@toc@l(3) +; GLOBAL-NEXT: ld 3, .LC6@toc@l(3) +; GLOBAL-NEXT: lfsx 2, 0, 3 ; GLOBAL-NEXT: fcmpu 0, 0, 2 ; GLOBAL-NEXT: xxlxor 0, 0, 0 ; GLOBAL-NEXT: blt 0, .LBB14_2 ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 -; GLOBAL-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI14_1@toc@ha -; GLOBAL-NEXT: lfs 2, .LCPI14_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI14_1@toc@l(4) +; GLOBAL-NEXT: lfs 2, 8(3) +; GLOBAL-NEXT: lfs 3, 4(3) ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 @@ -481,10 +485,10 @@ ; FMF-NEXT: beq 0, .LBB15_2 ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 -; FMF-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI15_1@toc@ha -; FMF-NEXT: lfs 2, .LCPI15_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI15_1@toc@l(4) +; FMF-NEXT: addis 3, 2, .LC7@toc@ha +; FMF-NEXT: ld 3, .LC7@toc@l(3) +; FMF-NEXT: lfs 2, 4(3) +; FMF-NEXT: lfsx 3, 0, 3 ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmaddasp 2, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 3 @@ -500,10 +504,10 @@ ; GLOBAL-NEXT: beq 0, .LBB15_2 ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 -; GLOBAL-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI15_1@toc@ha -; GLOBAL-NEXT: lfs 2, .LCPI15_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI15_1@toc@l(4) +; GLOBAL-NEXT: addis 3, 2, .LC7@toc@ha +; GLOBAL-NEXT: ld 3, .LC7@toc@l(3) +; GLOBAL-NEXT: lfs 2, 4(3) +; GLOBAL-NEXT: lfsx 3, 0, 3 ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll --- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll +++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll @@ -613,13 +613,14 @@ ; P8-NEXT: .cfi_def_cfa_offset 128 ; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset r30, -16 -; P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha +; P8-NEXT: addis r3, r2, .LC0@toc@ha ; P8-NEXT: xxlxor f3, f3, f3 ; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill -; P8-NEXT: lfs f0, .LCPI13_0@toc@l(r3) +; P8-NEXT: ld r3, .LC0@toc@l(r3) ; P8-NEXT: fcmpo cr0, f2, f3 -; P8-NEXT: lis r3, -32768 ; P8-NEXT: xxlxor f3, f3, f3 +; P8-NEXT: lfsx f0, 0, r3 +; P8-NEXT: lis r3, -32768 ; P8-NEXT: fcmpo cr1, f1, f0 ; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt ; P8-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq @@ -656,13 +657,14 @@ ; P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P9-NEXT: std r0, 16(r1) ; P9-NEXT: stdu r1, -48(r1) -; P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha +; P9-NEXT: addis r3, r2, .LC0@toc@ha ; P9-NEXT: xxlxor f3, f3, f3 -; P9-NEXT: lfs f0, .LCPI13_0@toc@l(r3) +; P9-NEXT: ld r3, .LC0@toc@l(r3) ; P9-NEXT: fcmpo cr1, f2, f3 +; P9-NEXT: xxlxor f3, f3, f3 +; P9-NEXT: lfs f0, 0(r3) ; P9-NEXT: lis r3, -32768 ; P9-NEXT: fcmpo cr0, f1, f0 -; P9-NEXT: xxlxor f3, f3, f3 ; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt ; P9-NEXT: crandc 4*cr5+gt, lt, eq ; P9-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt @@ -699,10 +701,10 @@ ; NOVSX-NEXT: .cfi_def_cfa_offset 48 ; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset cr2, 8 -; NOVSX-NEXT: addis r3, r2, .LCPI13_0@toc@ha -; NOVSX-NEXT: addis r4, r2, .LCPI13_1@toc@ha -; NOVSX-NEXT: lfs f0, .LCPI13_0@toc@l(r3) -; NOVSX-NEXT: lfs f4, .LCPI13_1@toc@l(r4) +; NOVSX-NEXT: addis r3, r2, .LC0@toc@ha +; NOVSX-NEXT: ld r3, .LC0@toc@l(r3) +; NOVSX-NEXT: lfs f0, 0(r3) +; NOVSX-NEXT: lfs f4, 4(r3) ; NOVSX-NEXT: fcmpo cr0, f1, f0 ; NOVSX-NEXT: fcmpo cr1, f2, f4 ; NOVSX-NEXT: fmr f3, f4 @@ -836,10 +838,11 @@ ; NOVSX: # %bb.0: # %entry ; NOVSX-NEXT: addi r4, r1, -4 ; NOVSX-NEXT: stw r3, -4(r1) -; NOVSX-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; NOVSX-NEXT: addis r3, r2, .LC1@toc@ha ; NOVSX-NEXT: lfiwax f0, 0, r4 -; NOVSX-NEXT: lfs f2, .LCPI16_0@toc@l(r3) +; NOVSX-NEXT: ld r3, .LC1@toc@l(r3) ; NOVSX-NEXT: fcfid f1, f0 +; NOVSX-NEXT: lfs f2, 0(r3) ; NOVSX-NEXT: blr entry: %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 @@ -865,10 +868,11 @@ ; NOVSX: # %bb.0: # %entry ; NOVSX-NEXT: addi r4, r1, -4 ; NOVSX-NEXT: stw r3, -4(r1) -; NOVSX-NEXT: addis r3, r2, .LCPI17_0@toc@ha +; NOVSX-NEXT: addis r3, r2, .LC2@toc@ha ; NOVSX-NEXT: lfiwax f0, 0, r4 -; NOVSX-NEXT: lfs f2, .LCPI17_0@toc@l(r3) +; NOVSX-NEXT: ld r3, .LC2@toc@l(r3) ; NOVSX-NEXT: fcfid f1, f0 +; NOVSX-NEXT: lfs f2, 0(r3) ; NOVSX-NEXT: blr entry: %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll --- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll +++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll @@ -65,10 +65,11 @@ ; ; PPC64-LABEL: fooul: ; PPC64: # %bb.0: # %entry -; PPC64-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; PPC64-NEXT: addis 3, 2, .LC0@toc@ha ; PPC64-NEXT: li 4, 1 -; PPC64-NEXT: lfs 0, .LCPI2_0@toc@l(3) +; PPC64-NEXT: ld 3, .LC0@toc@l(3) ; PPC64-NEXT: sldi 4, 4, 63 +; PPC64-NEXT: lfs 0, 0(3) ; PPC64-NEXT: fsubs 2, 1, 0 ; PPC64-NEXT: fcmpu 0, 1, 0 ; PPC64-NEXT: fctidz 2, 2 @@ -147,10 +148,11 @@ ; ; PPC64-LABEL: fooudl: ; PPC64: # %bb.0: # %entry -; PPC64-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; PPC64-NEXT: addis 3, 2, .LC1@toc@ha ; PPC64-NEXT: li 4, 1 -; PPC64-NEXT: lfs 0, .LCPI3_0@toc@l(3) +; PPC64-NEXT: ld 3, .LC1@toc@l(3) ; PPC64-NEXT: sldi 4, 4, 63 +; PPC64-NEXT: lfs 0, 0(3) ; PPC64-NEXT: fsub 2, 1, 0 ; PPC64-NEXT: fcmpu 0, 1, 0 ; PPC64-NEXT: fctidz 2, 2 @@ -170,12 +172,13 @@ ; PPC64-NEXT: rldicl 5, 3, 32, 32 ; PPC64-NEXT: clrldi 3, 3, 32 ; PPC64-NEXT: or 4, 5, 4 -; PPC64-NEXT: addis 5, 2, .LCPI3_1@toc@ha +; PPC64-NEXT: addis 5, 2, .LC2@toc@ha +; PPC64-NEXT: ld 5, .LC2@toc@l(5) ; PPC64-NEXT: std 4, -24(1) ; PPC64-NEXT: li 4, 1075 ; PPC64-NEXT: sldi 4, 4, 52 ; PPC64-NEXT: or 3, 3, 4 -; PPC64-NEXT: lfd 0, .LCPI3_1@toc@l(5) +; PPC64-NEXT: lfd 0, 0(5) ; PPC64-NEXT: std 3, -32(1) ; PPC64-NEXT: lfd 1, -24(1) ; PPC64-NEXT: lfd 2, -32(1) diff --git a/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll b/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll --- a/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll +++ b/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll @@ -1231,8 +1231,9 @@ ; P8-NEXT: fcmpu cr0, f1, f0 ; P8-NEXT: beq cr0, .LBB20_2 ; P8-NEXT: # %bb.1: -; P8-NEXT: addis r3, r2, .LCPI20_0@toc@ha -; P8-NEXT: lfs f0, .LCPI20_0@toc@l(r3) +; P8-NEXT: addis r3, r2, .LC0@toc@ha +; P8-NEXT: ld r3, .LC0@toc@l(r3) +; P8-NEXT: lfsx f0, 0, r3 ; P8-NEXT: .LBB20_2: ; P8-NEXT: fmr f1, f0 ; P8-NEXT: addi r1, r1, 32 @@ -1250,8 +1251,9 @@ ; CHECK-NEXT: fcmpu cr0, f0, f1 ; CHECK-NEXT: beqlr cr0 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: addis r3, r2, .LCPI20_0@toc@ha -; CHECK-NEXT: lfs f1, .LCPI20_0@toc@l(r3) +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: blr ; ; SOFT-LABEL: PR40273: diff --git a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll --- a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll +++ b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll @@ -70,9 +70,9 @@ define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) { ; CHECK-P8-LABEL: load_swap10: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -84,9 +84,9 @@ ; ; CHECK-P8-BE-LABEL: load_swap10: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-P8-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 -; CHECK-P8-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-P8-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r4 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr @@ -94,8 +94,8 @@ ; CHECK-P9-BE-LABEL: load_swap10: ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr @@ -108,9 +108,9 @@ define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) { ; CHECK-P8-LABEL: load_swap11: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-P8-NEXT: addis r3, r2, .LC1@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l +; CHECK-P8-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -122,18 +122,18 @@ ; ; CHECK-P8-BE-LABEL: load_swap11: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-P8-BE-NEXT: addis r3, r2, .LC1@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r4 -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l +; CHECK-P8-BE-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr ; ; CHECK-P9-BE-LABEL: load_swap11: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-P9-BE-NEXT: addis r3, r2, .LC1@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l +; CHECK-P9-BE-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr @@ -146,9 +146,9 @@ define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){ ; CHECK-P8-LABEL: load_swap20: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -160,9 +160,9 @@ ; ; CHECK-P8-BE-LABEL: load_swap20: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha +; CHECK-P8-BE-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 -; CHECK-P8-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l +; CHECK-P8-BE-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r4 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr @@ -170,8 +170,8 @@ ; CHECK-P9-BE-LABEL: load_swap20: ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr @@ -184,9 +184,9 @@ define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){ ; CHECK-P8-LABEL: load_swap21: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-P8-NEXT: addis r3, r2, .LC3@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-P8-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -198,18 +198,18 @@ ; ; CHECK-P8-BE-LABEL: load_swap21: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-P8-BE-NEXT: addis r3, r2, .LC3@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r4 -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-P8-BE-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr ; ; CHECK-P9-BE-LABEL: load_swap21: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-P9-BE-NEXT: addis r3, r2, .LC3@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-P9-BE-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr @@ -222,9 +222,9 @@ define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){ ; CHECK-P8-LABEL: load_swap30: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -236,9 +236,9 @@ ; ; CHECK-P8-BE-LABEL: load_swap30: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha +; CHECK-P8-BE-NEXT: addis r4, r2, .LC4@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 -; CHECK-P8-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-P8-BE-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r4 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr @@ -257,9 +257,9 @@ define <16 x i8> @load_swap31(<16 x i8>* %vp1, <16 x i8>* %vp2){ ; CHECK-P8-LABEL: load_swap31: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; CHECK-P8-NEXT: addis r3, r2, .LC5@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addi r3, r3, .LCPI7_0@toc@l +; CHECK-P8-NEXT: ld r3, .LC5@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -271,9 +271,9 @@ ; ; CHECK-P8-BE-LABEL: load_swap31: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; CHECK-P8-BE-NEXT: addis r3, r2, .LC5@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r4 -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI7_0@toc@l +; CHECK-P8-BE-NEXT: ld r3, .LC5@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr @@ -320,9 +320,9 @@ define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) { ; CHECK-P8-LABEL: load_swap50: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r4, r2, .LCPI9_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI9_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -334,9 +334,9 @@ ; ; CHECK-P8-BE-LABEL: load_swap50: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r4, r2, .LCPI9_0@toc@ha +; CHECK-P8-BE-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 -; CHECK-P8-BE-NEXT: addi r4, r4, .LCPI9_0@toc@l +; CHECK-P8-BE-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r4 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr @@ -344,8 +344,8 @@ ; CHECK-P9-BE-LABEL: load_swap50: ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI9_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr @@ -358,9 +358,9 @@ define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) { ; CHECK-P8-LABEL: load_swap51: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; CHECK-P8-NEXT: addis r3, r2, .LC7@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addi r3, r3, .LCPI10_0@toc@l +; CHECK-P8-NEXT: ld r3, .LC7@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: blr @@ -372,18 +372,18 @@ ; ; CHECK-P8-BE-LABEL: load_swap51: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; CHECK-P8-BE-NEXT: addis r3, r2, .LC7@toc@ha ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r4 -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l +; CHECK-P8-BE-NEXT: ld r3, .LC7@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: blr ; ; CHECK-P9-BE-LABEL: load_swap51: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; CHECK-P9-BE-NEXT: addis r3, r2, .LC5@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l +; CHECK-P9-BE-NEXT: ld r3, .LC5@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr @@ -450,8 +450,8 @@ define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) { ; CHECK-P8-LABEL: swap_store10: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI13_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha +; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -464,8 +464,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store10: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC8@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -473,8 +473,8 @@ ; ; CHECK-P9-BE-LABEL: swap_store10: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC6@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC6@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) @@ -487,8 +487,8 @@ define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) { ; CHECK-P8-LABEL: swap_store11: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI14_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI14_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC9@toc@ha +; CHECK-P8-NEXT: ld r3, .LC9@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -501,8 +501,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store11: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC9@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC9@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -510,8 +510,8 @@ ; ; CHECK-P9-BE-LABEL: swap_store11: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC7@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC7@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) @@ -524,8 +524,8 @@ define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) { ; CHECK-P8-LABEL: swap_store20: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC10@toc@ha +; CHECK-P8-NEXT: ld r3, .LC10@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -538,8 +538,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store20: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC10@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC10@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -547,8 +547,8 @@ ; ; CHECK-P9-BE-LABEL: swap_store20: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC8@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) @@ -561,8 +561,8 @@ define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) { ; CHECK-P8-LABEL: swap_store21: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI16_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC11@toc@ha +; CHECK-P8-NEXT: ld r3, .LC11@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -575,8 +575,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store21: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC11@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC11@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -584,8 +584,8 @@ ; ; CHECK-P9-BE-LABEL: swap_store21: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC9@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC9@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) @@ -598,8 +598,8 @@ define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) { ; CHECK-P8-LABEL: swap_store30: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI17_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI17_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC12@toc@ha +; CHECK-P8-NEXT: ld r3, .LC12@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -612,8 +612,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store30: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI17_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC12@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC12@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -632,8 +632,8 @@ define void @swap_store31(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) { ; CHECK-P8-LABEL: swap_store31: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI18_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI18_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC13@toc@ha +; CHECK-P8-NEXT: ld r3, .LC13@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -646,8 +646,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store31: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI18_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC13@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC13@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -720,8 +720,8 @@ define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) { ; CHECK-P8-LABEL: swap_store50: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI21_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI21_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC14@toc@ha +; CHECK-P8-NEXT: ld r3, .LC14@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -734,8 +734,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store50: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC14@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC14@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -743,8 +743,8 @@ ; ; CHECK-P9-BE-LABEL: swap_store50: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC10@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC10@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) @@ -757,8 +757,8 @@ define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) { ; CHECK-P8-LABEL: swap_store51: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis r3, r2, .LCPI22_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI22_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC15@toc@ha +; CHECK-P8-NEXT: ld r3, .LC15@toc@l(r3) ; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: stvx v2, 0, r7 @@ -771,8 +771,8 @@ ; ; CHECK-P8-BE-LABEL: swap_store51: ; CHECK-P8-BE: # %bb.0: -; CHECK-P8-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha -; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l +; CHECK-P8-BE-NEXT: addis r3, r2, .LC15@toc@ha +; CHECK-P8-BE-NEXT: ld r3, .LC15@toc@l(r3) ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 @@ -780,8 +780,8 @@ ; ; CHECK-P9-BE-LABEL: swap_store51: ; CHECK-P9-BE: # %bb.0: -; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha -; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l +; CHECK-P9-BE-NEXT: addis r3, r2, .LC11@toc@ha +; CHECK-P9-BE-NEXT: ld r3, .LC11@toc@l(r3) ; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) diff --git a/llvm/test/CodeGen/PowerPC/mcm-12.ll b/llvm/test/CodeGen/PowerPC/mcm-12.ll --- a/llvm/test/CodeGen/PowerPC/mcm-12.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-12.ll @@ -16,20 +16,29 @@ ret double 0x3F4FD4920B498CF0 } -; CHECK: [[VAR:[a-z0-9A-Z_.]+]]: +; CHECK: [[LCPI:[a-z0-9A-Z_.]+]]: ; CHECK: .quad 0x3f4fd4920b498cf0 ; CHECK-LABEL: test_double_const: -; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) +; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; CHECK: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) +; CHECK: lfd {{[0-9]+}}, 0([[REG2]]) +; CHECK: [[VAR]]: +; CHECK: .tc [[LCPI]][TC],[[LCPI]] -; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]: +; CHECK-VSX: [[LCPI:[a-z0-9A-Z_.]+]]: ; CHECK-VSX: .quad 0x3f4fd4920b498cf0 ; CHECK-VSX-LABEL: test_double_const: -; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; CHECK-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l({{[0-9]+}}) +; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; CHECK-VSX: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) +; CHECK-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] +; CHECK-VSX: [[VAR]]: +; CHECK-VSX: .tc [[LCPI]][TC],[[LCPI]] -; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]: +; CHECK-P9: [[LCPI:[a-z0-9A-Z_.]+]]: ; CHECK-P9: .quad 0x3f4fd4920b498cf0 ; CHECK-P9-LABEL: test_double_const: -; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) +; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; CHECK-P9: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) +; CHECK-P9: lfd {{[0-9]+}}, 0([[REG2]]) +; CHECK-P9: [[VAR]]: +; CHECK-P9: .tc [[LCPI]][TC],[[LCPI]] diff --git a/llvm/test/CodeGen/PowerPC/mcm-4.ll b/llvm/test/CodeGen/PowerPC/mcm-4.ll --- a/llvm/test/CodeGen/PowerPC/mcm-4.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-4.ll @@ -22,18 +22,23 @@ ret double 0x3F4FD4920B498CF0 } -; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]: +; MEDIUM: [[LCPI:[a-z0-9A-Z_.]+]]: ; MEDIUM: .quad 0x3f4fd4920b498cf0 ; MEDIUM-LABEL: test_double_const: -; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l +; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; MEDIUM: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) +; MEDIUM: [[VAR]]: +; MEDIUM: .tc [[LCPI]][TC],[[LCPI]] -; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: +; MEDIUM-VSX: [[LCPI:[a-z0-9A-Z_.]+]]: ; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0 ; MEDIUM-VSX-LABEL: test_double_const: -; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) +; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; MEDIUM-VSX: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) +; MEDIUM-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] +; MEDIUM-VSX: [[VAR]]: +; MEDIUM-VSX: .tc [[LCPI]][TC],[[LCPI]] ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: .quad 0x3f4fd4920b498cf0 @@ -49,12 +54,14 @@ ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] -; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: +; MEDIUM-P9: [[LCPI:[a-z0-9A-Z_.]+]]: ; MEDIUM-P9: .quad 0x3f4fd4920b498cf0 ; MEDIUM-P9-LABEL: test_double_const: -; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l +; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; MEDIUM-P9: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) +; MEDIUM-P9: [[VAR]]: +; MEDIUM-P9: .tc [[LCPI]][TC],[[LCPI]] ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE-P9: .quad 0x3f4fd4920b498cf0 diff --git a/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll b/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll --- a/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll @@ -47,8 +47,8 @@ ret double 0x3F4FD4920B498CF0 } -; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for +; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing a constant. ; ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]] -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]] +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]] diff --git a/llvm/test/CodeGen/PowerPC/mcm-obj.ll b/llvm/test/CodeGen/PowerPC/mcm-obj.ll --- a/llvm/test/CodeGen/PowerPC/mcm-obj.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-obj.ll @@ -86,11 +86,11 @@ ret double 0x3F4FD4920B498CF0 } -; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for +; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing a constant. ; ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]] -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]] ; ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing a constant. diff --git a/llvm/test/CodeGen/PowerPC/nofpexcept.ll b/llvm/test/CodeGen/PowerPC/nofpexcept.ll --- a/llvm/test/CodeGen/PowerPC/nofpexcept.ll +++ b/llvm/test/CodeGen/PowerPC/nofpexcept.ll @@ -99,8 +99,9 @@ ; CHECK: %16:vsfrc = nofpexcept XSCVDPSXWS killed %15, implicit $rm ; CHECK: [[MFVSRWZ2:%[0-9]+]]:gprc = MFVSRWZ killed %16 ; CHECK: STW killed [[MFVSRWZ2]], 0, [[COPY1]] :: (volatile store 4 into %ir.addr1) - ; CHECK: [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0 - ; CHECK: [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load 4 from constant-pool) + ; CHECK: [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, target-flags(ppc-got) %const.0 + ; CHECK: [[LDtocL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocL target-flags(ppc-got) %const.0, killed [[ADDIStocHA8_]] :: (load 8 from got) + ; CHECK: [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 0, killed [[LDtocL]] :: (load 4 from constant-pool) ; CHECK: [[COPY9:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]] ; CHECK: [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY9]] ; CHECK: [[COPY10:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq @@ -132,10 +133,10 @@ ; CHECK: [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm ; CHECK: MTFSB1 31, implicit-def $rm ; CHECK: MTFSB0 30, implicit-def $rm - ; CHECK: %37:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm + ; CHECK: %38:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm ; CHECK: MTFSFb 1, [[MFFS1]], implicit-def $rm - ; CHECK: %38:vsfrc = nofpexcept XSCVDPSXWS killed %37, implicit $rm - ; CHECK: [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %38 + ; CHECK: %39:vsfrc = nofpexcept XSCVDPSXWS killed %38, implicit $rm + ; CHECK: [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %39 ; CHECK: [[XOR:%[0-9]+]]:gprc = XOR killed [[MFVSRWZ3]], killed [[ISEL]] ; CHECK: STW killed [[XOR]], 0, [[COPY1]] :: (volatile store 4 into %ir.addr1) ; CHECK: BLR8 implicit $lr8, implicit $rm diff --git a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll --- a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll +++ b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll @@ -22,11 +22,10 @@ ; ; CHECK-NOPCREL-LABEL: testDoubleToDoubleFail: ; CHECK-NOPCREL: # %bb.0: # %entry -; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-NOPCREL-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-NOPCREL-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NOPCREL-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NOPCREL-NEXT: lxvx vs34, 0, r3 ; CHECK-NOPCREL-NEXT: blr - entry: ret <2 x double> } @@ -39,11 +38,10 @@ ; ; CHECK-NOPCREL-LABEL: testFloatDenormToDouble: ; CHECK-NOPCREL: # %bb.0: # %entry -; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-NOPCREL-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-NOPCREL-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-NOPCREL-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-NOPCREL-NEXT: lxvx vs34, 0, r3 ; CHECK-NOPCREL-NEXT: blr - entry: ret <2 x double> } @@ -56,11 +54,10 @@ ; ; CHECK-NOPCREL-LABEL: testDoubleToDoubleNaNFail: ; CHECK-NOPCREL: # %bb.0: # %entry -; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-NOPCREL-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-NOPCREL-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-NOPCREL-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-NOPCREL-NEXT: lxvx vs34, 0, r3 ; CHECK-NOPCREL-NEXT: blr - entry: ret <2 x double> } @@ -73,10 +70,10 @@ ; ; CHECK-NOPCREL-LABEL: testDoubleNonRepresentableScalar: ; CHECK-NOPCREL: # %bb.0: # %entry -; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI3_0@toc@ha -; CHECK-NOPCREL-NEXT: lfd f1, .LCPI3_0@toc@l(r3) +; CHECK-NOPCREL-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-NOPCREL-NEXT: ld r3, .LC3@toc@l(r3) +; CHECK-NOPCREL-NEXT: lfd f1, 0(r3) ; CHECK-NOPCREL-NEXT: blr - entry: ret double 3.423300e+02 } @@ -89,10 +86,10 @@ ; ; CHECK-NOPCREL-LABEL: testFloatDenormScalar: ; CHECK-NOPCREL: # %bb.0: # %entry -; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-NOPCREL-NEXT: lfs f1, .LCPI4_0@toc@l(r3) +; CHECK-NOPCREL-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-NOPCREL-NEXT: ld r3, .LC4@toc@l(r3) +; CHECK-NOPCREL-NEXT: lfs f1, 0(r3) ; CHECK-NOPCREL-NEXT: blr - entry: ret float 0x380B38FB80000000 } @@ -105,10 +102,10 @@ ; ; CHECK-NOPCREL-LABEL: testFloatDenormToDoubleScalar: ; CHECK-NOPCREL: # %bb.0: # %entry -; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-NOPCREL-NEXT: lfs f1, .LCPI5_0@toc@l(r3) +; CHECK-NOPCREL-NEXT: addis r3, r2, .LC5@toc@ha +; CHECK-NOPCREL-NEXT: ld r3, .LC5@toc@l(r3) +; CHECK-NOPCREL-NEXT: lfs f1, 0(r3) ; CHECK-NOPCREL-NEXT: blr - entry: ret double 0x380B38FB80000000 } diff --git a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll --- a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll +++ b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll @@ -32,8 +32,8 @@ ; ; CHECK-BE-LABEL: test_vrlq_cost_mult8: ; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vrlq v2, v3, v2 ; CHECK-BE-NEXT: blr @@ -53,8 +53,8 @@ ; ; CHECK-BE-LABEL: test_vrlq_cost_non_mult8: ; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-BE-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-BE-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vrlq v2, v3, v2 ; CHECK-BE-NEXT: blr @@ -88,8 +88,8 @@ ; ; CHECK-BE-LABEL: test_vrlqnm: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-BE-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-BE-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-BE-NEXT: lxvx v5, 0, r3 ; CHECK-BE-NEXT: vperm v3, v3, v4, v5 ; CHECK-BE-NEXT: vrlqnm v2, v2, v3 diff --git a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll --- a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll +++ b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll @@ -449,8 +449,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-BE-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -462,8 +462,8 @@ define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) { ; CHECK-LABEL: shuffle_vector_halfword_1_3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -480,8 +480,8 @@ define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) { ; CHECK-LABEL: shuffle_vector_halfword_2_3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC1@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -503,8 +503,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-BE-NEXT: ld 3, .LC1@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -516,8 +516,8 @@ define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) { ; CHECK-LABEL: shuffle_vector_halfword_4_3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -534,8 +534,8 @@ define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) { ; CHECK-LABEL: shuffle_vector_halfword_5_3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -557,8 +557,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -575,8 +575,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-BE-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1453,8 +1453,8 @@ define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_0_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1476,8 +1476,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_1_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-BE-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1494,8 +1494,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_2_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-BE-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1507,8 +1507,8 @@ define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_3_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1525,8 +1525,8 @@ define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_4_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC6@toc@ha +; CHECK-NEXT: ld 3, .LC6@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1548,8 +1548,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_5_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC6@toc@ha +; CHECK-BE-NEXT: ld 3, .LC6@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1566,8 +1566,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_6_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC7@toc@ha +; CHECK-BE-NEXT: ld 3, .LC7@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1584,8 +1584,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_7_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC8@toc@ha +; CHECK-BE-NEXT: ld 3, .LC8@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1597,8 +1597,8 @@ define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_8_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC7@toc@ha +; CHECK-NEXT: ld 3, .LC7@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1615,8 +1615,8 @@ define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_9_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC8@toc@ha +; CHECK-NEXT: ld 3, .LC8@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1633,8 +1633,8 @@ define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_10_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC9@toc@ha +; CHECK-NEXT: ld 3, .LC9@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1656,8 +1656,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_11_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC9@toc@ha +; CHECK-BE-NEXT: ld 3, .LC9@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1674,8 +1674,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_12_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC10@toc@ha +; CHECK-BE-NEXT: ld 3, .LC10@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr @@ -1687,8 +1687,8 @@ define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_13_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC10@toc@ha +; CHECK-NEXT: ld 3, .LC10@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1705,8 +1705,8 @@ define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) { ; CHECK-LABEL: shuffle_vector_byte_14_7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC11@toc@ha +; CHECK-NEXT: ld 3, .LC11@toc@l(3) ; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr @@ -1728,8 +1728,8 @@ ; ; CHECK-BE-LABEL: shuffle_vector_byte_15_8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l +; CHECK-BE-NEXT: addis 3, 2, .LC11@toc@ha +; CHECK-BE-NEXT: ld 3, .LC11@toc@l(3) ; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll --- a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll @@ -1123,8 +1123,9 @@ ; ; PC64-LABEL: test_fpext_ppc_fp128_f32: ; PC64: # %bb.0: # %entry -; PC64-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PC64-NEXT: lfs 2, .LCPI26_0@toc@l(3) +; PC64-NEXT: addis 3, 2, .LC0@toc@ha +; PC64-NEXT: ld 3, .LC0@toc@l(3) +; PC64-NEXT: lfs 2, 0(3) ; PC64-NEXT: blr entry: %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f32.ppcf128( @@ -1146,8 +1147,9 @@ ; ; PC64-LABEL: test_fpext_ppc_fp128_f64: ; PC64: # %bb.0: # %entry -; PC64-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PC64-NEXT: lfs 2, .LCPI27_0@toc@l(3) +; PC64-NEXT: addis 3, 2, .LC1@toc@ha +; PC64-NEXT: ld 3, .LC1@toc@l(3) +; PC64-NEXT: lfs 2, 0(3) ; PC64-NEXT: blr entry: %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f64.ppcf128( @@ -1290,12 +1292,13 @@ ; PC64LE-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC0@toc@ha ; PC64LE-NEXT: xxlxor 3, 3, 3 -; PC64LE-NEXT: lfs 0, .LCPI31_0@toc@l(3) +; PC64LE-NEXT: ld 3, .LC0@toc@l(3) ; PC64LE-NEXT: fcmpo 0, 2, 3 -; PC64LE-NEXT: lis 3, -32768 ; PC64LE-NEXT: xxlxor 3, 3, 3 +; PC64LE-NEXT: lfsx 0, 0, 3 +; PC64LE-NEXT: lis 3, -32768 ; PC64LE-NEXT: fcmpo 1, 1, 0 ; PC64LE-NEXT: crand 20, 6, 0 ; PC64LE-NEXT: crandc 21, 4, 6 @@ -1328,13 +1331,14 @@ ; PC64LE9-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI31_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC0@toc@ha ; PC64LE9-NEXT: xxlxor 3, 3, 3 -; PC64LE9-NEXT: lfs 0, .LCPI31_0@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC0@toc@l(3) ; PC64LE9-NEXT: fcmpo 1, 2, 3 +; PC64LE9-NEXT: xxlxor 3, 3, 3 +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: lis 3, -32768 ; PC64LE9-NEXT: fcmpo 0, 1, 0 -; PC64LE9-NEXT: xxlxor 3, 3, 3 ; PC64LE9-NEXT: crand 20, 2, 4 ; PC64LE9-NEXT: crandc 21, 0, 2 ; PC64LE9-NEXT: cror 20, 21, 20 @@ -1367,10 +1371,10 @@ ; PC64-NEXT: mfcr 12 ; PC64-NEXT: stw 12, 8(1) ; PC64-NEXT: stdu 1, -128(1) -; PC64-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PC64-NEXT: lfs 0, .LCPI31_0@toc@l(3) -; PC64-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PC64-NEXT: lfs 4, .LCPI31_1@toc@l(3) +; PC64-NEXT: addis 3, 2, .LC2@toc@ha +; PC64-NEXT: ld 3, .LC2@toc@l(3) +; PC64-NEXT: lfs 0, 0(3) +; PC64-NEXT: lfs 4, 4(3) ; PC64-NEXT: fcmpo 0, 1, 0 ; PC64-NEXT: crandc 21, 0, 2 ; PC64-NEXT: fcmpo 1, 2, 4 @@ -1529,11 +1533,12 @@ ; PC64-NEXT: mr 30, 4 ; PC64-NEXT: lfs 31, 0(29) ; PC64-NEXT: std 3, 8(4) -; PC64-NEXT: addis 3, 2, .LCPI32_0@toc@ha +; PC64-NEXT: addis 3, 2, .LC3@toc@ha +; PC64-NEXT: ld 3, .LC3@toc@l(3) ; PC64-NEXT: stfd 30, 160(1) # 8-byte Folded Spill -; PC64-NEXT: lfs 30, .LCPI32_0@toc@l(3) ; PC64-NEXT: fmr 1, 31 ; PC64-NEXT: fmr 3, 31 +; PC64-NEXT: lfs 30, 0(3) ; PC64-NEXT: stfd 28, 144(1) # 8-byte Folded Spill ; PC64-NEXT: fmr 2, 30 ; PC64-NEXT: fmr 4, 30 @@ -1628,10 +1633,11 @@ ; ; PC64-LABEL: i32_to_ppcq: ; PC64: # %bb.0: # %entry +; PC64-NEXT: addis 4, 2, .LC4@toc@ha ; PC64-NEXT: std 3, -8(1) -; PC64-NEXT: addis 3, 2, .LCPI33_0@toc@ha +; PC64-NEXT: ld 4, .LC4@toc@l(4) ; PC64-NEXT: lfd 0, -8(1) -; PC64-NEXT: lfs 2, .LCPI33_0@toc@l(3) +; PC64-NEXT: lfs 2, 0(4) ; PC64-NEXT: fcfid 1, 0 ; PC64-NEXT: blr entry: @@ -1697,15 +1703,15 @@ ; ; PC64-LABEL: u32_to_ppcq: ; PC64: # %bb.0: # %entry -; PC64-NEXT: lis 4, 17200 ; PC64-NEXT: stw 3, -4(1) -; PC64-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PC64-NEXT: stw 4, -8(1) -; PC64-NEXT: lfs 0, .LCPI35_0@toc@l(3) -; PC64-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PC64-NEXT: lfd 1, -8(1) -; PC64-NEXT: lfs 2, .LCPI35_1@toc@l(3) -; PC64-NEXT: fsub 1, 1, 0 +; PC64-NEXT: lis 3, 17200 +; PC64-NEXT: addis 4, 2, .LC5@toc@ha +; PC64-NEXT: stw 3, -8(1) +; PC64-NEXT: ld 3, .LC5@toc@l(4) +; PC64-NEXT: lfd 0, -8(1) +; PC64-NEXT: lfs 1, 4(3) +; PC64-NEXT: lfs 2, 0(3) +; PC64-NEXT: fsub 1, 0, 1 ; PC64-NEXT: blr entry: %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1 @@ -1724,11 +1730,12 @@ ; PC64LE-NEXT: mr 30, 3 ; PC64LE-NEXT: bl __floatditf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC1@toc@ha ; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: fmr 30, 1 +; PC64LE-NEXT: ld 3, .LC1@toc@l(3) ; PC64LE-NEXT: fmr 31, 2 -; PC64LE-NEXT: lfs 3, .LCPI36_0@toc@l(3) +; PC64LE-NEXT: lfsx 3, 0, 3 ; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: nop ; PC64LE-NEXT: cmpdi 30, 0 @@ -1759,11 +1766,12 @@ ; PC64LE9-NEXT: mr 30, 3 ; PC64LE9-NEXT: bl __floatditf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI36_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC1@toc@ha ; PC64LE9-NEXT: xxlxor 4, 4, 4 ; PC64LE9-NEXT: fmr 30, 1 +; PC64LE9-NEXT: ld 3, .LC1@toc@l(3) ; PC64LE9-NEXT: fmr 31, 2 -; PC64LE9-NEXT: lfs 3, .LCPI36_0@toc@l(3) +; PC64LE9-NEXT: lfs 3, 0(3) ; PC64LE9-NEXT: bl __gcc_qadd ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: cmpdi 30, 0 @@ -1794,12 +1802,12 @@ ; PC64-NEXT: stfd 31, 136(1) # 8-byte Folded Spill ; PC64-NEXT: bl __floatditf ; PC64-NEXT: nop -; PC64-NEXT: addis 3, 2, .LCPI36_0@toc@ha +; PC64-NEXT: addis 3, 2, .LC6@toc@ha ; PC64-NEXT: fmr 31, 2 -; PC64-NEXT: lfs 3, .LCPI36_0@toc@l(3) -; PC64-NEXT: addis 3, 2, .LCPI36_1@toc@ha +; PC64-NEXT: ld 3, .LC6@toc@l(3) ; PC64-NEXT: fmr 30, 1 -; PC64-NEXT: lfs 4, .LCPI36_1@toc@l(3) +; PC64-NEXT: lfs 3, 4(3) +; PC64-NEXT: lfs 4, 0(3) ; PC64-NEXT: bl __gcc_qadd ; PC64-NEXT: nop ; PC64-NEXT: cmpdi 30, 0 @@ -1876,11 +1884,12 @@ ; PC64LE-NEXT: mr 30, 4 ; PC64LE-NEXT: bl __floattitf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC2@toc@ha ; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: fmr 30, 1 +; PC64LE-NEXT: ld 3, .LC2@toc@l(3) ; PC64LE-NEXT: fmr 31, 2 -; PC64LE-NEXT: lfd 3, .LCPI38_0@toc@l(3) +; PC64LE-NEXT: lfdx 3, 0, 3 ; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: nop ; PC64LE-NEXT: cmpdi 30, 0 @@ -1911,11 +1920,12 @@ ; PC64LE9-NEXT: mr 30, 4 ; PC64LE9-NEXT: bl __floattitf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI38_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC2@toc@ha ; PC64LE9-NEXT: xxlxor 4, 4, 4 ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfd 3, .LCPI38_0@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC2@toc@l(3) ; PC64LE9-NEXT: fmr 31, 2 +; PC64LE9-NEXT: lfd 3, 0(3) ; PC64LE9-NEXT: bl __gcc_qadd ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: cmpdi 30, 0 @@ -1946,12 +1956,14 @@ ; PC64-NEXT: stfd 31, 136(1) # 8-byte Folded Spill ; PC64-NEXT: bl __floattitf ; PC64-NEXT: nop -; PC64-NEXT: addis 3, 2, .LCPI38_0@toc@ha +; PC64-NEXT: addis 3, 2, .LC7@toc@ha +; PC64-NEXT: addis 4, 2, .LC8@toc@ha ; PC64-NEXT: fmr 31, 2 -; PC64-NEXT: lfd 3, .LCPI38_0@toc@l(3) -; PC64-NEXT: addis 3, 2, .LCPI38_1@toc@ha +; PC64-NEXT: ld 3, .LC7@toc@l(3) +; PC64-NEXT: ld 4, .LC8@toc@l(4) ; PC64-NEXT: fmr 30, 1 -; PC64-NEXT: lfs 4, .LCPI38_1@toc@l(3) +; PC64-NEXT: lfd 3, 0(3) +; PC64-NEXT: lfs 4, 0(4) ; PC64-NEXT: bl __gcc_qadd ; PC64-NEXT: nop ; PC64-NEXT: cmpdi 30, 0 diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll --- a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll +++ b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -58,10 +58,10 @@ ; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI2_1@toc@ha -; CHECK-NEXT: lfs 1, .LCPI2_0@toc@l(3) -; CHECK-NEXT: lfs 2, .LCPI2_1@toc@l(4) +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-NEXT: lfs 1, 0(3) +; CHECK-NEXT: lfs 2, 4(3) ; CHECK-NEXT: bl test ; CHECK-NEXT: nop ; CHECK-NEXT: addi 1, 1, 32 diff --git a/llvm/test/CodeGen/PowerPC/pr25080.ll b/llvm/test/CodeGen/PowerPC/pr25080.ll --- a/llvm/test/CodeGen/PowerPC/pr25080.ll +++ b/llvm/test/CodeGen/PowerPC/pr25080.ll @@ -5,9 +5,9 @@ define <8 x i16> @pr25080(<8 x i32> %a) { ; LE-LABEL: pr25080: ; LE: # %bb.0: # %entry -; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; LE-NEXT: addis 3, 2, .LC0@toc@ha ; LE-NEXT: xxlxor 37, 37, 37 -; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l +; LE-NEXT: ld 3, .LC0@toc@l(3) ; LE-NEXT: lvx 4, 0, 3 ; LE-NEXT: xxland 34, 34, 36 ; LE-NEXT: xxland 35, 35, 36 @@ -36,9 +36,9 @@ ; LE-NEXT: mffprwz 3, 0 ; LE-NEXT: vmrghh 2, 0, 2 ; LE-NEXT: mtvsrd 32, 3 -; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; LE-NEXT: addis 3, 2, .LC1@toc@ha ; LE-NEXT: vmrghh 4, 1, 4 -; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l +; LE-NEXT: ld 3, .LC1@toc@l(3) ; LE-NEXT: vmrghh 3, 3, 6 ; LE-NEXT: vmrghh 5, 0, 5 ; LE-NEXT: vmrglw 2, 4, 2 @@ -53,9 +53,9 @@ ; ; BE-LABEL: pr25080: ; BE: # %bb.0: # %entry -; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; BE-NEXT: addis 3, 2, .LC0@toc@ha ; BE-NEXT: xxlxor 36, 36, 36 -; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l +; BE-NEXT: ld 3, .LC0@toc@l(3) ; BE-NEXT: lxvw4x 0, 0, 3 ; BE-NEXT: xxland 35, 35, 0 ; BE-NEXT: xxland 34, 34, 0 @@ -93,9 +93,9 @@ ; BE-NEXT: sldi 3, 4, 48 ; BE-NEXT: vmrghh 2, 2, 4 ; BE-NEXT: mtvsrd 36, 3 -; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; BE-NEXT: addis 3, 2, .LC1@toc@ha ; BE-NEXT: vmrghh 0, 1, 0 -; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l +; BE-NEXT: ld 3, .LC1@toc@l(3) ; BE-NEXT: vmrghh 4, 4, 5 ; BE-NEXT: lxvw4x 0, 0, 3 ; BE-NEXT: vmrghw 2, 2, 3 diff --git a/llvm/test/CodeGen/PowerPC/pr43976.ll b/llvm/test/CodeGen/PowerPC/pr43976.ll --- a/llvm/test/CodeGen/PowerPC/pr43976.ll +++ b/llvm/test/CodeGen/PowerPC/pr43976.ll @@ -9,30 +9,30 @@ ; CHECK-NEXT: mflr r0 ; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: stdu r1, -144(r1) -; CHECK-NEXT: addis r3, r2, a@toc@ha -; CHECK-NEXT: li r4, 1 -; CHECK-NEXT: lfd f0, a@toc@l(r3) -; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-NEXT: sldi r4, r4, 63 -; CHECK-NEXT: lfs f1, .LCPI0_0@toc@l(r3) +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: addis r4, r2, a@toc@ha +; CHECK-NEXT: li r5, 1 +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-NEXT: lfd f0, a@toc@l(r4) +; CHECK-NEXT: sldi r5, r5, 63 +; CHECK-NEXT: lfs f1, 4(r3) ; CHECK-NEXT: fsub f2, f0, f1 ; CHECK-NEXT: fctidz f2, f2 ; CHECK-NEXT: stfd f2, 128(r1) ; CHECK-NEXT: fctidz f2, f0 ; CHECK-NEXT: stfd f2, 120(r1) -; CHECK-NEXT: ld r3, 128(r1) -; CHECK-NEXT: ld r5, 120(r1) +; CHECK-NEXT: ld r4, 128(r1) +; CHECK-NEXT: ld r6, 120(r1) ; CHECK-NEXT: fcmpu cr0, f0, f1 -; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: lfs f1, 0(r3) +; CHECK-NEXT: xor r4, r4, r5 ; CHECK-NEXT: bc 12, lt, .LBB0_1 ; CHECK-NEXT: b .LBB0_2 ; CHECK-NEXT: .LBB0_1: # %entry -; CHECK-NEXT: addi r3, r5, 0 +; CHECK-NEXT: addi r4, r6, 0 ; CHECK-NEXT: .LBB0_2: # %entry -; CHECK-NEXT: std r3, 112(r1) -; CHECK-NEXT: addis r3, r2, .LCPI0_1@toc@ha +; CHECK-NEXT: std r4, 112(r1) ; CHECK-NEXT: lfd f0, 112(r1) -; CHECK-NEXT: lfs f1, .LCPI0_1@toc@l(r3) ; CHECK-NEXT: fcfid f0, f0 ; CHECK-NEXT: fmul f0, f0, f1 ; CHECK-NEXT: fctiwz f0, f0 diff --git a/llvm/test/CodeGen/PowerPC/pr45628.ll b/llvm/test/CodeGen/PowerPC/pr45628.ll --- a/llvm/test/CodeGen/PowerPC/pr45628.ll +++ b/llvm/test/CodeGen/PowerPC/pr45628.ll @@ -268,15 +268,13 @@ define <1 x i128> @NO_rotl(<1 x i128> %num) { ; P9-VSX-LABEL: NO_rotl: ; P9-VSX: # %bb.0: # %entry -; P9-VSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha -; P9-VSX-NEXT: addi r3, r3, .LCPI8_0@toc@l +; P9-VSX-NEXT: addis r3, r2, .LC0@toc@ha +; P9-VSX-NEXT: ld r3, .LC0@toc@l(r3) ; P9-VSX-NEXT: lxvx v3, 0, r3 -; P9-VSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha -; P9-VSX-NEXT: addi r3, r3, .LCPI8_1@toc@l ; P9-VSX-NEXT: vslo v4, v2, v3 ; P9-VSX-NEXT: vspltb v3, v3, 15 ; P9-VSX-NEXT: vsl v3, v4, v3 -; P9-VSX-NEXT: lxvx v4, 0, r3 +; P9-VSX-NEXT: lxv v4, 16(r3) ; P9-VSX-NEXT: vsro v2, v2, v4 ; P9-VSX-NEXT: vspltb v4, v4, 15 ; P9-VSX-NEXT: vsr v2, v2, v4 @@ -285,15 +283,14 @@ ; ; P9-NOVSX-LABEL: NO_rotl: ; P9-NOVSX: # %bb.0: # %entry -; P9-NOVSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha -; P9-NOVSX-NEXT: addi r3, r3, .LCPI8_0@toc@l +; P9-NOVSX-NEXT: addis r3, r2, .LC0@toc@ha +; P9-NOVSX-NEXT: li r4, 16 +; P9-NOVSX-NEXT: ld r3, .LC0@toc@l(r3) ; P9-NOVSX-NEXT: lvx v3, 0, r3 -; P9-NOVSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha -; P9-NOVSX-NEXT: addi r3, r3, .LCPI8_1@toc@l ; P9-NOVSX-NEXT: vslo v4, v2, v3 ; P9-NOVSX-NEXT: vspltb v3, v3, 15 ; P9-NOVSX-NEXT: vsl v3, v4, v3 -; P9-NOVSX-NEXT: lvx v4, 0, r3 +; P9-NOVSX-NEXT: lvx v4, r3, r4 ; P9-NOVSX-NEXT: vsro v2, v2, v4 ; P9-NOVSX-NEXT: vspltb v4, v4, 15 ; P9-NOVSX-NEXT: vsr v2, v2, v4 @@ -321,12 +318,11 @@ ; ; P8-NOVSX-LABEL: NO_rotl: ; P8-NOVSX: # %bb.0: # %entry -; P8-NOVSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha -; P8-NOVSX-NEXT: addis r4, r2, .LCPI8_1@toc@ha -; P8-NOVSX-NEXT: addi r3, r3, .LCPI8_0@toc@l +; P8-NOVSX-NEXT: addis r3, r2, .LC0@toc@ha +; P8-NOVSX-NEXT: li r4, 16 +; P8-NOVSX-NEXT: ld r3, .LC0@toc@l(r3) ; P8-NOVSX-NEXT: lvx v3, 0, r3 -; P8-NOVSX-NEXT: addi r3, r4, .LCPI8_1@toc@l -; P8-NOVSX-NEXT: lvx v4, 0, r3 +; P8-NOVSX-NEXT: lvx v4, r3, r4 ; P8-NOVSX-NEXT: vslo v5, v2, v3 ; P8-NOVSX-NEXT: vspltb v3, v3, 15 ; P8-NOVSX-NEXT: vsro v2, v2, v4 diff --git a/llvm/test/CodeGen/PowerPC/pr45709.ll b/llvm/test/CodeGen/PowerPC/pr45709.ll --- a/llvm/test/CodeGen/PowerPC/pr45709.ll +++ b/llvm/test/CodeGen/PowerPC/pr45709.ll @@ -17,8 +17,8 @@ ; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: .LBB0_3: -; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NEXT: lvx v3, 0, r3 ; CHECK-NEXT: vperm v2, v2, v2, v3 ; CHECK-NEXT: vxor v3, v3, v3 diff --git a/llvm/test/CodeGen/PowerPC/pr47660.ll b/llvm/test/CodeGen/PowerPC/pr47660.ll --- a/llvm/test/CodeGen/PowerPC/pr47660.ll +++ b/llvm/test/CodeGen/PowerPC/pr47660.ll @@ -21,11 +21,12 @@ ; ; CHECK-BE-LABEL: _Z1f1c: ; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: clrldi r3, r3, 56 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: std r3, -16(r1) -; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: lfd f0, -16(r1) -; CHECK-BE-NEXT: lfs f1, .LCPI0_0@toc@l(r3) +; CHECK-BE-NEXT: lfs f1, 0(r4) ; CHECK-BE-NEXT: fcfid f0, f0 ; CHECK-BE-NEXT: fmul f0, f0, f1 ; CHECK-BE-NEXT: fctiwz f0, f0 diff --git a/llvm/test/CodeGen/PowerPC/pr47891.ll b/llvm/test/CodeGen/PowerPC/pr47891.ll --- a/llvm/test/CodeGen/PowerPC/pr47891.ll +++ b/llvm/test/CodeGen/PowerPC/pr47891.ll @@ -8,57 +8,56 @@ ; CHECK-LABEL: poly2_lshift1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: li r4, 72 -; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha -; CHECK-NEXT: addis r6, r2, .LCPI0_1@toc@ha -; CHECK-NEXT: ld r7, 64(r3) +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: ld r6, 64(r3) +; CHECK-NEXT: li r7, 16 ; CHECK-NEXT: ld r8, 16(r3) ; CHECK-NEXT: ld r10, 24(r3) ; CHECK-NEXT: ld r11, 32(r3) ; CHECK-NEXT: lxvd2x vs0, r3, r4 -; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l -; CHECK-NEXT: addi r6, r6, .LCPI0_1@toc@l +; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r12, 56(r3) -; CHECK-NEXT: lxvd2x vs1, 0, r5 -; CHECK-NEXT: mtfprd f2, r7 -; CHECK-NEXT: ld r5, 0(r3) +; CHECK-NEXT: mtfprd f1, r6 ; CHECK-NEXT: xxswapd v2, vs0 -; CHECK-NEXT: lxvd2x vs0, 0, r6 -; CHECK-NEXT: ld r6, 8(r3) +; CHECK-NEXT: lxvd2x vs0, 0, r5 +; CHECK-NEXT: lxvd2x vs2, r5, r7 +; CHECK-NEXT: ld r5, 0(r3) +; CHECK-NEXT: ld r7, 8(r3) ; CHECK-NEXT: rotldi r9, r5, 1 ; CHECK-NEXT: sldi r5, r5, 1 -; CHECK-NEXT: xxswapd v3, vs1 +; CHECK-NEXT: xxpermdi v3, v2, vs1, 2 +; CHECK-NEXT: xxswapd v4, vs0 +; CHECK-NEXT: rldimi r9, r7, 1, 0 +; CHECK-NEXT: rotldi r7, r7, 1 ; CHECK-NEXT: std r5, 0(r3) -; CHECK-NEXT: rotldi r5, r10, 1 -; CHECK-NEXT: rldimi r9, r6, 1, 0 -; CHECK-NEXT: rotldi r6, r6, 1 -; CHECK-NEXT: xxpermdi v4, v2, vs2, 2 -; CHECK-NEXT: xxswapd v5, vs0 -; CHECK-NEXT: rldimi r6, r8, 1, 0 +; CHECK-NEXT: xxswapd v5, vs2 +; CHECK-NEXT: rldimi r7, r8, 1, 0 ; CHECK-NEXT: rotldi r8, r8, 1 ; CHECK-NEXT: std r9, 8(r3) ; CHECK-NEXT: ld r9, 40(r3) +; CHECK-NEXT: rotldi r5, r10, 1 ; CHECK-NEXT: rldimi r8, r10, 1, 0 +; CHECK-NEXT: std r7, 16(r3) +; CHECK-NEXT: vsrd v3, v3, v4 ; CHECK-NEXT: rldimi r5, r11, 1, 0 -; CHECK-NEXT: std r6, 16(r3) ; CHECK-NEXT: rotldi r10, r11, 1 ; CHECK-NEXT: ld r11, 48(r3) -; CHECK-NEXT: std r5, 32(r3) -; CHECK-NEXT: rotldi r6, r12, 1 -; CHECK-NEXT: vsrd v3, v4, v3 -; CHECK-NEXT: rldimi r10, r9, 1, 0 -; CHECK-NEXT: rotldi r9, r9, 1 ; CHECK-NEXT: std r8, 24(r3) ; CHECK-NEXT: vsld v2, v2, v5 +; CHECK-NEXT: rldimi r10, r9, 1, 0 +; CHECK-NEXT: rotldi r9, r9, 1 +; CHECK-NEXT: std r5, 32(r3) ; CHECK-NEXT: rotldi r5, r11, 1 -; CHECK-NEXT: rldimi r9, r11, 1, 0 +; CHECK-NEXT: rotldi r7, r12, 1 ; CHECK-NEXT: std r10, 40(r3) +; CHECK-NEXT: xxlor vs0, v2, v3 +; CHECK-NEXT: rldimi r9, r11, 1, 0 ; CHECK-NEXT: rldimi r5, r12, 1, 0 -; CHECK-NEXT: rldimi r6, r7, 1, 0 +; CHECK-NEXT: rldimi r7, r6, 1, 0 ; CHECK-NEXT: std r9, 48(r3) -; CHECK-NEXT: xxlor vs0, v2, v3 ; CHECK-NEXT: std r5, 56(r3) -; CHECK-NEXT: std r6, 64(r3) ; CHECK-NEXT: xxswapd vs0, vs0 +; CHECK-NEXT: std r7, 64(r3) ; CHECK-NEXT: stxvd2x vs0, r3, r4 ; CHECK-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll --- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll +++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll @@ -12,18 +12,16 @@ ; CHECK-LABEL: test_pre_inc_disable_1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lxsd v5, 0(r5) -; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: li r6, 0 -; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l -; CHECK-NEXT: lxvx v2, 0, r5 -; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha -; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l +; CHECK-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-NEXT: lxv v2, 16(r5) ; CHECK-NEXT: lxvx v4, 0, r5 ; CHECK-NEXT: li r5, 4 -; CHECK-NEXT: vperm v0, v3, v5, v2 ; CHECK-NEXT: mtctr r5 ; CHECK-NEXT: li r5, 0 +; CHECK-NEXT: vperm v0, v3, v5, v2 ; CHECK-NEXT: vperm v1, v3, v5, v4 ; CHECK-NEXT: xvnegsp v5, v0 ; CHECK-NEXT: xvnegsp v0, v1 @@ -68,19 +66,17 @@ ; P9BE-LABEL: test_pre_inc_disable_1: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: lfd f0, 0(r5) -; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha +; P9BE-NEXT: addis r5, r2, .LC0@toc@ha ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: li r6, 0 -; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r5 -; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha +; P9BE-NEXT: ld r5, .LC0@toc@l(r5) ; P9BE-NEXT: xxlor v5, vs0, vs0 -; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l -; P9BE-NEXT: lxvx v4, 0, r5 +; P9BE-NEXT: lxvx v2, 0, r5 +; P9BE-NEXT: lxv v4, 16(r5) ; P9BE-NEXT: li r5, 4 -; P9BE-NEXT: vperm v0, v3, v5, v2 ; P9BE-NEXT: mtctr r5 ; P9BE-NEXT: li r5, 0 +; P9BE-NEXT: vperm v0, v3, v5, v2 ; P9BE-NEXT: vperm v1, v3, v5, v4 ; P9BE-NEXT: xvnegsp v5, v0 ; P9BE-NEXT: xvnegsp v0, v1 @@ -179,14 +175,12 @@ ; CHECK-LABEL: test_pre_inc_disable_2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lxsd v2, 0(r3) -; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-NEXT: addis r3, r2, .LC1@toc@ha ; CHECK-NEXT: lxsd v1, 0(r4) ; CHECK-NEXT: xxlxor v3, v3, v3 -; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-NEXT: lxvx v4, 0, r3 -; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l -; CHECK-NEXT: lxvx v0, 0, r3 +; CHECK-NEXT: lxv v0, 16(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v5, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v0 @@ -206,17 +200,15 @@ ; P9BE-LABEL: test_pre_inc_disable_2: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: lfd f0, 0(r3) -; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; P9BE-NEXT: addis r3, r2, .LC1@toc@ha ; P9BE-NEXT: xxlxor v3, v3, v3 -; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; P9BE-NEXT: lxvx v4, 0, r3 -; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha -; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l +; P9BE-NEXT: ld r3, .LC1@toc@l(r3) ; P9BE-NEXT: xxlor v2, vs0, vs0 ; P9BE-NEXT: lfd f0, 0(r4) +; P9BE-NEXT: lxv v4, 16(r3) ; P9BE-NEXT: lxvx v0, 0, r3 -; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: li r3, 0 +; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: vperm v5, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v0 ; P9BE-NEXT: vperm v0, v3, v1, v0 @@ -282,9 +274,9 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: add r5, r3, r4 ; CHECK-NEXT: lxsiwzx v2, r3, r4 -; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha +; CHECK-NEXT: addis r3, r2, .LC2@toc@ha ; CHECK-NEXT: xxlxor v3, v3, v3 -; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: lxsiwzx v5, r5, r3 @@ -303,10 +295,10 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: add r5, r3, r4 ; P9BE-NEXT: lfiwzx f0, r3, r4 -; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha +; P9BE-NEXT: addis r3, r2, .LC2@toc@ha ; P9BE-NEXT: xxlxor v3, v3, v3 +; P9BE-NEXT: ld r3, .LC2@toc@l(r3) ; P9BE-NEXT: xxsldwi v2, f0, f0, 1 -; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l ; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: lfiwzx f0, r5, r3 @@ -352,10 +344,10 @@ ; CHECK-NEXT: li r7, 16 ; CHECK-NEXT: add r6, r3, r4 ; CHECK-NEXT: lxsihzx v4, r3, r4 -; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-NEXT: addis r3, r2, .LC3@toc@ha ; CHECK-NEXT: lxsihzx v2, r6, r7 ; CHECK-NEXT: li r6, 0 -; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l +; CHECK-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-NEXT: mtvsrd v3, r6 ; CHECK-NEXT: vsplth v4, v4, 3 ; CHECK-NEXT: vsplth v2, v2, 3 @@ -379,10 +371,10 @@ ; P9BE-NEXT: li r7, 16 ; P9BE-NEXT: add r6, r3, r4 ; P9BE-NEXT: lxsihzx v4, r3, r4 -; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; P9BE-NEXT: addis r3, r2, .LC3@toc@ha ; P9BE-NEXT: lxsihzx v2, r6, r7 ; P9BE-NEXT: li r6, 0 -; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l +; P9BE-NEXT: ld r3, .LC3@toc@l(r3) ; P9BE-NEXT: sldi r6, r6, 48 ; P9BE-NEXT: vsplth v4, v4, 3 ; P9BE-NEXT: mtvsrd v3, r6 @@ -441,10 +433,10 @@ ; CHECK-NEXT: mtvsrd v3, r3 ; CHECK-NEXT: li r3, 8 ; CHECK-NEXT: lxsibzx v5, r6, r3 +; CHECK-NEXT: addis r3, r2, .LC4@toc@ha ; CHECK-NEXT: vspltb v4, v3, 7 -; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-NEXT: vspltb v2, v2, 7 -; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-NEXT: vmrghb v2, v3, v2 ; CHECK-NEXT: vspltb v5, v5, 7 ; CHECK-NEXT: vmrglh v2, v2, v4 @@ -467,10 +459,10 @@ ; P9BE-NEXT: add r6, r3, r4 ; P9BE-NEXT: li r7, 8 ; P9BE-NEXT: lxsibzx v4, r3, r4 -; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; P9BE-NEXT: addis r3, r2, .LC4@toc@ha ; P9BE-NEXT: lxsibzx v2, r6, r7 ; P9BE-NEXT: li r6, 0 -; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; P9BE-NEXT: ld r3, .LC4@toc@l(r3) ; P9BE-NEXT: sldi r6, r6, 56 ; P9BE-NEXT: vspltb v4, v4, 7 ; P9BE-NEXT: mtvsrd v3, r6 diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -15,10 +15,10 @@ ; CHECK-P7-LABEL: foo_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: frsqrte 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI0_1@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI0_0@toc@l(3) -; CHECK-P7-NEXT: lfs 5, .LCPI0_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-P7-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P7-NEXT: lfs 4, 4(3) +; CHECK-P7-NEXT: lfs 5, 0(3) ; CHECK-P7-NEXT: fmul 3, 2, 0 ; CHECK-P7-NEXT: fmadd 3, 3, 0, 4 ; CHECK-P7-NEXT: fmul 0, 0, 5 @@ -33,12 +33,12 @@ ; CHECK-P8-LABEL: foo_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtedp 0, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P8-NEXT: lfs 4, .LCPI0_0@toc@l(3) -; CHECK-P8-NEXT: addis 3, 2, .LCPI0_1@toc@ha -; CHECK-P8-NEXT: lfs 5, .LCPI0_1@toc@l(3) -; CHECK-P8-NEXT: fmr 6, 4 +; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P8-NEXT: lfs 4, 4(3) +; CHECK-P8-NEXT: lfsx 5, 0, 3 ; CHECK-P8-NEXT: xsmuldp 3, 2, 0 +; CHECK-P8-NEXT: fmr 6, 4 ; CHECK-P8-NEXT: xsmaddadp 6, 3, 0 ; CHECK-P8-NEXT: xsmuldp 0, 0, 5 ; CHECK-P8-NEXT: xsmuldp 0, 0, 6 @@ -51,14 +51,14 @@ ; ; CHECK-P9-LABEL: foo_fmf: ; CHECK-P9: # %bb.0: +; CHECK-P9-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-P9-NEXT: xsrsqrtedp 0, 2 -; CHECK-P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P9-NEXT: lfs 4, .LCPI0_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; CHECK-P9-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P9-NEXT: lfs 4, 4(3) ; CHECK-P9-NEXT: xsmuldp 3, 2, 0 ; CHECK-P9-NEXT: fmr 5, 4 ; CHECK-P9-NEXT: xsmaddadp 5, 3, 0 -; CHECK-P9-NEXT: lfs 3, .LCPI0_1@toc@l(3) +; CHECK-P9-NEXT: lfs 3, 0(3) ; CHECK-P9-NEXT: xsmuldp 0, 0, 3 ; CHECK-P9-NEXT: xsmuldp 0, 0, 5 ; CHECK-P9-NEXT: xsmuldp 2, 2, 0 @@ -122,10 +122,10 @@ ; CHECK-P7-LABEL: foof_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: frsqrtes 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI3_1@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI3_0@toc@l(3) -; CHECK-P7-NEXT: lfs 4, .LCPI3_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-P7-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-P7-NEXT: lfs 3, 4(3) +; CHECK-P7-NEXT: lfs 4, 0(3) ; CHECK-P7-NEXT: fmuls 2, 2, 0 ; CHECK-P7-NEXT: fmadds 2, 2, 0, 3 ; CHECK-P7-NEXT: fmuls 0, 0, 4 @@ -136,10 +136,10 @@ ; CHECK-P8-LABEL: foof_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtesp 0, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI3_1@toc@ha -; CHECK-P8-NEXT: lfs 3, .LCPI3_0@toc@l(3) -; CHECK-P8-NEXT: lfs 4, .LCPI3_1@toc@l(4) +; CHECK-P8-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-P8-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-P8-NEXT: lfs 3, 4(3) +; CHECK-P8-NEXT: lfsx 4, 0, 3 ; CHECK-P8-NEXT: xsmulsp 2, 2, 0 ; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 ; CHECK-P8-NEXT: xsmulsp 0, 0, 4 @@ -150,12 +150,12 @@ ; CHECK-P9-LABEL: foof_fmf: ; CHECK-P9: # %bb.0: ; CHECK-P9-NEXT: xsrsqrtesp 0, 2 -; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: lfs 3, .LCPI3_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI3_1@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-P9-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-P9-NEXT: lfs 3, 4(3) ; CHECK-P9-NEXT: xsmulsp 2, 2, 0 ; CHECK-P9-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI3_1@toc@l(3) +; CHECK-P9-NEXT: lfs 2, 0(3) ; CHECK-P9-NEXT: xsmulsp 0, 0, 2 ; CHECK-P9-NEXT: xsmulsp 0, 0, 3 ; CHECK-P9-NEXT: xsmuldp 1, 1, 0 @@ -194,10 +194,10 @@ ; CHECK-P7-LABEL: food_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: frsqrte 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI5_1@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI5_0@toc@l(3) -; CHECK-P7-NEXT: lfs 5, .LCPI5_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-P7-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-P7-NEXT: lfs 4, 4(3) +; CHECK-P7-NEXT: lfs 5, 0(3) ; CHECK-P7-NEXT: fmul 3, 2, 0 ; CHECK-P7-NEXT: fmadd 3, 3, 0, 4 ; CHECK-P7-NEXT: fmul 0, 0, 5 @@ -213,12 +213,12 @@ ; CHECK-P8-LABEL: food_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtedp 0, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P8-NEXT: lfs 4, .LCPI5_0@toc@l(3) -; CHECK-P8-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; CHECK-P8-NEXT: lfs 5, .LCPI5_1@toc@l(3) -; CHECK-P8-NEXT: fmr 6, 4 +; CHECK-P8-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-P8-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-P8-NEXT: lfs 4, 4(3) +; CHECK-P8-NEXT: lfsx 5, 0, 3 ; CHECK-P8-NEXT: xsmuldp 3, 2, 0 +; CHECK-P8-NEXT: fmr 6, 4 ; CHECK-P8-NEXT: xsmaddadp 6, 3, 0 ; CHECK-P8-NEXT: xsmuldp 0, 0, 5 ; CHECK-P8-NEXT: xsmuldp 0, 0, 6 @@ -232,14 +232,14 @@ ; ; CHECK-P9-LABEL: food_fmf: ; CHECK-P9: # %bb.0: +; CHECK-P9-NEXT: addis 3, 2, .LC2@toc@ha ; CHECK-P9-NEXT: xsrsqrtedp 0, 2 -; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: lfs 4, .LCPI5_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI5_1@toc@ha +; CHECK-P9-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-P9-NEXT: lfs 4, 4(3) ; CHECK-P9-NEXT: xsmuldp 3, 2, 0 ; CHECK-P9-NEXT: fmr 5, 4 ; CHECK-P9-NEXT: xsmaddadp 5, 3, 0 -; CHECK-P9-NEXT: lfs 3, .LCPI5_1@toc@l(3) +; CHECK-P9-NEXT: lfs 3, 0(3) ; CHECK-P9-NEXT: xsmuldp 0, 0, 3 ; CHECK-P9-NEXT: xsmuldp 0, 0, 5 ; CHECK-P9-NEXT: xsmuldp 2, 2, 0 @@ -286,10 +286,10 @@ ; CHECK-P7-LABEL: goo_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: frsqrtes 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI7_1@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI7_0@toc@l(3) -; CHECK-P7-NEXT: lfs 4, .LCPI7_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-P7-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-P7-NEXT: lfs 3, 4(3) +; CHECK-P7-NEXT: lfs 4, 0(3) ; CHECK-P7-NEXT: fmuls 2, 2, 0 ; CHECK-P7-NEXT: fmadds 2, 2, 0, 3 ; CHECK-P7-NEXT: fmuls 0, 0, 4 @@ -300,10 +300,10 @@ ; CHECK-P8-LABEL: goo_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtesp 0, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI7_1@toc@ha -; CHECK-P8-NEXT: lfs 3, .LCPI7_0@toc@l(3) -; CHECK-P8-NEXT: lfs 4, .LCPI7_1@toc@l(4) +; CHECK-P8-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-P8-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-P8-NEXT: lfs 3, 4(3) +; CHECK-P8-NEXT: lfsx 4, 0, 3 ; CHECK-P8-NEXT: xsmulsp 2, 2, 0 ; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 ; CHECK-P8-NEXT: xsmulsp 0, 0, 4 @@ -314,12 +314,12 @@ ; CHECK-P9-LABEL: goo_fmf: ; CHECK-P9: # %bb.0: ; CHECK-P9-NEXT: xsrsqrtesp 0, 2 -; CHECK-P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P9-NEXT: lfs 3, .LCPI7_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI7_1@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-P9-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-P9-NEXT: lfs 3, 4(3) ; CHECK-P9-NEXT: xsmulsp 2, 2, 0 ; CHECK-P9-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI7_1@toc@l(3) +; CHECK-P9-NEXT: lfs 2, 0(3) ; CHECK-P9-NEXT: xsmulsp 0, 0, 2 ; CHECK-P9-NEXT: xsmulsp 0, 0, 3 ; CHECK-P9-NEXT: xsmulsp 1, 1, 0 @@ -379,10 +379,10 @@ ; CHECK-P7-LABEL: rsqrt_fmul_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: frsqrtes 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI10_1@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI10_0@toc@l(3) -; CHECK-P7-NEXT: lfs 5, .LCPI10_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-P7-NEXT: ld 3, .LC4@toc@l(3) +; CHECK-P7-NEXT: lfs 4, 4(3) +; CHECK-P7-NEXT: lfs 5, 0(3) ; CHECK-P7-NEXT: fmuls 1, 1, 0 ; CHECK-P7-NEXT: fmadds 1, 1, 0, 4 ; CHECK-P7-NEXT: fmuls 0, 0, 5 @@ -397,10 +397,10 @@ ; CHECK-P8-LABEL: rsqrt_fmul_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtesp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI10_1@toc@ha -; CHECK-P8-NEXT: lfs 4, .LCPI10_0@toc@l(3) -; CHECK-P8-NEXT: lfs 5, .LCPI10_1@toc@l(4) +; CHECK-P8-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-P8-NEXT: ld 3, .LC4@toc@l(3) +; CHECK-P8-NEXT: lfs 4, 4(3) +; CHECK-P8-NEXT: lfsx 5, 0, 3 ; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 4, 1, 0 ; CHECK-P8-NEXT: xsmulsp 0, 0, 5 @@ -415,12 +415,12 @@ ; CHECK-P9-LABEL: rsqrt_fmul_fmf: ; CHECK-P9: # %bb.0: ; CHECK-P9-NEXT: xsrsqrtesp 0, 1 -; CHECK-P9-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P9-NEXT: lfs 4, .LCPI10_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI10_1@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-P9-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-P9-NEXT: xsmulsp 1, 1, 0 +; CHECK-P9-NEXT: lfs 4, 4(3) ; CHECK-P9-NEXT: xsmaddasp 4, 1, 0 -; CHECK-P9-NEXT: lfs 1, .LCPI10_1@toc@l(3) +; CHECK-P9-NEXT: lfs 1, 0(3) ; CHECK-P9-NEXT: xsmulsp 0, 0, 1 ; CHECK-P9-NEXT: xsresp 1, 2 ; CHECK-P9-NEXT: xsmulsp 0, 0, 4 @@ -466,12 +466,11 @@ ; CHECK-P7-LABEL: hoo_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: vspltisw 4, -1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI12_0@toc@ha +; CHECK-P7-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-P7-NEXT: li 4, 16 ; CHECK-P7-NEXT: vrsqrtefp 5, 3 -; CHECK-P7-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P7-NEXT: lvx 0, 0, 3 -; CHECK-P7-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; CHECK-P7-NEXT: addi 3, 3, .LCPI12_1@toc@l +; CHECK-P7-NEXT: ld 3, .LC5@toc@l(3) +; CHECK-P7-NEXT: lvx 0, 3, 4 ; CHECK-P7-NEXT: lvx 1, 0, 3 ; CHECK-P7-NEXT: vslw 4, 4, 4 ; CHECK-P7-NEXT: vmaddfp 3, 3, 5, 4 @@ -484,13 +483,12 @@ ; CHECK-P8-LABEL: hoo_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xvrsqrtesp 0, 35 -; CHECK-P8-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI12_1@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P8-NEXT: xvmulsp 1, 35, 0 -; CHECK-P8-NEXT: lvx 3, 0, 3 -; CHECK-P8-NEXT: addi 3, 4, .LCPI12_1@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-P8-NEXT: li 4, 16 +; CHECK-P8-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-P8-NEXT: lvx 4, 0, 3 +; CHECK-P8-NEXT: xvmulsp 1, 35, 0 +; CHECK-P8-NEXT: lvx 3, 3, 4 ; CHECK-P8-NEXT: xvmaddasp 35, 1, 0 ; CHECK-P8-NEXT: xvmulsp 0, 0, 36 ; CHECK-P8-NEXT: xvmulsp 0, 0, 35 @@ -500,12 +498,10 @@ ; CHECK-P9-LABEL: hoo_fmf: ; CHECK-P9: # %bb.0: ; CHECK-P9-NEXT: xvrsqrtesp 0, 35 -; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI12_1@toc@l +; CHECK-P9-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-P9-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-P9-NEXT: xvmulsp 1, 35, 0 +; CHECK-P9-NEXT: lxv 2, 16(3) ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 ; CHECK-P9-NEXT: lxvx 1, 0, 3 ; CHECK-P9-NEXT: xvmulsp 0, 0, 1 @@ -567,9 +563,10 @@ define double @foo2_fmf(double %a, double %b) nounwind { ; CHECK-P7-LABEL: foo2_fmf: ; CHECK-P7: # %bb.0: +; CHECK-P7-NEXT: addis 3, 2, .LC6@toc@ha ; CHECK-P7-NEXT: fre 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI14_0@toc@l(3) +; CHECK-P7-NEXT: ld 3, .LC6@toc@l(3) +; CHECK-P7-NEXT: lfs 3, 0(3) ; CHECK-P7-NEXT: fmadd 3, 2, 0, 3 ; CHECK-P7-NEXT: fnmsub 0, 0, 3, 0 ; CHECK-P7-NEXT: fmul 3, 1, 0 @@ -579,9 +576,10 @@ ; ; CHECK-P8-LABEL: foo2_fmf: ; CHECK-P8: # %bb.0: +; CHECK-P8-NEXT: addis 3, 2, .LC6@toc@ha ; CHECK-P8-NEXT: xsredp 3, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; CHECK-P8-NEXT: lfs 0, .LCPI14_0@toc@l(3) +; CHECK-P8-NEXT: ld 3, .LC6@toc@l(3) +; CHECK-P8-NEXT: lfsx 0, 0, 3 ; CHECK-P8-NEXT: xsmaddadp 0, 2, 3 ; CHECK-P8-NEXT: xsnmsubadp 3, 3, 0 ; CHECK-P8-NEXT: xsmuldp 0, 1, 3 @@ -592,9 +590,10 @@ ; ; CHECK-P9-LABEL: foo2_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI14_0@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC6@toc@ha ; CHECK-P9-NEXT: xsredp 3, 2 -; CHECK-P9-NEXT: lfs 0, .LCPI14_0@toc@l(3) +; CHECK-P9-NEXT: ld 3, .LC6@toc@l(3) +; CHECK-P9-NEXT: lfs 0, 0(3) ; CHECK-P9-NEXT: xsmaddadp 0, 2, 3 ; CHECK-P9-NEXT: xsnmsubadp 3, 3, 0 ; CHECK-P9-NEXT: xsmuldp 0, 1, 3 @@ -753,10 +752,10 @@ ; CHECK-P7-NEXT: bc 12, 2, .LBB20_2 ; CHECK-P7-NEXT: # %bb.1: ; CHECK-P7-NEXT: frsqrte 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI20_1@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI20_0@toc@l(3) -; CHECK-P7-NEXT: lfs 4, .LCPI20_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC7@toc@ha +; CHECK-P7-NEXT: ld 3, .LC7@toc@l(3) +; CHECK-P7-NEXT: lfs 3, 4(3) +; CHECK-P7-NEXT: lfs 4, 0(3) ; CHECK-P7-NEXT: fmul 2, 1, 0 ; CHECK-P7-NEXT: fmadd 2, 2, 0, 3 ; CHECK-P7-NEXT: fmul 0, 0, 4 @@ -776,12 +775,12 @@ ; CHECK-P8-NEXT: bc 12, 2, .LBB20_2 ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xsrsqrtedp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-P8-NEXT: lfs 3, .LCPI20_0@toc@l(3) -; CHECK-P8-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; CHECK-P8-NEXT: lfs 4, .LCPI20_1@toc@l(3) -; CHECK-P8-NEXT: fmr 5, 3 +; CHECK-P8-NEXT: addis 3, 2, .LC7@toc@ha +; CHECK-P8-NEXT: ld 3, .LC7@toc@l(3) +; CHECK-P8-NEXT: lfs 3, 4(3) +; CHECK-P8-NEXT: lfsx 4, 0, 3 ; CHECK-P8-NEXT: xsmuldp 2, 1, 0 +; CHECK-P8-NEXT: fmr 5, 3 ; CHECK-P8-NEXT: xsmaddadp 5, 2, 0 ; CHECK-P8-NEXT: xsmuldp 0, 0, 4 ; CHECK-P8-NEXT: xsmuldp 0, 0, 5 @@ -799,14 +798,14 @@ ; CHECK-P9-NEXT: xstsqrtdp 0, 1 ; CHECK-P9-NEXT: bc 12, 2, .LBB20_2 ; CHECK-P9-NEXT: # %bb.1: +; CHECK-P9-NEXT: addis 3, 2, .LC7@toc@ha ; CHECK-P9-NEXT: xsrsqrtedp 0, 1 -; CHECK-P9-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-P9-NEXT: lfs 3, .LCPI20_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI20_1@toc@ha +; CHECK-P9-NEXT: ld 3, .LC7@toc@l(3) +; CHECK-P9-NEXT: lfs 3, 4(3) ; CHECK-P9-NEXT: xsmuldp 2, 1, 0 ; CHECK-P9-NEXT: fmr 4, 3 ; CHECK-P9-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI20_1@toc@l(3) +; CHECK-P9-NEXT: lfs 2, 0(3) ; CHECK-P9-NEXT: xsmuldp 0, 0, 2 ; CHECK-P9-NEXT: xsmuldp 0, 0, 4 ; CHECK-P9-NEXT: xsmuldp 1, 1, 0 @@ -824,17 +823,18 @@ define double @foo3_fmf_crbits_off(double %a) #2 { ; CHECK-P7-LABEL: foo3_fmf_crbits_off: ; CHECK-P7: # %bb.0: +; CHECK-P7-NEXT: addis 3, 2, .LC8@toc@ha ; CHECK-P7-NEXT: fabs 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI21_2@toc@ha -; CHECK-P7-NEXT: lfd 2, .LCPI21_2@toc@l(3) +; CHECK-P7-NEXT: ld 3, .LC8@toc@l(3) +; CHECK-P7-NEXT: lfd 2, 0(3) ; CHECK-P7-NEXT: fcmpu 0, 0, 2 ; CHECK-P7-NEXT: blt 0, .LBB21_2 ; CHECK-P7-NEXT: # %bb.1: ; CHECK-P7-NEXT: frsqrte 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI21_1@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI21_0@toc@l(3) -; CHECK-P7-NEXT: lfs 4, .LCPI21_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC9@toc@ha +; CHECK-P7-NEXT: ld 3, .LC9@toc@l(3) +; CHECK-P7-NEXT: lfs 3, 4(3) +; CHECK-P7-NEXT: lfs 4, 0(3) ; CHECK-P7-NEXT: fmul 2, 1, 0 ; CHECK-P7-NEXT: fmadd 2, 2, 0, 3 ; CHECK-P7-NEXT: fmul 0, 0, 4 @@ -850,19 +850,20 @@ ; ; CHECK-P8-LABEL: foo3_fmf_crbits_off: ; CHECK-P8: # %bb.0: +; CHECK-P8-NEXT: addis 3, 2, .LC8@toc@ha ; CHECK-P8-NEXT: xsabsdp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI21_2@toc@ha -; CHECK-P8-NEXT: lfd 2, .LCPI21_2@toc@l(3) +; CHECK-P8-NEXT: ld 3, .LC8@toc@l(3) +; CHECK-P8-NEXT: lfdx 2, 0, 3 ; CHECK-P8-NEXT: xscmpudp 0, 0, 2 ; CHECK-P8-NEXT: blt 0, .LBB21_2 ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xsrsqrtedp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-P8-NEXT: lfs 3, .LCPI21_0@toc@l(3) -; CHECK-P8-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; CHECK-P8-NEXT: lfs 4, .LCPI21_1@toc@l(3) -; CHECK-P8-NEXT: fmr 5, 3 +; CHECK-P8-NEXT: addis 3, 2, .LC9@toc@ha +; CHECK-P8-NEXT: ld 3, .LC9@toc@l(3) +; CHECK-P8-NEXT: lfs 3, 4(3) +; CHECK-P8-NEXT: lfsx 4, 0, 3 ; CHECK-P8-NEXT: xsmuldp 2, 1, 0 +; CHECK-P8-NEXT: fmr 5, 3 ; CHECK-P8-NEXT: xsmaddadp 5, 2, 0 ; CHECK-P8-NEXT: xsmuldp 0, 0, 4 ; CHECK-P8-NEXT: xsmuldp 0, 0, 5 @@ -877,20 +878,21 @@ ; ; CHECK-P9-LABEL: foo3_fmf_crbits_off: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI21_2@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC8@toc@ha ; CHECK-P9-NEXT: xsabsdp 0, 1 -; CHECK-P9-NEXT: lfd 2, .LCPI21_2@toc@l(3) +; CHECK-P9-NEXT: ld 3, .LC8@toc@l(3) +; CHECK-P9-NEXT: lfd 2, 0(3) ; CHECK-P9-NEXT: xscmpudp 0, 0, 2 ; CHECK-P9-NEXT: blt 0, .LBB21_2 ; CHECK-P9-NEXT: # %bb.1: +; CHECK-P9-NEXT: addis 3, 2, .LC9@toc@ha ; CHECK-P9-NEXT: xsrsqrtedp 0, 1 -; CHECK-P9-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-P9-NEXT: lfs 3, .LCPI21_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI21_1@toc@ha +; CHECK-P9-NEXT: ld 3, .LC9@toc@l(3) +; CHECK-P9-NEXT: lfs 3, 4(3) ; CHECK-P9-NEXT: xsmuldp 2, 1, 0 ; CHECK-P9-NEXT: fmr 4, 3 ; CHECK-P9-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI21_1@toc@l(3) +; CHECK-P9-NEXT: lfs 2, 0(3) ; CHECK-P9-NEXT: xsmuldp 0, 0, 2 ; CHECK-P9-NEXT: xsmuldp 0, 0, 4 ; CHECK-P9-NEXT: xsmuldp 1, 1, 0 @@ -927,41 +929,38 @@ define float @goo3_fmf(float %a) nounwind { ; CHECK-P7-LABEL: goo3_fmf: ; CHECK-P7: # %bb.0: +; CHECK-P7-NEXT: addis 3, 2, .LC10@toc@ha ; CHECK-P7-NEXT: fabs 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_2@toc@ha -; CHECK-P7-NEXT: lfs 2, .LCPI23_2@toc@l(3) +; CHECK-P7-NEXT: ld 3, .LC10@toc@l(3) +; CHECK-P7-NEXT: lfs 2, 0(3) ; CHECK-P7-NEXT: fcmpu 0, 0, 2 ; CHECK-P7-NEXT: blt 0, .LBB23_2 ; CHECK-P7-NEXT: # %bb.1: ; CHECK-P7-NEXT: frsqrtes 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI23_1@toc@ha -; CHECK-P7-NEXT: lfs 2, .LCPI23_0@toc@l(3) -; CHECK-P7-NEXT: lfs 3, .LCPI23_1@toc@l(4) +; CHECK-P7-NEXT: lfs 2, 12(3) +; CHECK-P7-NEXT: lfs 3, 8(3) ; CHECK-P7-NEXT: fmuls 1, 1, 0 ; CHECK-P7-NEXT: fmadds 0, 1, 0, 2 ; CHECK-P7-NEXT: fmuls 1, 1, 3 ; CHECK-P7-NEXT: fmuls 1, 1, 0 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB23_2: -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_3@toc@ha -; CHECK-P7-NEXT: lfs 1, .LCPI23_3@toc@l(3) +; CHECK-P7-NEXT: lfs 1, 4(3) ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo3_fmf: ; CHECK-P8: # %bb.0: +; CHECK-P8-NEXT: addis 3, 2, .LC10@toc@ha ; CHECK-P8-NEXT: xsabsdp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI23_2@toc@ha -; CHECK-P8-NEXT: lfs 2, .LCPI23_2@toc@l(3) +; CHECK-P8-NEXT: ld 3, .LC10@toc@l(3) +; CHECK-P8-NEXT: lfsx 2, 0, 3 ; CHECK-P8-NEXT: fcmpu 0, 0, 2 ; CHECK-P8-NEXT: xxlxor 0, 0, 0 ; CHECK-P8-NEXT: blt 0, .LBB23_2 ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xsrsqrtesp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI23_1@toc@ha -; CHECK-P8-NEXT: lfs 2, .LCPI23_0@toc@l(3) -; CHECK-P8-NEXT: lfs 3, .LCPI23_1@toc@l(4) +; CHECK-P8-NEXT: lfs 2, 8(3) +; CHECK-P8-NEXT: lfs 3, 4(3) ; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 2, 1, 0 ; CHECK-P8-NEXT: xsmulsp 0, 1, 3 @@ -972,20 +971,19 @@ ; ; CHECK-P9-LABEL: goo3_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI23_2@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC10@toc@ha ; CHECK-P9-NEXT: xsabsdp 0, 1 -; CHECK-P9-NEXT: lfs 2, .LCPI23_2@toc@l(3) +; CHECK-P9-NEXT: ld 3, .LC10@toc@l(3) +; CHECK-P9-NEXT: lfs 2, 0(3) ; CHECK-P9-NEXT: fcmpu 0, 0, 2 ; CHECK-P9-NEXT: xxlxor 0, 0, 0 ; CHECK-P9-NEXT: blt 0, .LBB23_2 ; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: xsrsqrtesp 0, 1 -; CHECK-P9-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P9-NEXT: lfs 2, .LCPI23_0@toc@l(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI23_1@toc@ha +; CHECK-P9-NEXT: lfs 2, 8(3) ; CHECK-P9-NEXT: xsmulsp 1, 1, 0 ; CHECK-P9-NEXT: xsmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lfs 0, .LCPI23_1@toc@l(3) +; CHECK-P9-NEXT: lfs 0, 4(3) ; CHECK-P9-NEXT: xsmulsp 0, 1, 0 ; CHECK-P9-NEXT: xsmulsp 0, 0, 2 ; CHECK-P9-NEXT: .LBB23_2: @@ -1018,12 +1016,11 @@ ; CHECK-P7-LABEL: hoo3_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: vspltisw 3, -1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI25_0@toc@ha +; CHECK-P7-NEXT: addis 3, 2, .LC11@toc@ha +; CHECK-P7-NEXT: li 4, 16 ; CHECK-P7-NEXT: vrsqrtefp 4, 2 -; CHECK-P7-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P7-NEXT: lvx 0, 0, 3 -; CHECK-P7-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; CHECK-P7-NEXT: addi 3, 3, .LCPI25_1@toc@l +; CHECK-P7-NEXT: ld 3, .LC11@toc@l(3) +; CHECK-P7-NEXT: lvx 0, 3, 4 ; CHECK-P7-NEXT: lvx 1, 0, 3 ; CHECK-P7-NEXT: vslw 3, 3, 3 ; CHECK-P7-NEXT: vmaddfp 5, 2, 4, 3 @@ -1041,13 +1038,12 @@ ; CHECK-P8-NEXT: bc 12, 2, .LBB25_2 ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xvrsqrtesp 0, 34 -; CHECK-P8-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI25_1@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P8-NEXT: xvmulsp 1, 34, 0 -; CHECK-P8-NEXT: lvx 2, 0, 3 -; CHECK-P8-NEXT: addi 3, 4, .LCPI25_1@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC11@toc@ha +; CHECK-P8-NEXT: li 4, 16 +; CHECK-P8-NEXT: ld 3, .LC11@toc@l(3) ; CHECK-P8-NEXT: lvx 3, 0, 3 +; CHECK-P8-NEXT: xvmulsp 1, 34, 0 +; CHECK-P8-NEXT: lvx 2, 3, 4 ; CHECK-P8-NEXT: xvmaddasp 34, 1, 0 ; CHECK-P8-NEXT: xvmulsp 0, 1, 35 ; CHECK-P8-NEXT: xvmulsp 34, 0, 34 @@ -1062,12 +1058,10 @@ ; CHECK-P9-NEXT: bc 12, 2, .LBB25_2 ; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: xvrsqrtesp 0, 34 -; CHECK-P9-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI25_1@toc@l +; CHECK-P9-NEXT: addis 3, 2, .LC11@toc@ha +; CHECK-P9-NEXT: ld 3, .LC11@toc@l(3) ; CHECK-P9-NEXT: xvmulsp 1, 34, 0 +; CHECK-P9-NEXT: lxv 2, 16(3) ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 ; CHECK-P9-NEXT: lxvx 0, 0, 3 ; CHECK-P9-NEXT: xvmulsp 0, 1, 0 @@ -1118,10 +1112,10 @@ ; CHECK-P7-LABEL: hoo4_fmf: ; CHECK-P7: # %bb.0: ; CHECK-P7-NEXT: ftsqrt 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-P7-NEXT: addis 4, 2, .LCPI27_1@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI27_0@toc@l(3) -; CHECK-P7-NEXT: lfs 0, .LCPI27_1@toc@l(4) +; CHECK-P7-NEXT: addis 3, 2, .LC12@toc@ha +; CHECK-P7-NEXT: ld 3, .LC12@toc@l(3) +; CHECK-P7-NEXT: lfs 3, 4(3) +; CHECK-P7-NEXT: lfs 0, 0(3) ; CHECK-P7-NEXT: bc 12, 2, .LBB27_3 ; CHECK-P7-NEXT: # %bb.1: ; CHECK-P7-NEXT: frsqrte 4, 1 @@ -1160,14 +1154,13 @@ ; CHECK-P8-NEXT: bc 12, 2, .LBB27_2 ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xvrsqrtedp 0, 34 -; CHECK-P8-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI27_0@toc@l -; CHECK-P8-NEXT: lxvd2x 1, 0, 3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI27_1@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC12@toc@ha +; CHECK-P8-NEXT: li 4, 16 +; CHECK-P8-NEXT: ld 3, .LC12@toc@l(3) +; CHECK-P8-NEXT: lxvd2x 1, 3, 4 ; CHECK-P8-NEXT: lxvd2x 3, 0, 3 -; CHECK-P8-NEXT: xxswapd 1, 1 ; CHECK-P8-NEXT: xvmuldp 2, 34, 0 +; CHECK-P8-NEXT: xxswapd 1, 1 ; CHECK-P8-NEXT: xxswapd 3, 3 ; CHECK-P8-NEXT: xxlor 4, 1, 1 ; CHECK-P8-NEXT: xvmaddadp 4, 2, 0 @@ -1188,12 +1181,10 @@ ; CHECK-P9-NEXT: bc 12, 2, .LBB27_2 ; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: xvrsqrtedp 0, 34 -; CHECK-P9-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI27_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI27_1@toc@l +; CHECK-P9-NEXT: addis 3, 2, .LC12@toc@ha +; CHECK-P9-NEXT: ld 3, .LC12@toc@l(3) ; CHECK-P9-NEXT: xvmuldp 1, 34, 0 +; CHECK-P9-NEXT: lxv 2, 16(3) ; CHECK-P9-NEXT: xxlor 3, 2, 2 ; CHECK-P9-NEXT: xvmaddadp 3, 1, 0 ; CHECK-P9-NEXT: lxvx 1, 0, 3 diff --git a/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll b/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll --- a/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll +++ b/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll @@ -6,11 +6,10 @@ ; CHECK-LABEL: repeated_fp_divisor_noest: ; CHECK: # %bb.0: ; CHECK-NEXT: xscvdpspn 0, 1 -; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l -; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: lvx 3, 3, 4 ; CHECK-NEXT: xxspltw 0, 0, 0 ; CHECK-NEXT: xvdivsp 0, 35, 0 ; CHECK-NEXT: lvx 3, 0, 3 @@ -28,11 +27,10 @@ ; CHECK-LABEL: repeated_fp_divisor: ; CHECK: # %bb.0: ; CHECK-NEXT: xscvdpspn 0, 1 -; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l -; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-NEXT: lvx 3, 3, 4 ; CHECK-NEXT: lvx 4, 0, 3 ; CHECK-NEXT: xxspltw 0, 0, 0 ; CHECK-NEXT: xvresp 1, 0 diff --git a/llvm/test/CodeGen/PowerPC/sat-add.ll b/llvm/test/CodeGen/PowerPC/sat-add.ll --- a/llvm/test/CodeGen/PowerPC/sat-add.ll +++ b/llvm/test/CodeGen/PowerPC/sat-add.ll @@ -377,13 +377,12 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) { ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI24_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI24_1@toc@l ; CHECK-NEXT: vminub 2, 2, 3 -; CHECK-NEXT: lvx 3, 0, 3 +; CHECK-NEXT: lvx 3, 3, 4 ; CHECK-NEXT: vaddubm 2, 2, 3 ; CHECK-NEXT: blr %c = icmp ult <16 x i8> %x, @@ -395,8 +394,8 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) { ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC1@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vaddubs 2, 2, 3 ; CHECK-NEXT: blr @@ -409,8 +408,8 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) { ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI26_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vaddubs 2, 2, 3 ; CHECK-NEXT: blr @@ -423,13 +422,12 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) { ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI27_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI27_1@toc@l ; CHECK-NEXT: vminuh 2, 2, 3 -; CHECK-NEXT: lvx 3, 0, 3 +; CHECK-NEXT: lvx 3, 3, 4 ; CHECK-NEXT: vadduhm 2, 2, 3 ; CHECK-NEXT: blr %c = icmp ult <8 x i16> %x, @@ -441,8 +439,8 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) { ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduhs 2, 2, 3 ; CHECK-NEXT: blr @@ -455,8 +453,8 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) { ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI29_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduhs 2, 2, 3 ; CHECK-NEXT: blr @@ -469,11 +467,10 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) { ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI30_0@toc@l -; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI30_1@toc@l +; CHECK-NEXT: addis 3, 2, .LC6@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC6@toc@l(3) +; CHECK-NEXT: lvx 3, 3, 4 ; CHECK-NEXT: vminuw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduwm 2, 2, 3 @@ -487,8 +484,8 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) { ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC7@toc@ha +; CHECK-NEXT: ld 3, .LC7@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduws 2, 2, 3 ; CHECK-NEXT: blr @@ -501,8 +498,8 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) { ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI32_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC8@toc@ha +; CHECK-NEXT: ld 3, .LC8@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduws 2, 2, 3 ; CHECK-NEXT: blr @@ -515,11 +512,10 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) { ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI33_0@toc@l -; CHECK-NEXT: lxvd2x 0, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI33_1@toc@l +; CHECK-NEXT: addis 3, 2, .LC9@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC9@toc@l(3) +; CHECK-NEXT: lxvd2x 0, 3, 4 ; CHECK-NEXT: xxswapd 35, 0 ; CHECK-NEXT: lxvd2x 0, 0, 3 ; CHECK-NEXT: vminud 2, 2, 3 @@ -535,8 +531,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) { ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI34_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC10@toc@ha +; CHECK-NEXT: ld 3, .LC10@toc@l(3) ; CHECK-NEXT: lxvd2x 0, 0, 3 ; CHECK-NEXT: xxswapd 35, 0 ; CHECK-NEXT: xxleqv 0, 0, 0 @@ -553,15 +549,14 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) { ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: ; CHECK: # %bb.0: -; CHECK-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI35_1@toc@l +; CHECK-NEXT: addis 3, 2, .LC11@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC11@toc@l(3) ; CHECK-NEXT: lxvd2x 0, 0, 3 -; CHECK-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI35_0@toc@l -; CHECK-NEXT: lxvd2x 1, 0, 3 +; CHECK-NEXT: lxvd2x 1, 3, 4 ; CHECK-NEXT: xxswapd 35, 0 -; CHECK-NEXT: xxleqv 0, 0, 0 ; CHECK-NEXT: xxswapd 36, 1 +; CHECK-NEXT: xxleqv 0, 0, 0 ; CHECK-NEXT: vcmpgtud 3, 2, 3 ; CHECK-NEXT: vaddudm 2, 2, 4 ; CHECK-NEXT: xxsel 34, 34, 0, 35 diff --git a/llvm/test/CodeGen/PowerPC/scalar_cmp.ll b/llvm/test/CodeGen/PowerPC/scalar_cmp.ll --- a/llvm/test/CodeGen/PowerPC/scalar_cmp.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_cmp.ll @@ -895,24 +895,27 @@ define double @onecmp1(double %a, double %y, double %z) { ; FAST-P8-LABEL: onecmp1: ; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: addis r3, r2, .LCPI24_0@toc@ha -; FAST-P8-NEXT: lfs f0, .LCPI24_0@toc@l(r3) +; FAST-P8-NEXT: addis r3, r2, .LC0@toc@ha +; FAST-P8-NEXT: ld r3, .LC0@toc@l(r3) +; FAST-P8-NEXT: lfsx f0, 0, r3 ; FAST-P8-NEXT: xssubdp f0, f1, f0 ; FAST-P8-NEXT: fsel f1, f0, f2, f3 ; FAST-P8-NEXT: blr ; ; FAST-P9-LABEL: onecmp1: ; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: addis r3, r2, .LCPI24_0@toc@ha -; FAST-P9-NEXT: lfs f0, .LCPI24_0@toc@l(r3) +; FAST-P9-NEXT: addis r3, r2, .LC0@toc@ha +; FAST-P9-NEXT: ld r3, .LC0@toc@l(r3) +; FAST-P9-NEXT: lfs f0, 0(r3) ; FAST-P9-NEXT: xssubdp f0, f1, f0 ; FAST-P9-NEXT: fsel f1, f0, f2, f3 ; FAST-P9-NEXT: blr ; ; NO-FAST-P8-LABEL: onecmp1: ; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: addis r3, r2, .LCPI24_0@toc@ha -; NO-FAST-P8-NEXT: lfs f0, .LCPI24_0@toc@l(r3) +; NO-FAST-P8-NEXT: addis r3, r2, .LC0@toc@ha +; NO-FAST-P8-NEXT: ld r3, .LC0@toc@l(r3) +; NO-FAST-P8-NEXT: lfsx f0, 0, r3 ; NO-FAST-P8-NEXT: fcmpu cr0, f1, f0 ; NO-FAST-P8-NEXT: cror 4*cr5+lt, lt, un ; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB24_2 @@ -924,8 +927,9 @@ ; ; NO-FAST-P9-LABEL: onecmp1: ; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: addis r3, r2, .LCPI24_0@toc@ha -; NO-FAST-P9-NEXT: lfs f0, .LCPI24_0@toc@l(r3) +; NO-FAST-P9-NEXT: addis r3, r2, .LC0@toc@ha +; NO-FAST-P9-NEXT: ld r3, .LC0@toc@l(r3) +; NO-FAST-P9-NEXT: lfs f0, 0(r3) ; NO-FAST-P9-NEXT: fcmpu cr0, f1, f0 ; NO-FAST-P9-NEXT: cror 4*cr5+lt, lt, un ; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB24_2 @@ -943,24 +947,27 @@ define double @onecmp2(double %a, double %y, double %z) { ; FAST-P8-LABEL: onecmp2: ; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; FAST-P8-NEXT: lfs f0, .LCPI25_0@toc@l(r3) +; FAST-P8-NEXT: addis r3, r2, .LC1@toc@ha +; FAST-P8-NEXT: ld r3, .LC1@toc@l(r3) +; FAST-P8-NEXT: lfsx f0, 0, r3 ; FAST-P8-NEXT: xssubdp f0, f0, f1 ; FAST-P8-NEXT: fsel f1, f0, f3, f2 ; FAST-P8-NEXT: blr ; ; FAST-P9-LABEL: onecmp2: ; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; FAST-P9-NEXT: lfs f0, .LCPI25_0@toc@l(r3) +; FAST-P9-NEXT: addis r3, r2, .LC1@toc@ha +; FAST-P9-NEXT: ld r3, .LC1@toc@l(r3) +; FAST-P9-NEXT: lfs f0, 0(r3) ; FAST-P9-NEXT: xssubdp f0, f0, f1 ; FAST-P9-NEXT: fsel f1, f0, f3, f2 ; FAST-P9-NEXT: blr ; ; NO-FAST-P8-LABEL: onecmp2: ; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; NO-FAST-P8-NEXT: lfs f0, .LCPI25_0@toc@l(r3) +; NO-FAST-P8-NEXT: addis r3, r2, .LC1@toc@ha +; NO-FAST-P8-NEXT: ld r3, .LC1@toc@l(r3) +; NO-FAST-P8-NEXT: lfsx f0, 0, r3 ; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f0 ; NO-FAST-P8-NEXT: fmr f1, f2 ; NO-FAST-P8-NEXT: bgtlr cr0 @@ -970,8 +977,9 @@ ; ; NO-FAST-P9-LABEL: onecmp2: ; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: addis r3, r2, .LCPI25_0@toc@ha -; NO-FAST-P9-NEXT: lfs f0, .LCPI25_0@toc@l(r3) +; NO-FAST-P9-NEXT: addis r3, r2, .LC1@toc@ha +; NO-FAST-P9-NEXT: ld r3, .LC1@toc@l(r3) +; NO-FAST-P9-NEXT: lfs f0, 0(r3) ; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f0 ; NO-FAST-P9-NEXT: bgt cr0, .LBB25_2 ; NO-FAST-P9-NEXT: # %bb.1: # %entry @@ -988,8 +996,9 @@ define double @onecmp3(double %a, double %y, double %z) { ; FAST-P8-LABEL: onecmp3: ; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: addis r3, r2, .LCPI26_0@toc@ha -; FAST-P8-NEXT: lfs f0, .LCPI26_0@toc@l(r3) +; FAST-P8-NEXT: addis r3, r2, .LC2@toc@ha +; FAST-P8-NEXT: ld r3, .LC2@toc@l(r3) +; FAST-P8-NEXT: lfsx f0, 0, r3 ; FAST-P8-NEXT: xssubdp f0, f1, f0 ; FAST-P8-NEXT: xsnegdp f1, f0 ; FAST-P8-NEXT: fsel f0, f0, f2, f3 @@ -998,8 +1007,9 @@ ; ; FAST-P9-LABEL: onecmp3: ; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: addis r3, r2, .LCPI26_0@toc@ha -; FAST-P9-NEXT: lfs f0, .LCPI26_0@toc@l(r3) +; FAST-P9-NEXT: addis r3, r2, .LC2@toc@ha +; FAST-P9-NEXT: ld r3, .LC2@toc@l(r3) +; FAST-P9-NEXT: lfs f0, 0(r3) ; FAST-P9-NEXT: xssubdp f0, f1, f0 ; FAST-P9-NEXT: fsel f1, f0, f2, f3 ; FAST-P9-NEXT: xsnegdp f0, f0 @@ -1008,8 +1018,9 @@ ; ; NO-FAST-P8-LABEL: onecmp3: ; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: addis r3, r2, .LCPI26_0@toc@ha -; NO-FAST-P8-NEXT: lfs f0, .LCPI26_0@toc@l(r3) +; NO-FAST-P8-NEXT: addis r3, r2, .LC2@toc@ha +; NO-FAST-P8-NEXT: ld r3, .LC2@toc@l(r3) +; NO-FAST-P8-NEXT: lfsx f0, 0, r3 ; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f0 ; NO-FAST-P8-NEXT: fmr f1, f2 ; NO-FAST-P8-NEXT: beqlr cr0 @@ -1019,8 +1030,9 @@ ; ; NO-FAST-P9-LABEL: onecmp3: ; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: addis r3, r2, .LCPI26_0@toc@ha -; NO-FAST-P9-NEXT: lfs f0, .LCPI26_0@toc@l(r3) +; NO-FAST-P9-NEXT: addis r3, r2, .LC2@toc@ha +; NO-FAST-P9-NEXT: ld r3, .LC2@toc@l(r3) +; NO-FAST-P9-NEXT: lfs f0, 0(r3) ; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f0 ; NO-FAST-P9-NEXT: beq cr0, .LBB26_2 ; NO-FAST-P9-NEXT: # %bb.1: # %entry diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll --- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll @@ -26,9 +26,9 @@ ; ; P8LE-LABEL: s2v_test1: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r4, r2, .LCPI0_0@toc@ha +; P8LE-NEXT: addis r4, r2, .LC0@toc@ha ; P8LE-NEXT: lxsiwzx v4, 0, r3 -; P8LE-NEXT: addi r4, r4, .LCPI0_0@toc@l +; P8LE-NEXT: ld r4, .LC0@toc@l(r4) ; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: blr @@ -64,9 +64,9 @@ ; ; P8LE-LABEL: s2v_test2: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; P8LE-NEXT: addis r4, r2, .LC1@toc@ha ; P8LE-NEXT: addi r3, r3, 4 -; P8LE-NEXT: addi r4, r4, .LCPI1_0@toc@l +; P8LE-NEXT: ld r4, .LC1@toc@l(r4) ; P8LE-NEXT: lxsiwzx v4, 0, r3 ; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: vperm v2, v2, v4, v3 @@ -107,9 +107,9 @@ ; ; P8LE-LABEL: s2v_test3: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; P8LE-NEXT: addis r4, r2, .LC2@toc@ha ; P8LE-NEXT: sldi r5, r7, 2 -; P8LE-NEXT: addi r4, r4, .LCPI2_0@toc@l +; P8LE-NEXT: ld r4, .LC2@toc@l(r4) ; P8LE-NEXT: lxsiwzx v3, r3, r5 ; P8LE-NEXT: lvx v4, 0, r4 ; P8LE-NEXT: vperm v2, v2, v3, v4 @@ -149,9 +149,9 @@ ; ; P8LE-LABEL: s2v_test4: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; P8LE-NEXT: addis r4, r2, .LC3@toc@ha ; P8LE-NEXT: addi r3, r3, 4 -; P8LE-NEXT: addi r4, r4, .LCPI3_0@toc@l +; P8LE-NEXT: ld r4, .LC3@toc@l(r4) ; P8LE-NEXT: lxsiwzx v4, 0, r3 ; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: vperm v2, v2, v4, v3 @@ -190,9 +190,9 @@ ; ; P8LE-LABEL: s2v_test5: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; P8LE-NEXT: addis r3, r2, .LC4@toc@ha ; P8LE-NEXT: lxsiwzx v4, 0, r5 -; P8LE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; P8LE-NEXT: ld r3, .LC4@toc@l(r3) ; P8LE-NEXT: lvx v3, 0, r3 ; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: blr @@ -230,9 +230,9 @@ ; ; P8LE-LABEL: s2v_test_f1: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: addis r4, r2, .LCPI5_0@toc@ha +; P8LE-NEXT: addis r4, r2, .LC5@toc@ha ; P8LE-NEXT: lxsiwzx v4, 0, r3 -; P8LE-NEXT: addi r4, r4, .LCPI5_0@toc@l +; P8LE-NEXT: ld r4, .LC5@toc@l(r4) ; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/select_const.ll b/llvm/test/CodeGen/PowerPC/select_const.ll --- a/llvm/test/CodeGen/PowerPC/select_const.ll +++ b/llvm/test/CodeGen/PowerPC/select_const.ll @@ -720,22 +720,20 @@ define double @sel_constants_fadd_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fadd_constant: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC0@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI42_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l +; ISEL-NEXT: ld 4, .LC0@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 ; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fadd_constant: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC0@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI42_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l +; NO_ISEL-NEXT: ld 4, .LC0@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 ; NO_ISEL-NEXT: bc 12, 1, .LBB42_2 ; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 @@ -751,22 +749,20 @@ define double @sel_constants_fsub_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fsub_constant: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC1@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI43_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l +; ISEL-NEXT: ld 4, .LC1@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 ; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fsub_constant: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC1@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI43_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l +; NO_ISEL-NEXT: ld 4, .LC1@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 ; NO_ISEL-NEXT: bc 12, 1, .LBB43_2 ; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 @@ -782,22 +778,20 @@ define double @fsub_constant_sel_constants(i1 %cond) { ; ISEL-LABEL: fsub_constant_sel_constants: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC2@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI44_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l +; ISEL-NEXT: ld 4, .LC2@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 ; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: fsub_constant_sel_constants: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC2@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI44_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l +; NO_ISEL-NEXT: ld 4, .LC2@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 ; NO_ISEL-NEXT: bc 12, 1, .LBB44_2 ; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 @@ -813,22 +807,20 @@ define double @sel_constants_fmul_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fmul_constant: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC3@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI45_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l +; ISEL-NEXT: ld 4, .LC3@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 ; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fmul_constant: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC3@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI45_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l +; NO_ISEL-NEXT: ld 4, .LC3@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 ; NO_ISEL-NEXT: bc 12, 1, .LBB45_2 ; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 @@ -844,22 +836,20 @@ define double @sel_constants_fdiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fdiv_constant: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC4@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI46_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l +; ISEL-NEXT: ld 4, .LC4@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 ; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fdiv_constant: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC4@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI46_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l +; NO_ISEL-NEXT: ld 4, .LC4@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 ; NO_ISEL-NEXT: bc 12, 1, .LBB46_2 ; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 @@ -875,22 +865,20 @@ define double @fdiv_constant_sel_constants(i1 %cond) { ; ISEL-LABEL: fdiv_constant_sel_constants: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC5@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI47_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l +; ISEL-NEXT: ld 4, .LC5@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 ; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: fdiv_constant_sel_constants: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC5@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI47_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l +; NO_ISEL-NEXT: ld 4, .LC5@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 ; NO_ISEL-NEXT: bc 12, 1, .LBB47_2 ; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 @@ -909,12 +897,14 @@ ; ALL-NEXT: andi. 3, 3, 1 ; ALL-NEXT: bc 12, 1, .LBB48_2 ; ALL-NEXT: # %bb.1: -; ALL-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; ALL-NEXT: lfd 1, .LCPI48_0@toc@l(3) +; ALL-NEXT: addis 3, 2, .LC6@toc@ha +; ALL-NEXT: ld 3, .LC6@toc@l(3) +; ALL-NEXT: lfdx 1, 0, 3 ; ALL-NEXT: blr ; ALL-NEXT: .LBB48_2: -; ALL-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; ALL-NEXT: lfs 1, .LCPI48_1@toc@l(3) +; ALL-NEXT: addis 3, 2, .LC7@toc@ha +; ALL-NEXT: ld 3, .LC7@toc@l(3) +; ALL-NEXT: lfsx 1, 0, 3 ; ALL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = frem double %sel, 5.1 @@ -924,26 +914,24 @@ define double @frem_constant_sel_constants(i1 %cond) { ; ISEL-LABEL: frem_constant_sel_constants: ; ISEL: # %bb.0: +; ISEL-NEXT: addis 4, 2, .LC8@toc@ha ; ISEL-NEXT: andi. 3, 3, 1 -; ISEL-NEXT: addis 4, 2, .LCPI49_0@toc@ha -; ISEL-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l -; ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l -; ISEL-NEXT: iselgt 3, 3, 4 +; ISEL-NEXT: ld 4, .LC8@toc@l(4) +; ISEL-NEXT: addi 3, 4, 8 +; ISEL-NEXT: iselgt 3, 4, 3 ; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: frem_constant_sel_constants: ; NO_ISEL: # %bb.0: +; NO_ISEL-NEXT: addis 4, 2, .LC8@toc@ha ; NO_ISEL-NEXT: andi. 3, 3, 1 -; NO_ISEL-NEXT: addis 4, 2, .LCPI49_0@toc@ha -; NO_ISEL-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; NO_ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l -; NO_ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l -; NO_ISEL-NEXT: bc 12, 1, .LBB49_2 -; NO_ISEL-NEXT: # %bb.1: -; NO_ISEL-NEXT: ori 3, 4, 0 +; NO_ISEL-NEXT: ld 4, .LC8@toc@l(4) +; NO_ISEL-NEXT: addi 3, 4, 8 +; NO_ISEL-NEXT: bc 12, 1, .LBB49_1 ; NO_ISEL-NEXT: b .LBB49_2 +; NO_ISEL-NEXT: .LBB49_1: +; NO_ISEL-NEXT: addi 3, 4, 0 ; NO_ISEL-NEXT: .LBB49_2: ; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll --- a/llvm/test/CodeGen/PowerPC/signbit-shift.ll +++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll @@ -30,8 +30,8 @@ ; CHECK-LABEL: add_zext_ifpos_vec_splat: ; CHECK: # %bb.0: ; CHECK-NEXT: xxleqv 35, 35, 35 -; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: vcmpgtsw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vsubuwm 2, 3, 2 @@ -81,8 +81,8 @@ ; CHECK-LABEL: add_sext_ifpos_vec_splat: ; CHECK: # %bb.0: ; CHECK-NEXT: xxleqv 35, 35, 35 -; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC1@toc@l(3) ; CHECK-NEXT: vcmpgtsw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduwm 2, 2, 3 @@ -190,8 +190,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 -; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 @@ -220,8 +220,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 -; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsrw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 @@ -274,8 +274,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 -; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 diff --git a/llvm/test/CodeGen/PowerPC/toc-float.ll b/llvm/test/CodeGen/PowerPC/toc-float.ll --- a/llvm/test/CodeGen/PowerPC/toc-float.ll +++ b/llvm/test/CodeGen/PowerPC/toc-float.ll @@ -7,14 +7,16 @@ define double @doubleConstant1() { ; CHECK-P9-LABEL: doubleConstant1: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P9-NEXT: lfs 1, .LCPI0_0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-P9-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P9-NEXT: lfs 1, 0(3) ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: doubleConstant1: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P8-NEXT: lfs 1, .LCPI0_0@toc@l(3) +; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P8-NEXT: lfsx 1, 0, 3 ; CHECK-P8-NEXT: blr ret double 1.400000e+01 } @@ -24,14 +26,16 @@ define double @doubleConstant2() { ; CHECK-P9-LABEL: doubleConstant2: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; CHECK-P9-NEXT: lfd 1, .LCPI1_0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-P9-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-P9-NEXT: lfd 1, 0(3) ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: doubleConstant2: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; CHECK-P8-NEXT: lfd 1, .LCPI1_0@toc@l(3) +; CHECK-P8-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-P8-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-P8-NEXT: lfdx 1, 0, 3 ; CHECK-P8-NEXT: blr ret double 2.408904e+01 } @@ -43,18 +47,20 @@ ; CHECK-P9: # %bb.0: ; CHECK-P9-NEXT: addis 3, 2, FArr@toc@ha+12 ; CHECK-P9-NEXT: lfs 0, FArr@toc@l+12(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; CHECK-P9-NEXT: lfs 1, .LCPI2_0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-P9-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-P9-NEXT: lfs 1, 0(3) ; CHECK-P9-NEXT: xsaddsp 1, 0, 1 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: floatConstantArray: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, FArr@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, FArr@toc@l -; CHECK-P8-NEXT: lfs 1, .LCPI2_0@toc@l(4) -; CHECK-P8-NEXT: lfs 0, 12(3) +; CHECK-P8-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-P8-NEXT: addis 4, 2, FArr@toc@ha +; CHECK-P8-NEXT: ld 3, .LC2@toc@l(3) +; CHECK-P8-NEXT: addi 4, 4, FArr@toc@l +; CHECK-P8-NEXT: lfs 0, 12(4) +; CHECK-P8-NEXT: lfsx 1, 0, 3 ; CHECK-P8-NEXT: xsaddsp 1, 0, 1 ; CHECK-P8-NEXT: blr %1 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* @FArr, i64 0, i64 3), align 4 @@ -65,14 +71,16 @@ define float @floatConstant() { ; CHECK-P9-LABEL: floatConstant: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: lfs 1, .LCPI3_0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-P9-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-P9-NEXT: lfs 1, 0(3) ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: floatConstant: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: lfs 1, .LCPI3_0@toc@l(3) +; CHECK-P8-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-P8-NEXT: ld 3, .LC3@toc@l(3) +; CHECK-P8-NEXT: lfsx 1, 0, 3 ; CHECK-P8-NEXT: blr ret float 0x400470A3E0000000 } @@ -86,18 +94,20 @@ ; CHECK-P9: # %bb.0: ; CHECK-P9-NEXT: addis 3, 2, d@toc@ha+24 ; CHECK-P9-NEXT: lfd 0, d@toc@l+24(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-P9-NEXT: lfd 1, .LCPI4_0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-P9-NEXT: ld 3, .LC4@toc@l(3) +; CHECK-P9-NEXT: lfd 1, 0(3) ; CHECK-P9-NEXT: xsadddp 1, 0, 1 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: doubleConstantArray: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, d@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI4_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, d@toc@l -; CHECK-P8-NEXT: lfd 1, .LCPI4_0@toc@l(4) -; CHECK-P8-NEXT: lfd 0, 24(3) +; CHECK-P8-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-P8-NEXT: addis 4, 2, d@toc@ha +; CHECK-P8-NEXT: ld 3, .LC4@toc@l(3) +; CHECK-P8-NEXT: addi 4, 4, d@toc@l +; CHECK-P8-NEXT: lfd 0, 24(4) +; CHECK-P8-NEXT: lfdx 1, 0, 3 ; CHECK-P8-NEXT: xsadddp 1, 0, 1 ; CHECK-P8-NEXT: blr %1 = load double, double* getelementptr inbounds ([200 x double], [200 x double]* @d, i64 0, i64 3), align 8 @@ -116,20 +126,22 @@ ; CHECK-P9-NEXT: addi 3, 3, arr@toc@l ; CHECK-P9-NEXT: ori 4, 4, 32768 ; CHECK-P9-NEXT: lfdx 0, 3, 4 -; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: lfd 1, .LCPI5_0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-P9-NEXT: ld 3, .LC5@toc@l(3) +; CHECK-P9-NEXT: lfd 1, 0(3) ; CHECK-P9-NEXT: xsadddp 1, 0, 1 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: doubleLargeConstantArray: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, arr@toc@ha -; CHECK-P8-NEXT: li 4, 0 -; CHECK-P8-NEXT: addis 5, 2, .LCPI5_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, arr@toc@l -; CHECK-P8-NEXT: ori 4, 4, 32768 -; CHECK-P8-NEXT: lfdx 0, 3, 4 -; CHECK-P8-NEXT: lfd 1, .LCPI5_0@toc@l(5) +; CHECK-P8-NEXT: addis 3, 2, .LC5@toc@ha +; CHECK-P8-NEXT: addis 4, 2, arr@toc@ha +; CHECK-P8-NEXT: li 5, 0 +; CHECK-P8-NEXT: ld 3, .LC5@toc@l(3) +; CHECK-P8-NEXT: addi 4, 4, arr@toc@l +; CHECK-P8-NEXT: ori 5, 5, 32768 +; CHECK-P8-NEXT: lfdx 0, 4, 5 +; CHECK-P8-NEXT: lfdx 1, 0, 3 ; CHECK-P8-NEXT: xsadddp 1, 0, 1 ; CHECK-P8-NEXT: blr %1 = load double, double* getelementptr inbounds ([20000 x double], [20000 x double]* @arr, i64 0, i64 4096), align 8 @@ -142,15 +154,15 @@ define <4 x i32> @vectorArray() #0 { ; CHECK-P9-LABEL: vectorArray: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis 3, 2, .LC0@toc@ha -; CHECK-P9-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P9-NEXT: addis 3, 2, .LC6@toc@ha +; CHECK-P9-NEXT: ld 3, .LC6@toc@l(3) ; CHECK-P9-NEXT: lxv 34, 32(3) ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: vectorArray: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha -; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-P8-NEXT: addis 3, 2, .LC6@toc@ha +; CHECK-P8-NEXT: ld 3, .LC6@toc@l(3) ; CHECK-P8-NEXT: addi 3, 3, 32 ; CHECK-P8-NEXT: lvx 2, 0, 3 ; CHECK-P8-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vavg.ll b/llvm/test/CodeGen/PowerPC/vavg.ll --- a/llvm/test/CodeGen/PowerPC/vavg.ll +++ b/llvm/test/CodeGen/PowerPC/vavg.ll @@ -137,9 +137,9 @@ define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) { ; CHECK-P9-LABEL: test_v8i16_sign_negative: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; CHECK-P9-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-P9-NEXT: vadduhm 2, 2, 3 -; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l +; CHECK-P9-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-P9-NEXT: lxvx 35, 0, 3 ; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vspltish 3, 1 @@ -148,10 +148,10 @@ ; ; CHECK-P8-LABEL: test_v8i16_sign_negative: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-P8-NEXT: vadduhm 2, 2, 3 ; CHECK-P8-NEXT: vspltish 4, 1 -; CHECK-P8-NEXT: addi 3, 3, .LCPI6_0@toc@l +; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-P8-NEXT: lvx 3, 0, 3 ; CHECK-P8-NEXT: vadduhm 2, 2, 3 ; CHECK-P8-NEXT: vsrah 2, 2, 4 @@ -159,10 +159,10 @@ ; ; CHECK-P7-LABEL: test_v8i16_sign_negative: ; CHECK-P7: # %bb.0: # %entry -; CHECK-P7-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; CHECK-P7-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-P7-NEXT: vadduhm 2, 2, 3 ; CHECK-P7-NEXT: vspltish 4, 1 -; CHECK-P7-NEXT: addi 3, 3, .LCPI6_0@toc@l +; CHECK-P7-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-P7-NEXT: lvx 3, 0, 3 ; CHECK-P7-NEXT: vadduhm 2, 2, 3 ; CHECK-P7-NEXT: vsrah 2, 2, 4 diff --git a/llvm/test/CodeGen/PowerPC/vec-itofp.ll b/llvm/test/CodeGen/PowerPC/vec-itofp.ll --- a/llvm/test/CodeGen/PowerPC/vec-itofp.ll +++ b/llvm/test/CodeGen/PowerPC/vec-itofp.ll @@ -12,26 +12,21 @@ define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { ; CHECK-P8-LABEL: test8: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI0_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI0_2@toc@ha -; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI0_1@toc@ha -; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI0_0@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI0_2@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI0_1@toc@l +; CHECK-P8-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-P8-NEXT: li r6, 16 +; CHECK-P8-NEXT: li r7, 48 +; CHECK-P8-NEXT: lvx v4, 0, r4 +; CHECK-P8-NEXT: li r4, 32 +; CHECK-P8-NEXT: xxlxor v3, v3, v3 +; CHECK-P8-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI0_3@toc@ha -; CHECK-P8-NEXT: lvx v5, 0, r6 -; CHECK-P8-NEXT: lvx v1, 0, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: addi r5, r5, .LCPI0_3@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r5 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: vperm v2, v4, v3, v2 -; CHECK-P8-NEXT: vperm v5, v4, v3, v5 -; CHECK-P8-NEXT: vperm v0, v4, v3, v0 -; CHECK-P8-NEXT: vperm v3, v4, v3, v1 +; CHECK-P8-NEXT: lvx v5, r5, r6 +; CHECK-P8-NEXT: lvx v0, r5, r7 +; CHECK-P8-NEXT: lvx v1, r5, r4 +; CHECK-P8-NEXT: vperm v2, v3, v4, v2 +; CHECK-P8-NEXT: vperm v5, v3, v4, v5 +; CHECK-P8-NEXT: vperm v0, v3, v4, v0 +; CHECK-P8-NEXT: vperm v3, v3, v4, v1 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0 @@ -40,37 +35,30 @@ ; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test8: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l +; CHECK-P9-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -80,27 +68,21 @@ ; CHECK-BE-LABEL: test8: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2@toc@l +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -116,37 +98,33 @@ define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { ; CHECK-P8-LABEL: test4: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC1@toc@ha +; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l +; CHECK-P8-NEXT: ld r5, .LC1@toc@l(r5) ; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI1_1@toc@l -; CHECK-P8-NEXT: lvx v5, 0, r5 +; CHECK-P8-NEXT: lvx v5, r5, r6 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: vperm v3, v4, v3, v5 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test4: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l +; CHECK-P9-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -156,15 +134,13 @@ ; CHECK-BE-LABEL: test4: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -180,10 +156,10 @@ define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { ; CHECK-P8-LABEL: test2: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC2@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l +; CHECK-P8-NEXT: ld r5, .LC2@toc@l(r5) ; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2 @@ -194,9 +170,9 @@ ; CHECK-P9-LABEL: test2: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-P9-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v2 @@ -206,9 +182,9 @@ ; CHECK-BE-LABEL: test2: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v2 @@ -224,25 +200,20 @@ define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { ; CHECK-P8-LABEL: stest8: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC3@toc@ha +; CHECK-P8-NEXT: addis r6, r2, .LC4@toc@ha +; CHECK-P8-NEXT: li r7, 32 +; CHECK-P8-NEXT: li r8, 16 ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3@toc@ha -; CHECK-P8-NEXT: lvx v4, 0, r6 -; CHECK-P8-NEXT: addis r6, r2, .LCPI3_4@toc@ha -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3@toc@l -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI3_4@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r5 +; CHECK-P8-NEXT: ld r5, .LC3@toc@l(r5) +; CHECK-P8-NEXT: ld r6, .LC4@toc@l(r6) +; CHECK-P8-NEXT: lvx v2, 0, r5 +; CHECK-P8-NEXT: lvx v4, r5, r7 +; CHECK-P8-NEXT: lvx v5, r5, r8 +; CHECK-P8-NEXT: lvx v0, r5, r4 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r6 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 -; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: vperm v4, v3, v3, v4 ; CHECK-P8-NEXT: vperm v5, v3, v3, v5 ; CHECK-P8-NEXT: vperm v3, v3, v3, v0 @@ -252,50 +223,43 @@ ; CHECK-P8-NEXT: vsld v5, v5, v0 ; CHECK-P8-NEXT: vsld v3, v3, v0 ; CHECK-P8-NEXT: vsrad v2, v2, v0 -; CHECK-P8-NEXT: vsrad v3, v3, v0 ; CHECK-P8-NEXT: vsrad v4, v4, v0 ; CHECK-P8-NEXT: vsrad v5, v5, v0 -; CHECK-P8-NEXT: xvcvsxddp vs2, v3 +; CHECK-P8-NEXT: vsrad v3, v3, v0 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5 +; CHECK-P8-NEXT: xvcvsxddp vs2, v3 ; CHECK-P8-NEXT: xvcvsxddp vs3, v4 -; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 +; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r8 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: stest8: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC3@toc@ha +; CHECK-P9-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -306,30 +270,24 @@ ; CHECK-BE-LABEL: stest8: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -346,17 +304,15 @@ define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { ; CHECK-P8-LABEL: stest4: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI4_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI4_2@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC5@toc@ha +; CHECK-P8-NEXT: addis r6, r2, .LC6@toc@ha +; CHECK-P8-NEXT: li r7, 16 ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI4_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI4_0@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI4_1@toc@l +; CHECK-P8-NEXT: ld r5, .LC5@toc@l(r5) +; CHECK-P8-NEXT: ld r6, .LC6@toc@l(r6) ; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI4_2@toc@l -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: lvx v4, 0, r5 +; CHECK-P8-NEXT: lvx v4, r5, r7 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r6 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: xxswapd v4, vs0 @@ -368,22 +324,20 @@ ; CHECK-P8-NEXT: xvcvsxddp vs1, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: stest4: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC4@toc@ha +; CHECK-P9-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -394,13 +348,11 @@ ; CHECK-BE-LABEL: stest4: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha -; CHECK-BE-NEXT: xxlxor v3, v3, v3 -; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l -; CHECK-BE-NEXT: vperm v3, v3, v2, v4 +; CHECK-BE-NEXT: addis r4, r2, .LC4@toc@ha +; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: ld r4, .LC4@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 16(r4) +; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 @@ -420,14 +372,14 @@ define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { ; CHECK-P8-LABEL: stest2: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC7@toc@ha +; CHECK-P8-NEXT: addis r6, r2, .LC8@toc@ha ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l +; CHECK-P8-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 +; CHECK-P8-NEXT: ld r5, .LC8@toc@l(r6) ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r5 ; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3 @@ -439,8 +391,8 @@ ; CHECK-P9-LABEL: stest2: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-P9-NEXT: ld r4, .LC5@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -451,8 +403,8 @@ ; CHECK-BE-LABEL: stest2: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l +; CHECK-BE-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-BE-NEXT: ld r4, .LC5@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 diff --git a/llvm/test/CodeGen/PowerPC/vec-trunc.ll b/llvm/test/CodeGen/PowerPC/vec-trunc.ll --- a/llvm/test/CodeGen/PowerPC/vec-trunc.ll +++ b/llvm/test/CodeGen/PowerPC/vec-trunc.ll @@ -59,9 +59,9 @@ define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) { ; CHECK-LABEL: test4i8w: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis r5, r2, .LCPI2_0@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: lvx v3, 0, r4 -; CHECK-NEXT: addi r5, r5, .LCPI2_0@toc@l +; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: lvx v2, 0, r5 ; CHECK-NEXT: vperm v2, v3, v3, v2 ; CHECK-NEXT: xxsldwi vs0, v2, v2, 2 @@ -70,11 +70,11 @@ ; ; CHECK-BE-LABEL: test4i8w: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: lxvw4x v2, 0, r4 -; CHECK-BE-NEXT: addi r4, r5, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvw4x v3, 0, r4 +; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: addi r4, r1, -16 +; CHECK-BE-NEXT: lxvw4x v3, 0, r5 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lwz r4, -16(r1) @@ -167,11 +167,11 @@ define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) { ; CHECK-LABEL: test2i16d: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC1@toc@ha ; CHECK-NEXT: lxvd2x vs0, 0, r4 -; CHECK-NEXT: addis r5, r2, .LCPI6_0@toc@ha -; CHECK-NEXT: addi r4, r5, .LCPI6_0@toc@l -; CHECK-NEXT: lvx v3, 0, r4 +; CHECK-NEXT: ld r4, .LC1@toc@l(r5) ; CHECK-NEXT: xxswapd v2, vs0 +; CHECK-NEXT: lvx v3, 0, r4 ; CHECK-NEXT: vperm v2, v2, v2, v3 ; CHECK-NEXT: xxsldwi vs0, v2, v2, 2 ; CHECK-NEXT: stfiwx f0, 0, r3 @@ -179,11 +179,11 @@ ; ; CHECK-BE-LABEL: test2i16d: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha +; CHECK-BE-NEXT: addis r5, r2, .LC1@toc@ha ; CHECK-BE-NEXT: lxvw4x v2, 0, r4 -; CHECK-BE-NEXT: addi r4, r5, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvw4x v3, 0, r4 +; CHECK-BE-NEXT: ld r5, .LC1@toc@l(r5) ; CHECK-BE-NEXT: addi r4, r1, -16 +; CHECK-BE-NEXT: lxvw4x v3, 0, r5 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lwz r4, -16(r1) diff --git a/llvm/test/CodeGen/PowerPC/vec-trunc2.ll b/llvm/test/CodeGen/PowerPC/vec-trunc2.ll --- a/llvm/test/CodeGen/PowerPC/vec-trunc2.ll +++ b/llvm/test/CodeGen/PowerPC/vec-trunc2.ll @@ -9,18 +9,18 @@ define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) { ; CHECK-LABEL: test8x32: ; CHECK: # %bb.0: +; CHECK-NEXT: addis r11, r2, .LC0@toc@ha ; CHECK-NEXT: rldimi r3, r4, 32, 0 ; CHECK-NEXT: rldimi r5, r6, 32, 0 -; CHECK-NEXT: addis r11, r2, .LCPI0_0@toc@ha +; CHECK-NEXT: mtfprd f0, r3 ; CHECK-NEXT: rldimi r7, r8, 32, 0 ; CHECK-NEXT: rldimi r9, r10, 32, 0 -; CHECK-NEXT: mtfprd f0, r3 -; CHECK-NEXT: addi r3, r11, .LCPI0_0@toc@l +; CHECK-NEXT: ld r3, .LC0@toc@l(r11) ; CHECK-NEXT: mtfprd f1, r5 -; CHECK-NEXT: lvx v4, 0, r3 ; CHECK-NEXT: mtfprd f2, r7 ; CHECK-NEXT: mtfprd f3, r9 ; CHECK-NEXT: xxmrghd v2, vs1, vs0 +; CHECK-NEXT: lvx v4, 0, r3 ; CHECK-NEXT: xxmrghd v3, vs3, vs2 ; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: blr @@ -34,6 +34,7 @@ ; CHECK-BE-NEXT: stw r6, -16(r1) ; CHECK-BE-NEXT: stw r5, -32(r1) ; CHECK-BE-NEXT: stw r4, -48(r1) +; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: stw r3, -64(r1) ; CHECK-BE-NEXT: addi r3, r1, -80 ; CHECK-BE-NEXT: lxvw4x v2, 0, r3 @@ -48,16 +49,15 @@ ; CHECK-BE-NEXT: addi r3, r1, -32 ; CHECK-BE-NEXT: lxvw4x v1, 0, r3 ; CHECK-BE-NEXT: addi r3, r1, -48 +; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: lxvw4x v6, 0, r3 ; CHECK-BE-NEXT: addi r3, r1, -64 ; CHECK-BE-NEXT: lxvw4x v7, 0, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v4, v1, v0 -; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-BE-NEXT: lxvw4x v8, 0, r4 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2 -; CHECK-BE-NEXT: lxvw4x v8, 0, r3 ; CHECK-BE-NEXT: vmrghw v5, v7, v6 ; CHECK-BE-NEXT: xxmrghd v3, v5, v4 ; CHECK-BE-NEXT: vperm v2, v3, v2, v8 @@ -77,11 +77,11 @@ define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) { ; CHECK-LABEL: test4x64: ; CHECK: # %bb.0: -; CHECK-NEXT: addis r7, r2, .LCPI1_0@toc@ha +; CHECK-NEXT: addis r7, r2, .LC1@toc@ha +; CHECK-NEXT: mtfprd f2, r3 +; CHECK-NEXT: ld r3, .LC1@toc@l(r7) ; CHECK-NEXT: mtfprd f0, r5 ; CHECK-NEXT: mtfprd f1, r6 -; CHECK-NEXT: mtfprd f2, r3 -; CHECK-NEXT: addi r3, r7, .LCPI1_0@toc@l ; CHECK-NEXT: mtfprd f3, r4 ; CHECK-NEXT: xxmrghd v2, vs1, vs0 ; CHECK-NEXT: lvx v4, 0, r3 @@ -91,16 +91,16 @@ ; ; CHECK-BE-LABEL: test4x64: ; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: addis r7, r2, .LC1@toc@ha +; CHECK-BE-NEXT: std r3, -32(r1) ; CHECK-BE-NEXT: std r6, -8(r1) ; CHECK-BE-NEXT: std r5, -16(r1) +; CHECK-BE-NEXT: addi r5, r1, -16 +; CHECK-BE-NEXT: ld r3, .LC1@toc@l(r7) ; CHECK-BE-NEXT: std r4, -24(r1) -; CHECK-BE-NEXT: std r3, -32(r1) -; CHECK-BE-NEXT: addi r3, r1, -32 -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha -; CHECK-BE-NEXT: addi r7, r1, -16 -; CHECK-BE-NEXT: lxvd2x v3, 0, r3 -; CHECK-BE-NEXT: addi r3, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvd2x v2, 0, r7 +; CHECK-BE-NEXT: addi r4, r1, -32 +; CHECK-BE-NEXT: lxvd2x v2, 0, r5 +; CHECK-BE-NEXT: lxvd2x v3, 0, r4 ; CHECK-BE-NEXT: lxvw4x v4, 0, r3 ; CHECK-BE-NEXT: vperm v2, v3, v2, v4 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll --- a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll +++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll @@ -16,16 +16,16 @@ define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind { ; VSX-LABEL: increment_by_one: ; VSX: # %bb.0: -; VSX-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; VSX-NEXT: addi 3, 3, .LCPI1_0@toc@l +; VSX-NEXT: addis 3, 2, .LC0@toc@ha +; VSX-NEXT: ld 3, .LC0@toc@l(3) ; VSX-NEXT: lxvd2x 35, 0, 3 ; VSX-NEXT: vaddudm 2, 2, 3 ; VSX-NEXT: blr ; ; NOVSX-LABEL: increment_by_one: ; NOVSX: # %bb.0: -; NOVSX-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; NOVSX-NEXT: addi 3, 3, .LCPI1_0@toc@l +; NOVSX-NEXT: addis 3, 2, .LC0@toc@ha +; NOVSX-NEXT: ld 3, .LC0@toc@l(3) ; NOVSX-NEXT: lvx 3, 0, 3 ; NOVSX-NEXT: vaddudm 2, 2, 3 ; NOVSX-NEXT: blr @@ -86,8 +86,8 @@ ; ; NOVSX-LABEL: decrement_by_one: ; NOVSX: # %bb.0: -; NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; NOVSX-NEXT: addi 3, 3, .LCPI4_0@toc@l +; NOVSX-NEXT: addis 3, 2, .LC1@toc@ha +; NOVSX-NEXT: ld 3, .LC1@toc@l(3) ; NOVSX-NEXT: lvx 3, 0, 3 ; NOVSX-NEXT: vsubudm 2, 2, 3 ; NOVSX-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll --- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -25,16 +25,16 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind { ; VSX-LABEL: increment_by_one: ; VSX: # %bb.0: -; VSX-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; VSX-NEXT: addi 3, 3, .LCPI2_0@toc@l +; VSX-NEXT: addis 3, 2, .LC0@toc@ha +; VSX-NEXT: ld 3, .LC0@toc@l(3) ; VSX-NEXT: lxvd2x 35, 0, 3 ; VSX-NEXT: vadduqm 2, 2, 3 ; VSX-NEXT: blr ; ; NOVSX-LABEL: increment_by_one: ; NOVSX: # %bb.0: -; NOVSX-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; NOVSX-NEXT: addi 3, 3, .LCPI2_0@toc@l +; NOVSX-NEXT: addis 3, 2, .LC0@toc@ha +; NOVSX-NEXT: ld 3, .LC0@toc@l(3) ; NOVSX-NEXT: lvx 3, 0, 3 ; NOVSX-NEXT: vadduqm 2, 2, 3 ; NOVSX-NEXT: blr @@ -76,16 +76,16 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind { ; VSX-LABEL: decrement_by_one: ; VSX: # %bb.0: -; VSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; VSX-NEXT: addi 3, 3, .LCPI5_0@toc@l +; VSX-NEXT: addis 3, 2, .LC1@toc@ha +; VSX-NEXT: ld 3, .LC1@toc@l(3) ; VSX-NEXT: lxvd2x 35, 0, 3 ; VSX-NEXT: vsubuqm 2, 2, 3 ; VSX-NEXT: blr ; ; NOVSX-LABEL: decrement_by_one: ; NOVSX: # %bb.0: -; NOVSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; NOVSX-NEXT: addi 3, 3, .LCPI5_0@toc@l +; NOVSX-NEXT: addis 3, 2, .LC1@toc@ha +; NOVSX-NEXT: ld 3, .LC1@toc@l(3) ; NOVSX-NEXT: lvx 3, 0, 3 ; NOVSX-NEXT: vsubuqm 2, 2, 3 ; NOVSX-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll @@ -97,9 +97,9 @@ ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2 @@ -136,15 +136,13 @@ ; ; CHECK-BE-LABEL: test8elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 @@ -159,80 +157,74 @@ define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI3_1@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: xxlxor v3, v3, v3 ; CHECK-P8-NEXT: lvx v4, 0, r4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI3_1@toc@l -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: li r5, 16 -; CHECK-P8-NEXT: lvx v0, 0, r6 -; CHECK-P8-NEXT: li r6, 32 -; CHECK-P8-NEXT: lvx v5, r4, r5 +; CHECK-P8-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-P8-NEXT: lvx v0, r4, r6 ; CHECK-P8-NEXT: li r4, 48 +; CHECK-P8-NEXT: lvx v2, 0, r5 +; CHECK-P8-NEXT: lvx v5, r5, r6 +; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: vperm v1, v3, v4, v2 -; CHECK-P8-NEXT: vperm v2, v3, v5, v2 -; CHECK-P8-NEXT: vperm v5, v3, v5, v0 -; CHECK-P8-NEXT: vperm v3, v3, v4, v0 +; CHECK-P8-NEXT: vperm v6, v3, v0, v5 +; CHECK-P8-NEXT: vperm v2, v3, v0, v2 +; CHECK-P8-NEXT: vperm v3, v3, v4, v5 ; CHECK-P8-NEXT: xvcvuxwsp v4, v1 +; CHECK-P8-NEXT: xvcvuxwsp v5, v6 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2 -; CHECK-P8-NEXT: xvcvuxwsp v5, v5 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: stvx v4, 0, r3 -; CHECK-P8-NEXT: stvx v2, r3, r6 ; CHECK-P8-NEXT: stvx v5, r3, r4 -; CHECK-P8-NEXT: stvx v3, r3, r5 +; CHECK-P8-NEXT: stvx v2, r3, r5 +; CHECK-P8-NEXT: stvx v3, r3, r6 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: lxv v2, 16(r4) -; CHECK-P9-NEXT: lxv v3, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: xxlxor v5, v5, v5 -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v4, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l -; CHECK-P9-NEXT: vperm v0, v5, v3, v4 -; CHECK-P9-NEXT: xvcvuxwsp vs0, v0 -; CHECK-P9-NEXT: lxvx v0, 0, r4 -; CHECK-P9-NEXT: vperm v3, v5, v3, v0 +; CHECK-P9-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-P9-NEXT: lxv v2, 0(r4) +; CHECK-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-P9-NEXT: ld r5, .LC0@toc@l(r5) +; CHECK-P9-NEXT: lxvx v3, 0, r5 +; CHECK-P9-NEXT: lxv v0, 16(r5) +; CHECK-P9-NEXT: vperm v5, v4, v2, v3 +; CHECK-P9-NEXT: vperm v2, v4, v2, v0 +; CHECK-P9-NEXT: xvcvuxwsp vs0, v5 +; CHECK-P9-NEXT: lxv v5, 16(r4) +; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 +; CHECK-P9-NEXT: vperm v2, v4, v5, v3 +; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3) -; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 -; CHECK-P9-NEXT: vperm v3, v5, v2, v4 -; CHECK-P9-NEXT: vperm v2, v5, v2, v0 -; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 +; CHECK-P9-NEXT: xvcvuxwsp vs2, v2 +; CHECK-P9-NEXT: vperm v2, v4, v5, v0 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 -; CHECK-P9-NEXT: stxv vs1, 16(r3) -; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3) +; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: blr ; ; CHECK-BE-LABEL: test16elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: lxv v2, 16(r4) -; CHECK-BE-NEXT: lxv v3, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-BE-NEXT: xxlxor v5, v5, v5 -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l -; CHECK-BE-NEXT: vperm v0, v3, v5, v4 -; CHECK-BE-NEXT: xvcvuxwsp vs0, v0 -; CHECK-BE-NEXT: lxvx v0, 0, r4 -; CHECK-BE-NEXT: vperm v3, v5, v3, v0 +; CHECK-BE-NEXT: addis r5, r2, .LC2@toc@ha +; CHECK-BE-NEXT: lxv v2, 0(r4) +; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: ld r5, .LC2@toc@l(r5) +; CHECK-BE-NEXT: lxvx v3, 0, r5 +; CHECK-BE-NEXT: lxv v0, 16(r5) +; CHECK-BE-NEXT: vperm v5, v2, v4, v3 +; CHECK-BE-NEXT: vperm v2, v4, v2, v0 +; CHECK-BE-NEXT: xvcvuxwsp vs0, v5 +; CHECK-BE-NEXT: lxv v5, 16(r4) +; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 +; CHECK-BE-NEXT: vperm v2, v5, v4, v3 +; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3) -; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 -; CHECK-BE-NEXT: vperm v3, v2, v5, v4 -; CHECK-BE-NEXT: vperm v2, v5, v2, v0 -; CHECK-BE-NEXT: xvcvuxwsp vs2, v3 +; CHECK-BE-NEXT: xvcvuxwsp vs2, v2 +; CHECK-BE-NEXT: vperm v2, v4, v5, v0 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 -; CHECK-BE-NEXT: stxv vs1, 16(r3) -; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3) +; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: blr entry: %a = load <16 x i16>, <16 x i16>* %0, align 32 @@ -374,9 +366,9 @@ ; ; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v2 @@ -451,9 +443,9 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC4@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: vperm v0, v5, v3, v4 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll @@ -12,9 +12,9 @@ define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 { ; CHECK-P8-LABEL: test2elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mtvsrwz v2, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3 @@ -24,9 +24,9 @@ ; CHECK-P9-LABEL: test2elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp v2, v2 @@ -35,9 +35,9 @@ ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp v2, v2 @@ -51,37 +51,33 @@ define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC1@toc@ha +; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: mtvsrd v2, r4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l -; CHECK-P8-NEXT: addi r4, r6, .LCPI1_1@toc@l +; CHECK-P8-NEXT: ld r5, .LC1@toc@l(r5) ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: lvx v3, 0, r5 -; CHECK-P8-NEXT: lvx v5, 0, r4 -; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: lvx v3, r5, r6 +; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v5 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs1, v2 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test4elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrd v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l +; CHECK-P9-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -91,15 +87,13 @@ ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -115,21 +109,16 @@ define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addis r5, r2, .LCPI2_2@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha +; CHECK-P8-NEXT: li r5, 16 +; CHECK-P8-NEXT: li r6, 48 +; CHECK-P8-NEXT: li r7, 32 ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI2_2@toc@l +; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r4 -; CHECK-P8-NEXT: lvx v1, 0, r5 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: li r5, 32 +; CHECK-P8-NEXT: lvx v5, r4, r5 +; CHECK-P8-NEXT: lvx v0, r4, r6 +; CHECK-P8-NEXT: lvx v1, r4, r7 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0 @@ -142,36 +131,29 @@ ; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test8elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-P9-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -180,27 +162,21 @@ ; ; CHECK-BE-LABEL: test8elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -215,87 +191,75 @@ define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC3@toc@ha +; CHECK-P8-NEXT: li r6, 16 +; CHECK-P8-NEXT: li r7, 32 ; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: xxlxor v3, v3, v3 -; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l -; CHECK-P8-NEXT: lvx v5, 0, r6 -; CHECK-P8-NEXT: li r6, 16 -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha +; CHECK-P8-NEXT: li r8, 96 +; CHECK-P8-NEXT: ld r5, .LC3@toc@l(r5) ; CHECK-P8-NEXT: lvx v0, r4, r6 -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l -; CHECK-P8-NEXT: lvx v1, 0, r5 -; CHECK-P8-NEXT: li r5, 96 -; CHECK-P8-NEXT: lvx v8, 0, r4 +; CHECK-P8-NEXT: li r4, 48 +; CHECK-P8-NEXT: lvx v2, 0, r5 +; CHECK-P8-NEXT: lvx v5, r5, r6 +; CHECK-P8-NEXT: lvx v1, r5, r7 +; CHECK-P8-NEXT: lvx v7, r5, r4 +; CHECK-P8-NEXT: li r5, 112 ; CHECK-P8-NEXT: vperm v6, v3, v4, v2 -; CHECK-P8-NEXT: li r4, 112 -; CHECK-P8-NEXT: vperm v7, v3, v4, v5 -; CHECK-P8-NEXT: vperm v2, v3, v0, v2 +; CHECK-P8-NEXT: vperm v8, v3, v0, v5 ; CHECK-P8-NEXT: vperm v9, v3, v0, v1 -; CHECK-P8-NEXT: vperm v5, v3, v0, v5 -; CHECK-P8-NEXT: vperm v0, v3, v0, v8 +; CHECK-P8-NEXT: vperm v2, v3, v0, v2 +; CHECK-P8-NEXT: vperm v0, v3, v0, v7 ; CHECK-P8-NEXT: vperm v1, v3, v4, v1 -; CHECK-P8-NEXT: vperm v3, v3, v4, v8 -; CHECK-P8-NEXT: xvcvuxddp vs1, v2 -; CHECK-P8-NEXT: xvcvuxddp vs4, v9 -; CHECK-P8-NEXT: xvcvuxddp vs2, v5 -; CHECK-P8-NEXT: xvcvuxddp vs3, v0 -; CHECK-P8-NEXT: xvcvuxddp vs0, v7 +; CHECK-P8-NEXT: vperm v5, v3, v4, v5 +; CHECK-P8-NEXT: vperm v3, v3, v4, v7 +; CHECK-P8-NEXT: xvcvuxddp vs1, v9 +; CHECK-P8-NEXT: xvcvuxddp vs0, v8 +; CHECK-P8-NEXT: xvcvuxddp vs2, v0 +; CHECK-P8-NEXT: xvcvuxddp vs3, v1 +; CHECK-P8-NEXT: xvcvuxddp vs4, v2 ; CHECK-P8-NEXT: xvcvuxddp vs5, v3 ; CHECK-P8-NEXT: xvcvuxddp vs6, v6 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: xvcvuxddp vs7, v1 -; CHECK-P8-NEXT: xxswapd vs4, vs4 +; CHECK-P8-NEXT: xvcvuxddp vs7, v5 +; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: xxswapd vs0, vs0 +; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: xxswapd vs5, vs5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 -; CHECK-P8-NEXT: li r4, 80 -; CHECK-P8-NEXT: li r5, 64 -; CHECK-P8-NEXT: xxswapd vs2, vs7 -; CHECK-P8-NEXT: xxswapd vs3, vs6 -; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 +; CHECK-P8-NEXT: li r5, 80 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r8 +; CHECK-P8-NEXT: xxswapd vs2, vs6 +; CHECK-P8-NEXT: li r8, 64 +; CHECK-P8-NEXT: xxswapd vs1, vs7 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 -; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 +; CHECK-P8-NEXT: stxvd2x vs4, r3, r8 +; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4) -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-P9-NEXT: xxlxor v5, v5, v5 -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l +; CHECK-P9-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-P9-NEXT: lxvx v4, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0 -; CHECK-P9-NEXT: lxvx v0, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l +; CHECK-P9-NEXT: lxv v0, 16(r4) ; CHECK-P9-NEXT: vperm v1, v5, v3, v0 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v1 -; CHECK-P9-NEXT: lxvx v1, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l +; CHECK-P9-NEXT: lxv v1, 32(r4) ; CHECK-P9-NEXT: vperm v6, v5, v3, v1 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v6 -; CHECK-P9-NEXT: lxvx v6, 0, r4 +; CHECK-P9-NEXT: lxv v6, 48(r4) ; CHECK-P9-NEXT: vperm v3, v5, v3, v6 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v3 @@ -318,27 +282,21 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4) -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0 -; CHECK-BE-NEXT: lxvx v0, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l +; CHECK-BE-NEXT: lxv v0, 16(r4) ; CHECK-BE-NEXT: vperm v1, v5, v3, v0 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v1 -; CHECK-BE-NEXT: lxvx v1, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l +; CHECK-BE-NEXT: lxv v1, 32(r4) ; CHECK-BE-NEXT: vperm v6, v5, v3, v1 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v6 -; CHECK-BE-NEXT: lxvx v6, 0, r4 +; CHECK-BE-NEXT: lxv v6, 48(r4) ; CHECK-BE-NEXT: vperm v3, v5, v3, v6 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v3 @@ -366,14 +324,14 @@ define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 { ; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC5@toc@ha ; CHECK-P8-NEXT: mtvsrwz v3, r3 -; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l +; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 -; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r5) ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3 @@ -383,8 +341,8 @@ ; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-P9-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -394,8 +352,8 @@ ; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-BE-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-BE-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -410,17 +368,15 @@ define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC6@toc@ha +; CHECK-P8-NEXT: li r6, 16 +; CHECK-P8-NEXT: addis r7, r2, .LC7@toc@ha ; CHECK-P8-NEXT: mtvsrd v3, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 -; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: ld r5, .LC6@toc@l(r5) +; CHECK-P8-NEXT: ld r7, .LC7@toc@l(r7) +; CHECK-P8-NEXT: lvx v2, r5, r6 ; CHECK-P8-NEXT: lvx v4, 0, r5 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r7 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: xxswapd v4, vs0 @@ -432,18 +388,16 @@ ; CHECK-P8-NEXT: xvcvsxddp vs1, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrd v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-P9-NEXT: ld r4, .LC5@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 @@ -458,13 +412,11 @@ ; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha -; CHECK-BE-NEXT: xxlxor v3, v3, v3 -; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l -; CHECK-BE-NEXT: vperm v3, v3, v2, v4 +; CHECK-BE-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: ld r4, .LC5@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 16(r4) +; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 @@ -484,23 +436,18 @@ define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha -; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI6_2@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l -; CHECK-P8-NEXT: lvx v4, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI6_4@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC8@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC9@toc@ha +; CHECK-P8-NEXT: li r6, 32 +; CHECK-P8-NEXT: li r7, 16 +; CHECK-P8-NEXT: li r8, 48 +; CHECK-P8-NEXT: ld r4, .LC8@toc@l(r4) +; CHECK-P8-NEXT: ld r5, .LC9@toc@l(r5) ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: lvx v5, 0, r6 -; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI6_4@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r5 -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: li r5, 32 +; CHECK-P8-NEXT: lvx v4, r4, r6 +; CHECK-P8-NEXT: lvx v5, r4, r7 +; CHECK-P8-NEXT: lvx v0, r4, r8 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r5 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5 @@ -511,49 +458,42 @@ ; CHECK-P8-NEXT: vsld v5, v5, v0 ; CHECK-P8-NEXT: vsld v2, v2, v0 ; CHECK-P8-NEXT: vsrad v3, v3, v0 -; CHECK-P8-NEXT: vsrad v2, v2, v0 ; CHECK-P8-NEXT: vsrad v4, v4, v0 ; CHECK-P8-NEXT: vsrad v5, v5, v0 -; CHECK-P8-NEXT: xvcvsxddp vs2, v2 +; CHECK-P8-NEXT: vsrad v2, v2, v0 ; CHECK-P8-NEXT: xvcvsxddp vs0, v3 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5 +; CHECK-P8-NEXT: xvcvsxddp vs2, v2 ; CHECK-P8-NEXT: xvcvsxddp vs3, v4 -; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 +; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r8 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC6@toc@ha +; CHECK-P9-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -563,30 +503,24 @@ ; ; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-BE-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -602,115 +536,103 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI7_2@toc@ha -; CHECK-P8-NEXT: lvx v4, 0, r4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_0@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI7_2@toc@l -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_3@toc@ha -; CHECK-P8-NEXT: lvx v3, 0, r6 -; CHECK-P8-NEXT: addis r6, r2, .LCPI7_4@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_3@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI7_4@toc@l -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: lvx v0, 0, r6 +; CHECK-P8-NEXT: addis r5, r2, .LC10@toc@ha ; CHECK-P8-NEXT: li r6, 16 -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha -; CHECK-P8-NEXT: lvx v7, r4, r6 -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-P8-NEXT: vperm v1, v4, v4, v2 +; CHECK-P8-NEXT: li r7, 32 +; CHECK-P8-NEXT: addis r8, r2, .LC11@toc@ha +; CHECK-P8-NEXT: li r9, 48 +; CHECK-P8-NEXT: lvx v6, 0, r4 +; CHECK-P8-NEXT: ld r5, .LC10@toc@l(r5) +; CHECK-P8-NEXT: ld r8, .LC11@toc@l(r8) +; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: li r4, 112 -; CHECK-P8-NEXT: vperm v6, v4, v4, v3 -; CHECK-P8-NEXT: lxvd2x vs0, 0, r5 +; CHECK-P8-NEXT: lvx v2, r5, r6 +; CHECK-P8-NEXT: lvx v4, r5, r7 +; CHECK-P8-NEXT: lvx v5, r5, r9 +; CHECK-P8-NEXT: lvx v0, 0, r5 ; CHECK-P8-NEXT: li r5, 96 -; CHECK-P8-NEXT: vperm v8, v4, v4, v5 -; CHECK-P8-NEXT: vperm v4, v4, v4, v0 -; CHECK-P8-NEXT: vperm v5, v7, v7, v5 -; CHECK-P8-NEXT: xxswapd v9, vs0 -; CHECK-P8-NEXT: vperm v0, v7, v7, v0 -; CHECK-P8-NEXT: vperm v2, v7, v7, v2 -; CHECK-P8-NEXT: vperm v3, v7, v7, v3 -; CHECK-P8-NEXT: vsld v1, v1, v9 -; CHECK-P8-NEXT: vsld v6, v6, v9 -; CHECK-P8-NEXT: vsld v5, v5, v9 -; CHECK-P8-NEXT: vsld v0, v0, v9 -; CHECK-P8-NEXT: vsld v2, v2, v9 -; CHECK-P8-NEXT: vsld v3, v3, v9 -; CHECK-P8-NEXT: vsrad v5, v5, v9 -; CHECK-P8-NEXT: vsrad v0, v0, v9 -; CHECK-P8-NEXT: vsld v7, v8, v9 -; CHECK-P8-NEXT: vsld v4, v4, v9 -; CHECK-P8-NEXT: vsrad v2, v2, v9 -; CHECK-P8-NEXT: vsrad v3, v3, v9 -; CHECK-P8-NEXT: xvcvsxddp vs2, v5 -; CHECK-P8-NEXT: xvcvsxddp vs3, v0 -; CHECK-P8-NEXT: vsrad v1, v1, v9 -; CHECK-P8-NEXT: vsrad v6, v6, v9 -; CHECK-P8-NEXT: vsrad v7, v7, v9 -; CHECK-P8-NEXT: vsrad v4, v4, v9 -; CHECK-P8-NEXT: xvcvsxddp vs1, v2 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r8 +; CHECK-P8-NEXT: vperm v1, v3, v3, v2 +; CHECK-P8-NEXT: vperm v7, v3, v3, v4 +; CHECK-P8-NEXT: xxswapd v10, vs0 +; CHECK-P8-NEXT: vperm v8, v3, v3, v5 +; CHECK-P8-NEXT: vperm v9, v6, v6, v0 +; CHECK-P8-NEXT: vperm v2, v6, v6, v2 +; CHECK-P8-NEXT: vperm v4, v6, v6, v4 +; CHECK-P8-NEXT: vperm v5, v6, v6, v5 +; CHECK-P8-NEXT: vperm v3, v3, v3, v0 +; CHECK-P8-NEXT: vsld v0, v1, v10 +; CHECK-P8-NEXT: vsld v1, v7, v10 +; CHECK-P8-NEXT: vsld v6, v8, v10 +; CHECK-P8-NEXT: vsrad v1, v1, v10 +; CHECK-P8-NEXT: vsrad v6, v6, v10 +; CHECK-P8-NEXT: vsld v7, v9, v10 +; CHECK-P8-NEXT: vsld v2, v2, v10 +; CHECK-P8-NEXT: vsld v4, v4, v10 +; CHECK-P8-NEXT: vsld v5, v5, v10 +; CHECK-P8-NEXT: vsld v3, v3, v10 +; CHECK-P8-NEXT: xvcvsxddp vs1, v1 +; CHECK-P8-NEXT: xvcvsxddp vs2, v6 +; CHECK-P8-NEXT: vsrad v0, v0, v10 +; CHECK-P8-NEXT: vsrad v7, v7, v10 +; CHECK-P8-NEXT: vsrad v2, v2, v10 +; CHECK-P8-NEXT: vsrad v4, v4, v10 +; CHECK-P8-NEXT: vsrad v5, v5, v10 +; CHECK-P8-NEXT: xxswapd vs1, vs1 +; CHECK-P8-NEXT: vsrad v3, v3, v10 ; CHECK-P8-NEXT: xxswapd vs2, vs2 +; CHECK-P8-NEXT: xvcvsxddp vs0, v0 +; CHECK-P8-NEXT: xvcvsxddp vs3, v4 ; CHECK-P8-NEXT: xvcvsxddp vs4, v3 -; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: xvcvsxddp vs0, v7 -; CHECK-P8-NEXT: xvcvsxddp vs5, v4 -; CHECK-P8-NEXT: xvcvsxddp vs6, v1 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: li r4, 80 -; CHECK-P8-NEXT: xvcvsxddp vs7, v6 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 +; CHECK-P8-NEXT: xvcvsxddp vs5, v5 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: li r5, 64 -; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: xxswapd vs4, vs4 +; CHECK-P8-NEXT: xvcvsxddp vs6, v7 +; CHECK-P8-NEXT: xvcvsxddp vs7, v2 ; CHECK-P8-NEXT: xxswapd vs0, vs0 +; CHECK-P8-NEXT: xxswapd vs3, vs3 +; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: xxswapd vs5, vs5 -; CHECK-P8-NEXT: xxswapd vs3, vs6 -; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: xxswapd vs2, vs7 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 -; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 +; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 +; CHECK-P8-NEXT: xxswapd vs2, vs6 +; CHECK-P8-NEXT: xxswapd vs1, vs7 +; CHECK-P8-NEXT: stxvd2x vs4, r3, r5 +; CHECK-P8-NEXT: stxvd2x vs5, r3, r9 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha +; CHECK-P9-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-P9-NEXT: lxv v2, 0(r4) -; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l +; CHECK-P9-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-P9-NEXT: lxvx v3, 0, r5 -; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha -; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-P9-NEXT: lxvx v5, 0, r5 -; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha +; CHECK-P9-NEXT: lxv v5, 16(r5) +; CHECK-P9-NEXT: lxv v0, 32(r5) +; CHECK-P9-NEXT: lxv v1, 48(r5) ; CHECK-P9-NEXT: vperm v4, v2, v2, v3 -; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vextsh2d v4, v4 -; CHECK-P9-NEXT: lxvx v0, 0, r5 -; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: xvcvsxddp vs0, v4 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5 -; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l -; CHECK-P9-NEXT: lxvx v1, 0, r5 ; CHECK-P9-NEXT: vextsh2d v4, v4 +; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0 ; CHECK-P9-NEXT: vperm v2, v2, v2, v1 -; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v4, v4 +; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp vs2, v4 ; CHECK-P9-NEXT: lxv v4, 16(r4) -; CHECK-P9-NEXT: stxv vs1, 16(r3) -; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2 +; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vperm v2, v4, v4, v3 +; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 -; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: xvcvsxddp vs4, v2 ; CHECK-P9-NEXT: vperm v2, v4, v4, v5 ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -729,53 +651,47 @@ ; ; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha -; CHECK-BE-NEXT: lxv v4, 0(r4) -; CHECK-BE-NEXT: lxv v1, 16(r4) +; CHECK-BE-NEXT: lxv v2, 16(r4) +; CHECK-BE-NEXT: lxv v3, 0(r4) +; CHECK-BE-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha -; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l -; CHECK-BE-NEXT: lxvx v2, 0, r5 -; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha -; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r5 -; CHECK-BE-NEXT: vperm v0, v5, v4, v2 -; CHECK-BE-NEXT: vperm v2, v5, v1, v2 -; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: ld r4, .LC7@toc@l(r4) +; CHECK-BE-NEXT: lxv v4, 16(r4) +; CHECK-BE-NEXT: vperm v0, v5, v3, v4 +; CHECK-BE-NEXT: vperm v4, v5, v2, v4 ; CHECK-BE-NEXT: vextsh2d v0, v0 -; CHECK-BE-NEXT: xvcvsxddp vs2, v2 -; CHECK-BE-NEXT: vperm v2, v5, v1, v3 +; CHECK-BE-NEXT: vextsh2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v0 -; CHECK-BE-NEXT: vperm v0, v5, v4, v3 -; CHECK-BE-NEXT: vextsh2d v2, v2 -; CHECK-BE-NEXT: vextsh2d v0, v0 -; CHECK-BE-NEXT: xvcvsxddp vs3, v2 -; CHECK-BE-NEXT: lxvx v2, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha -; CHECK-BE-NEXT: xvcvsxddp vs1, v0 -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l +; CHECK-BE-NEXT: lxv v0, 48(r4) +; CHECK-BE-NEXT: xvcvsxddp vs2, v4 +; CHECK-BE-NEXT: vperm v4, v5, v2, v0 +; CHECK-BE-NEXT: vperm v1, v5, v3, v0 ; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3) -; CHECK-BE-NEXT: vperm v3, v4, v4, v2 -; CHECK-BE-NEXT: vperm v2, v1, v1, v2 +; CHECK-BE-NEXT: vextsh2d v4, v4 +; CHECK-BE-NEXT: vextsh2d v1, v1 +; CHECK-BE-NEXT: xvcvsxddp vs3, v4 +; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: xvcvsxddp vs1, v1 +; CHECK-BE-NEXT: vperm v5, v3, v3, v4 ; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3) -; CHECK-BE-NEXT: vextsh2d v3, v3 -; CHECK-BE-NEXT: vextsh2d v2, v2 -; CHECK-BE-NEXT: xvcvsxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: xvcvsxddp vs6, v2 -; CHECK-BE-NEXT: vperm v4, v4, v4, v3 -; CHECK-BE-NEXT: vperm v2, v1, v1, v3 -; CHECK-BE-NEXT: stxv vs6, 64(r3) +; CHECK-BE-NEXT: vextsh2d v5, v5 +; CHECK-BE-NEXT: xvcvsxddp vs4, v5 +; CHECK-BE-NEXT: lxv v5, 32(r4) +; CHECK-BE-NEXT: vperm v3, v3, v3, v5 ; CHECK-BE-NEXT: stxv vs4, 0(r3) -; CHECK-BE-NEXT: vextsh2d v4, v4 +; CHECK-BE-NEXT: vextsh2d v3, v3 +; CHECK-BE-NEXT: xvcvsxddp vs5, v3 +; CHECK-BE-NEXT: vperm v3, v2, v2, v4 +; CHECK-BE-NEXT: vperm v2, v2, v2, v5 +; CHECK-BE-NEXT: stxv vs5, 32(r3) +; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 -; CHECK-BE-NEXT: xvcvsxddp vs5, v4 +; CHECK-BE-NEXT: xvcvsxddp vs6, v3 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2 ; CHECK-BE-NEXT: stxv vs7, 96(r3) -; CHECK-BE-NEXT: stxv vs5, 32(r3) +; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: blr entry: %a = load <16 x i16>, <16 x i16>* %0, align 32 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll @@ -80,9 +80,9 @@ define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mtvsrwz v2, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI1_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3 @@ -92,9 +92,9 @@ ; CHECK-P9-LABEL: test4elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2 @@ -103,9 +103,9 @@ ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2 @@ -119,32 +119,28 @@ define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI2_1@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC1@toc@ha +; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: mtvsrd v2, r4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l -; CHECK-P8-NEXT: addi r4, r6, .LCPI2_1@toc@l +; CHECK-P8-NEXT: ld r5, .LC1@toc@l(r5) ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: lvx v3, 0, r5 -; CHECK-P8-NEXT: lvx v5, 0, r4 -; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: lvx v3, r5, r6 +; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v5 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: stvx v3, 0, r3 -; CHECK-P8-NEXT: stvx v2, r3, r4 +; CHECK-P8-NEXT: stvx v2, r3, r6 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test8elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrd v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l +; CHECK-P9-NEXT: ld r4, .LC1@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4 @@ -157,12 +153,10 @@ ; CHECK-BE-LABEL: test8elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 @@ -181,55 +175,43 @@ define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_2@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha +; CHECK-P8-NEXT: li r5, 48 +; CHECK-P8-NEXT: li r6, 32 +; CHECK-P8-NEXT: li r7, 16 ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_2@toc@l +; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r4 -; CHECK-P8-NEXT: lvx v1, 0, r5 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: vperm v5, v4, v2, v5 +; CHECK-P8-NEXT: lvx v5, r4, r5 +; CHECK-P8-NEXT: lvx v0, r4, r6 +; CHECK-P8-NEXT: lvx v1, r4, r7 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3 +; CHECK-P8-NEXT: vperm v5, v4, v2, v5 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1 -; CHECK-P8-NEXT: xvcvuxwsp v4, v5 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3 +; CHECK-P8-NEXT: xvcvuxwsp v4, v5 ; CHECK-P8-NEXT: xvcvuxwsp v5, v0 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2 -; CHECK-P8-NEXT: stvx v4, r3, r5 -; CHECK-P8-NEXT: stvx v3, 0, r3 -; CHECK-P8-NEXT: stvx v5, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stvx v2, r3, r4 +; CHECK-P8-NEXT: stvx v3, r3, r5 +; CHECK-P8-NEXT: stvx v4, 0, r3 +; CHECK-P8-NEXT: stvx v5, r3, r6 +; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l +; CHECK-P9-NEXT: ld r4, .LC2@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 @@ -242,23 +224,17 @@ ; ; CHECK-BE-LABEL: test16elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3 @@ -345,9 +321,9 @@ define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-P8-NEXT: mtvsrwz v3, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI5_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vspltisw v3, 12 @@ -360,8 +336,8 @@ ; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-P9-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v2, v2 @@ -371,8 +347,8 @@ ; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l +; CHECK-BE-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-BE-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsb2w v2, v2 @@ -387,14 +363,12 @@ define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI6_1@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC4@toc@ha +; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: vspltisw v5, 12 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI6_1@toc@l +; CHECK-P8-NEXT: ld r5, .LC4@toc@l(r5) +; CHECK-P8-NEXT: lvx v2, r5, r6 ; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4 @@ -405,22 +379,20 @@ ; CHECK-P8-NEXT: vsraw v3, v3, v4 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3 -; CHECK-P8-NEXT: stvx v2, 0, r3 -; CHECK-P8-NEXT: stvx v3, r3, r4 +; CHECK-P8-NEXT: stvx v2, r3, r6 +; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrd v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC4@toc@ha +; CHECK-P9-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2w v2, v2 @@ -431,16 +403,14 @@ ; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha -; CHECK-BE-NEXT: xxlxor v3, v3, v3 -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l -; CHECK-BE-NEXT: vperm v3, v3, v2, v4 +; CHECK-BE-NEXT: addis r4, r2, .LC4@toc@ha +; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: ld r4, .LC4@toc@l(r4) +; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2w v2, v2 @@ -457,21 +427,16 @@ define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-P8-NEXT: li r5, 48 +; CHECK-P8-NEXT: li r6, 32 +; CHECK-P8-NEXT: li r7, 16 ; CHECK-P8-NEXT: vspltisw v1, 12 -; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l -; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha -; CHECK-P8-NEXT: lvx v4, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l +; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r4) +; CHECK-P8-NEXT: lvx v3, r4, r5 +; CHECK-P8-NEXT: lvx v4, r4, r6 ; CHECK-P8-NEXT: lvx v5, 0, r4 -; CHECK-P8-NEXT: lvx v0, 0, r5 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: li r5, 32 +; CHECK-P8-NEXT: lvx v0, r4, r7 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5 @@ -490,32 +455,25 @@ ; CHECK-P8-NEXT: xvcvsxwsp v5, v5 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: stvx v3, 0, r3 -; CHECK-P8-NEXT: stvx v4, r3, r5 -; CHECK-P8-NEXT: stvx v5, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stvx v2, r3, r4 +; CHECK-P8-NEXT: stvx v4, r3, r6 +; CHECK-P8-NEXT: stvx v5, r3, r5 +; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-P9-NEXT: ld r4, .LC5@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2w v3, v3 @@ -530,25 +488,19 @@ ; ; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC5@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC5@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2w v3, v3 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll @@ -12,9 +12,9 @@ define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 { ; CHECK-P8-LABEL: test2elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mtvsrwz v2, r3 -; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3 @@ -24,9 +24,9 @@ ; CHECK-P9-LABEL: test2elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp v2, v2 @@ -35,9 +35,9 @@ ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp v2, v2 @@ -51,34 +51,30 @@ define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC1@toc@ha ; CHECK-P8-NEXT: mtvsrwz v2, r4 -; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l -; CHECK-P8-NEXT: addi r4, r6, .LCPI1_1@toc@l +; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: ld r5, .LC1@toc@l(r5) ; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: lvx v3, 0, r5 -; CHECK-P8-NEXT: lvx v5, 0, r4 -; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: lvx v5, r5, r4 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v5 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs1, v2 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test4elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l +; CHECK-P9-NEXT: ld r4, .LC1@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4 @@ -91,12 +87,10 @@ ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 @@ -115,37 +109,31 @@ define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI2_2@toc@ha -; CHECK-P8-NEXT: mtvsrd v2, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l -; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: lvx v3, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI2_2@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l -; CHECK-P8-NEXT: lvx v1, 0, r5 -; CHECK-P8-NEXT: vperm v0, v4, v2, v0 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: vperm v3, v4, v2, v3 -; CHECK-P8-NEXT: vperm v5, v4, v2, v5 -; CHECK-P8-NEXT: vperm v2, v4, v2, v1 -; CHECK-P8-NEXT: xvcvuxddp vs2, v0 +; CHECK-P8-NEXT: addis r5, r2, .LC2@toc@ha +; CHECK-P8-NEXT: li r6, 32 +; CHECK-P8-NEXT: li r7, 48 +; CHECK-P8-NEXT: mtvsrd v4, r4 +; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: ld r5, .LC2@toc@l(r5) +; CHECK-P8-NEXT: xxlxor v2, v2, v2 +; CHECK-P8-NEXT: lvx v3, r5, r6 +; CHECK-P8-NEXT: lvx v5, r5, r7 +; CHECK-P8-NEXT: lvx v0, 0, r5 +; CHECK-P8-NEXT: lvx v1, r5, r4 +; CHECK-P8-NEXT: vperm v3, v2, v4, v3 +; CHECK-P8-NEXT: vperm v5, v2, v4, v5 +; CHECK-P8-NEXT: vperm v0, v2, v4, v0 +; CHECK-P8-NEXT: vperm v2, v2, v4, v1 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5 +; CHECK-P8-NEXT: xvcvuxddp vs2, v0 ; CHECK-P8-NEXT: xvcvuxddp vs3, v2 -; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 +; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr @@ -153,23 +141,17 @@ ; CHECK-P9-LABEL: test8elt: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrd v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-P9-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l +; CHECK-P9-NEXT: ld r4, .LC2@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 @@ -183,23 +165,17 @@ ; CHECK-BE-LABEL: test8elt: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 @@ -219,120 +195,92 @@ define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC3@toc@ha +; CHECK-P8-NEXT: li r5, 112 +; CHECK-P8-NEXT: li r6, 48 +; CHECK-P8-NEXT: li r7, 32 +; CHECK-P8-NEXT: li r8, 16 +; CHECK-P8-NEXT: li r9, 80 +; CHECK-P8-NEXT: li r10, 96 +; CHECK-P8-NEXT: ld r4, .LC3@toc@l(r4) +; CHECK-P8-NEXT: li r11, 64 ; CHECK-P8-NEXT: xxlxor v4, v4, v4 -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_4@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_4@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_6@toc@ha -; CHECK-P8-NEXT: lvx v1, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_7@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_6@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_7@toc@l +; CHECK-P8-NEXT: lvx v5, r4, r5 +; CHECK-P8-NEXT: lvx v0, r4, r6 +; CHECK-P8-NEXT: lvx v1, r4, r7 +; CHECK-P8-NEXT: lvx v6, r4, r8 +; CHECK-P8-NEXT: lvx v7, r4, r9 +; CHECK-P8-NEXT: lvx v8, r4, r10 +; CHECK-P8-NEXT: lvx v9, r4, r11 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3 -; CHECK-P8-NEXT: lvx v6, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI3_5@toc@ha -; CHECK-P8-NEXT: lvx v7, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3@toc@ha ; CHECK-P8-NEXT: vperm v5, v4, v2, v5 -; CHECK-P8-NEXT: addi r4, r4, .LCPI3_5@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3@toc@l ; CHECK-P8-NEXT: vperm v0, v4, v2, v0 -; CHECK-P8-NEXT: lvx v8, 0, r4 -; CHECK-P8-NEXT: lvx v9, 0, r5 ; CHECK-P8-NEXT: vperm v1, v4, v2, v1 -; CHECK-P8-NEXT: li r4, 112 -; CHECK-P8-NEXT: li r5, 96 ; CHECK-P8-NEXT: vperm v6, v4, v2, v6 ; CHECK-P8-NEXT: vperm v7, v4, v2, v7 ; CHECK-P8-NEXT: vperm v8, v4, v2, v8 ; CHECK-P8-NEXT: vperm v2, v4, v2, v9 -; CHECK-P8-NEXT: xvcvuxddp vs0, v0 -; CHECK-P8-NEXT: xvcvuxddp vs1, v1 -; CHECK-P8-NEXT: xvcvuxddp vs2, v6 +; CHECK-P8-NEXT: xvcvuxddp vs0, v3 +; CHECK-P8-NEXT: xvcvuxddp vs1, v5 +; CHECK-P8-NEXT: xvcvuxddp vs2, v1 ; CHECK-P8-NEXT: xvcvuxddp vs3, v7 ; CHECK-P8-NEXT: xvcvuxddp vs4, v8 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2 -; CHECK-P8-NEXT: xvcvuxddp vs6, v3 +; CHECK-P8-NEXT: xvcvuxddp vs6, v6 ; CHECK-P8-NEXT: xxswapd vs0, vs0 -; CHECK-P8-NEXT: xvcvuxddp vs7, v5 +; CHECK-P8-NEXT: xvcvuxddp vs7, v0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 +; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: xxswapd vs5, vs5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 -; CHECK-P8-NEXT: li r4, 80 -; CHECK-P8-NEXT: li r5, 64 -; CHECK-P8-NEXT: xxswapd vs2, vs7 -; CHECK-P8-NEXT: xxswapd vs3, vs6 -; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 +; CHECK-P8-NEXT: xxswapd vs6, vs6 +; CHECK-P8-NEXT: xxswapd vs7, vs7 +; CHECK-P8-NEXT: stxvd2x vs4, r3, r10 +; CHECK-P8-NEXT: stxvd2x vs5, r3, r9 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r11 +; CHECK-P8-NEXT: stxvd2x vs6, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs7, r3, r8 +; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 -; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 +; CHECK-P9-NEXT: addis r4, r2, .LC3@toc@ha +; CHECK-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-P9-NEXT: ld r4, .LC3@toc@l(r4) +; CHECK-P9-NEXT: lxv v4, 112(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 +; CHECK-P9-NEXT: xvcvuxddp vs0, v4 +; CHECK-P9-NEXT: lxv v4, 48(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs0, 0(r3) -; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 +; CHECK-P9-NEXT: xvcvuxddp vs1, v4 +; CHECK-P9-NEXT: lxv v4, 32(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs1, 16(r3) -; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 +; CHECK-P9-NEXT: xvcvuxddp vs2, v4 +; CHECK-P9-NEXT: lxv v4, 16(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs2, 32(r3) -; CHECK-P9-NEXT: xvcvuxddp vs3, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 +; CHECK-P9-NEXT: xvcvuxddp vs3, v4 +; CHECK-P9-NEXT: lxv v4, 80(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs3, 48(r3) -; CHECK-P9-NEXT: xvcvuxddp vs4, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 +; CHECK-P9-NEXT: xvcvuxddp vs4, v4 +; CHECK-P9-NEXT: lxv v4, 64(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs4, 64(r3) -; CHECK-P9-NEXT: xvcvuxddp vs5, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l -; CHECK-P9-NEXT: vperm v3, v4, v2, v3 +; CHECK-P9-NEXT: xvcvuxddp vs5, v4 +; CHECK-P9-NEXT: lxv v4, 96(r4) +; CHECK-P9-NEXT: vperm v4, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs5, 80(r3) -; CHECK-P9-NEXT: xvcvuxddp vs6, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: vperm v2, v4, v2, v3 +; CHECK-P9-NEXT: xvcvuxddp vs6, v4 +; CHECK-P9-NEXT: lxvx v4, 0, r4 +; CHECK-P9-NEXT: vperm v2, v3, v2, v4 ; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: xvcvuxddp vs7, v2 ; CHECK-P9-NEXT: stxv vs7, 112(r3) @@ -340,52 +288,38 @@ ; ; CHECK-BE-LABEL: test16elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha -; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l -; CHECK-BE-NEXT: vperm v3, v2, v4, v3 -; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l -; CHECK-BE-NEXT: vperm v3, v4, v2, v3 +; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha +; CHECK-BE-NEXT: xxlxor v3, v3, v3 +; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) +; CHECK-BE-NEXT: lxv v4, 112(r4) +; CHECK-BE-NEXT: vperm v4, v2, v3, v4 +; CHECK-BE-NEXT: xvcvuxddp vs0, v4 +; CHECK-BE-NEXT: lxv v4, 48(r4) +; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs0, 0(r3) -; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l -; CHECK-BE-NEXT: vperm v3, v4, v2, v3 +; CHECK-BE-NEXT: xvcvuxddp vs1, v4 +; CHECK-BE-NEXT: lxv v4, 32(r4) +; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs1, 16(r3) -; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l -; CHECK-BE-NEXT: vperm v3, v4, v2, v3 +; CHECK-BE-NEXT: xvcvuxddp vs2, v4 +; CHECK-BE-NEXT: lxv v4, 16(r4) +; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs2, 32(r3) -; CHECK-BE-NEXT: xvcvuxddp vs3, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l -; CHECK-BE-NEXT: vperm v3, v4, v2, v3 +; CHECK-BE-NEXT: xvcvuxddp vs3, v4 +; CHECK-BE-NEXT: lxv v4, 80(r4) +; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs3, 48(r3) -; CHECK-BE-NEXT: xvcvuxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l -; CHECK-BE-NEXT: vperm v3, v4, v2, v3 +; CHECK-BE-NEXT: xvcvuxddp vs4, v4 +; CHECK-BE-NEXT: lxv v4, 64(r4) +; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs4, 64(r3) -; CHECK-BE-NEXT: xvcvuxddp vs5, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l -; CHECK-BE-NEXT: vperm v3, v4, v2, v3 +; CHECK-BE-NEXT: xvcvuxddp vs5, v4 +; CHECK-BE-NEXT: lxv v4, 96(r4) +; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs5, 80(r3) -; CHECK-BE-NEXT: xvcvuxddp vs6, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 +; CHECK-BE-NEXT: xvcvuxddp vs6, v4 +; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: vperm v2, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: xvcvuxddp vs7, v2 ; CHECK-BE-NEXT: stxv vs7, 112(r3) @@ -399,14 +333,14 @@ define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { ; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC5@toc@ha ; CHECK-P8-NEXT: mtvsrwz v3, r3 -; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l +; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P8-NEXT: lvx v2, 0, r4 -; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r5) ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3 @@ -416,8 +350,8 @@ ; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r3 -; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-P9-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-P9-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -427,8 +361,8 @@ ; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r3 -; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-BE-NEXT: addis r3, r2, .LC4@toc@ha +; CHECK-BE-NEXT: ld r3, .LC4@toc@l(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -443,17 +377,15 @@ define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC6@toc@ha +; CHECK-P8-NEXT: addis r6, r2, .LC7@toc@ha +; CHECK-P8-NEXT: li r7, 16 ; CHECK-P8-NEXT: mtvsrwz v3, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l +; CHECK-P8-NEXT: ld r5, .LC6@toc@l(r5) +; CHECK-P8-NEXT: ld r6, .LC7@toc@l(r6) ; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: lvx v4, 0, r5 +; CHECK-P8-NEXT: lvx v4, r5, r7 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r6 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: xxswapd v4, vs0 @@ -465,22 +397,20 @@ ; CHECK-P8-NEXT: xvcvsxddp vs1, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrws v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-P9-NEXT: ld r4, .LC5@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -491,16 +421,14 @@ ; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrws v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha -; CHECK-BE-NEXT: xxlxor v3, v3, v3 -; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l -; CHECK-BE-NEXT: vperm v3, v3, v2, v4 +; CHECK-BE-NEXT: addis r4, r2, .LC5@toc@ha +; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: ld r4, .LC5@toc@l(r4) +; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -517,25 +445,20 @@ define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI6_2@toc@ha +; CHECK-P8-NEXT: addis r5, r2, .LC8@toc@ha +; CHECK-P8-NEXT: li r6, 32 +; CHECK-P8-NEXT: addis r7, r2, .LC9@toc@ha +; CHECK-P8-NEXT: li r8, 48 ; CHECK-P8-NEXT: mtvsrd v3, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI6_2@toc@l -; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l -; CHECK-P8-NEXT: lvx v2, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI6_3@toc@ha -; CHECK-P8-NEXT: lvx v4, 0, r6 -; CHECK-P8-NEXT: addis r6, r2, .LCPI6_4@toc@ha -; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: addi r5, r5, .LCPI6_3@toc@l -; CHECK-P8-NEXT: lvx v5, 0, r5 -; CHECK-P8-NEXT: addi r5, r6, .LCPI6_4@toc@l +; CHECK-P8-NEXT: li r4, 16 +; CHECK-P8-NEXT: ld r5, .LC8@toc@l(r5) +; CHECK-P8-NEXT: ld r7, .LC9@toc@l(r7) +; CHECK-P8-NEXT: lvx v2, r5, r6 +; CHECK-P8-NEXT: lvx v4, r5, r8 +; CHECK-P8-NEXT: lvx v5, r5, r4 ; CHECK-P8-NEXT: lvx v0, 0, r5 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r7 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2 -; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: vperm v4, v3, v3, v4 ; CHECK-P8-NEXT: vperm v5, v3, v3, v5 ; CHECK-P8-NEXT: vperm v3, v3, v3, v0 @@ -545,50 +468,43 @@ ; CHECK-P8-NEXT: vsld v5, v5, v0 ; CHECK-P8-NEXT: vsld v3, v3, v0 ; CHECK-P8-NEXT: vsrad v2, v2, v0 -; CHECK-P8-NEXT: vsrad v3, v3, v0 ; CHECK-P8-NEXT: vsrad v4, v4, v0 ; CHECK-P8-NEXT: vsrad v5, v5, v0 -; CHECK-P8-NEXT: xvcvsxddp vs2, v3 +; CHECK-P8-NEXT: vsrad v3, v3, v0 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2 -; CHECK-P8-NEXT: xvcvsxddp vs1, v5 -; CHECK-P8-NEXT: xvcvsxddp vs3, v4 -; CHECK-P8-NEXT: xxswapd vs2, vs2 +; CHECK-P8-NEXT: xvcvsxddp vs1, v4 +; CHECK-P8-NEXT: xvcvsxddp vs2, v5 +; CHECK-P8-NEXT: xvcvsxddp vs3, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs1, vs1 +; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r8 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 +; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: mtvsrd v2, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC6@toc@ha +; CHECK-P9-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -599,30 +515,24 @@ ; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrd v2, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC6@toc@l(r4) +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -639,139 +549,111 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha -; CHECK-P8-NEXT: addis r6, r2, .LCPI7_3@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI7_3@toc@l -; CHECK-P8-NEXT: lvx v3, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI7_4@toc@ha -; CHECK-P8-NEXT: lvx v4, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_5@toc@ha -; CHECK-P8-NEXT: lvx v5, 0, r6 -; CHECK-P8-NEXT: addis r6, r2, .LCPI7_1@toc@ha -; CHECK-P8-NEXT: addi r4, r4, .LCPI7_4@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_5@toc@l -; CHECK-P8-NEXT: addi r6, r6, .LCPI7_1@toc@l -; CHECK-P8-NEXT: lvx v0, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI7_6@toc@ha -; CHECK-P8-NEXT: lvx v1, 0, r5 -; CHECK-P8-NEXT: addis r5, r2, .LCPI7_7@toc@ha -; CHECK-P8-NEXT: lxvd2x vs0, 0, r6 -; CHECK-P8-NEXT: addi r4, r4, .LCPI7_6@toc@l -; CHECK-P8-NEXT: addi r5, r5, .LCPI7_7@toc@l +; CHECK-P8-NEXT: addis r7, r2, .LC10@toc@ha +; CHECK-P8-NEXT: addis r4, r2, .LC11@toc@ha +; CHECK-P8-NEXT: li r5, 112 +; CHECK-P8-NEXT: li r6, 48 +; CHECK-P8-NEXT: li r8, 32 +; CHECK-P8-NEXT: li r9, 16 +; CHECK-P8-NEXT: li r10, 80 +; CHECK-P8-NEXT: li r11, 64 +; CHECK-P8-NEXT: ld r7, .LC10@toc@l(r7) +; CHECK-P8-NEXT: ld r4, .LC11@toc@l(r4) +; CHECK-P8-NEXT: lxvd2x vs0, 0, r7 +; CHECK-P8-NEXT: li r7, 96 +; CHECK-P8-NEXT: lvx v3, r4, r5 +; CHECK-P8-NEXT: lvx v4, r4, r6 +; CHECK-P8-NEXT: lvx v5, r4, r8 +; CHECK-P8-NEXT: lvx v0, r4, r9 +; CHECK-P8-NEXT: lvx v1, r4, r10 +; CHECK-P8-NEXT: lvx v6, r4, r11 +; CHECK-P8-NEXT: lvx v7, r4, r7 +; CHECK-P8-NEXT: lvx v8, 0, r4 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3 -; CHECK-P8-NEXT: lvx v6, 0, r4 -; CHECK-P8-NEXT: addis r4, r2, .LCPI7_8@toc@ha -; CHECK-P8-NEXT: lvx v7, 0, r5 +; CHECK-P8-NEXT: xxswapd v9, vs0 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4 -; CHECK-P8-NEXT: li r5, 96 -; CHECK-P8-NEXT: addi r4, r4, .LCPI7_8@toc@l ; CHECK-P8-NEXT: vperm v5, v2, v2, v5 -; CHECK-P8-NEXT: xxswapd v9, vs0 -; CHECK-P8-NEXT: lvx v8, 0, r4 ; CHECK-P8-NEXT: vperm v0, v2, v2, v0 -; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: vperm v1, v2, v2, v1 ; CHECK-P8-NEXT: vperm v6, v2, v2, v6 ; CHECK-P8-NEXT: vperm v7, v2, v2, v7 ; CHECK-P8-NEXT: vperm v2, v2, v2, v8 ; CHECK-P8-NEXT: vsld v3, v3, v9 +; CHECK-P8-NEXT: vsld v4, v4, v9 +; CHECK-P8-NEXT: vsld v5, v5, v9 ; CHECK-P8-NEXT: vsld v0, v0, v9 ; CHECK-P8-NEXT: vsld v1, v1, v9 ; CHECK-P8-NEXT: vsld v6, v6, v9 ; CHECK-P8-NEXT: vsld v7, v7, v9 ; CHECK-P8-NEXT: vsld v2, v2, v9 -; CHECK-P8-NEXT: vsrad v7, v7, v9 -; CHECK-P8-NEXT: vsrad v2, v2, v9 -; CHECK-P8-NEXT: vsld v4, v4, v9 -; CHECK-P8-NEXT: vsld v5, v5, v9 -; CHECK-P8-NEXT: vsrad v6, v6, v9 -; CHECK-P8-NEXT: vsrad v0, v0, v9 -; CHECK-P8-NEXT: vsrad v1, v1, v9 -; CHECK-P8-NEXT: xvcvsxddp vs2, v7 -; CHECK-P8-NEXT: xvcvsxddp vs3, v2 ; CHECK-P8-NEXT: vsrad v3, v3, v9 ; CHECK-P8-NEXT: vsrad v4, v4, v9 ; CHECK-P8-NEXT: vsrad v5, v5, v9 -; CHECK-P8-NEXT: xvcvsxddp vs4, v6 -; CHECK-P8-NEXT: xvcvsxddp vs1, v1 +; CHECK-P8-NEXT: vsrad v0, v0, v9 +; CHECK-P8-NEXT: vsrad v1, v1, v9 +; CHECK-P8-NEXT: vsrad v6, v6, v9 +; CHECK-P8-NEXT: vsrad v7, v7, v9 +; CHECK-P8-NEXT: vsrad v2, v2, v9 +; CHECK-P8-NEXT: xvcvsxddp vs0, v3 +; CHECK-P8-NEXT: xvcvsxddp vs1, v5 +; CHECK-P8-NEXT: xvcvsxddp vs2, v1 +; CHECK-P8-NEXT: xvcvsxddp vs3, v7 +; CHECK-P8-NEXT: xvcvsxddp vs4, v2 +; CHECK-P8-NEXT: xvcvsxddp vs5, v6 +; CHECK-P8-NEXT: xvcvsxddp vs6, v0 +; CHECK-P8-NEXT: xxswapd vs0, vs0 +; CHECK-P8-NEXT: xvcvsxddp vs7, v4 +; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs2, vs2 -; CHECK-P8-NEXT: xvcvsxddp vs5, v0 ; CHECK-P8-NEXT: xxswapd vs3, vs3 -; CHECK-P8-NEXT: xvcvsxddp vs0, v5 -; CHECK-P8-NEXT: xvcvsxddp vs6, v3 -; CHECK-P8-NEXT: xvcvsxddp vs7, v4 -; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 -; CHECK-P8-NEXT: li r4, 80 ; CHECK-P8-NEXT: xxswapd vs4, vs4 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 -; CHECK-P8-NEXT: li r5, 64 -; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs5, vs5 -; CHECK-P8-NEXT: xxswapd vs0, vs0 -; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 -; CHECK-P8-NEXT: li r4, 48 -; CHECK-P8-NEXT: xxswapd vs3, vs6 -; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 -; CHECK-P8-NEXT: li r5, 32 -; CHECK-P8-NEXT: xxswapd vs2, vs7 -; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 -; CHECK-P8-NEXT: li r4, 16 -; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 -; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 -; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 +; CHECK-P8-NEXT: xxswapd vs6, vs6 +; CHECK-P8-NEXT: xxswapd vs7, vs7 +; CHECK-P8-NEXT: stxvd2x vs4, r3, r5 +; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 +; CHECK-P8-NEXT: stxvd2x vs5, r3, r10 +; CHECK-P8-NEXT: stxvd2x vs2, r3, r11 +; CHECK-P8-NEXT: stxvd2x vs6, r3, r6 +; CHECK-P8-NEXT: stxvd2x vs1, r3, r8 +; CHECK-P8-NEXT: stxvd2x vs7, r3, r9 +; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l +; CHECK-P9-NEXT: addis r4, r2, .LC7@toc@ha +; CHECK-P9-NEXT: ld r4, .LC7@toc@l(r4) +; CHECK-P9-NEXT: lxv v3, 112(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l +; CHECK-P9-NEXT: lxv v3, 48(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l +; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l +; CHECK-P9-NEXT: lxv v3, 16(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs3, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l +; CHECK-P9-NEXT: lxv v3, 80(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l +; CHECK-P9-NEXT: lxv v3, 64(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 -; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha -; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l +; CHECK-P9-NEXT: lxv v3, 96(r4) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 @@ -786,58 +668,44 @@ ; ; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha +; CHECK-BE-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l +; CHECK-BE-NEXT: ld r4, .LC7@toc@l(r4) +; CHECK-BE-NEXT: lxv v4, 96(r4) ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l +; CHECK-BE-NEXT: lxv v4, 80(r4) ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l +; CHECK-BE-NEXT: lxv v4, 112(r4) ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs2, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l +; CHECK-BE-NEXT: lxv v4, 64(r4) ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l +; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 -; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha -; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l +; CHECK-BE-NEXT: lxv v3, 16(r4) ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll --- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll @@ -5,19 +5,19 @@ define <1 x float> @constrained_vector_fdiv_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fdiv_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI0_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI0_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI0_1@toc@l(4) -; PC64LE-NEXT: xsdivsp 1, 1, 0 +; PC64LE-NEXT: addis 3, 2, .LC0@toc@ha +; PC64LE-NEXT: ld 3, .LC0@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 +; PC64LE-NEXT: xsdivsp 1, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fdiv_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI0_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI0_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI0_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC0@toc@ha +; PC64LE9-NEXT: ld 3, .LC0@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 4(3) ; PC64LE9-NEXT: xsdivsp 1, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -32,25 +32,22 @@ define <2 x double> @constrained_vector_fdiv_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fdiv_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI1_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI1_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI1_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC1@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC1@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvdivdp 34, 1, 0 +; PC64LE-NEXT: xvdivdp 34, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fdiv_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI1_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC1@toc@ha +; PC64LE9-NEXT: ld 3, .LC1@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI1_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI1_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -65,24 +62,22 @@ define <3 x float> @constrained_vector_fdiv_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fdiv_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI2_3@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI2_2@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI2_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI2_3@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI2_2@toc@l(5) -; PC64LE-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PC64LE-NEXT: xsdivsp 1, 1, 0 -; PC64LE-NEXT: lfs 3, .LCPI2_1@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI2_4@toc@ha -; PC64LE-NEXT: xsdivsp 2, 2, 0 -; PC64LE-NEXT: addi 3, 3, .LCPI2_4@toc@l +; PC64LE-NEXT: addis 3, 2, .LC2@toc@ha +; PC64LE-NEXT: ld 3, .LC2@toc@l(3) +; PC64LE-NEXT: lfs 0, 12(3) +; PC64LE-NEXT: lfsx 1, 0, 3 +; PC64LE-NEXT: lfs 2, 8(3) +; PC64LE-NEXT: lfs 3, 4(3) +; PC64LE-NEXT: addis 3, 2, .LC3@toc@ha +; PC64LE-NEXT: xsdivsp 0, 0, 1 +; PC64LE-NEXT: ld 3, .LC3@toc@l(3) +; PC64LE-NEXT: xsdivsp 2, 2, 1 +; PC64LE-NEXT: xsdivsp 1, 3, 1 ; PC64LE-NEXT: lvx 4, 0, 3 -; PC64LE-NEXT: xsdivsp 0, 3, 0 -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 -; PC64LE-NEXT: xxsldwi 34, 1, 1, 3 +; PC64LE-NEXT: xscvdpspn 2, 2 +; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 ; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 @@ -91,20 +86,18 @@ ; ; PC64LE9-LABEL: constrained_vector_fdiv_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI2_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI2_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI2_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC2@toc@ha +; PC64LE9-NEXT: ld 3, .LC2@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 8(3) +; PC64LE9-NEXT: lfs 3, 12(3) +; PC64LE9-NEXT: addis 3, 2, .LC3@toc@ha +; PC64LE9-NEXT: ld 3, .LC3@toc@l(3) ; PC64LE9-NEXT: xsdivsp 1, 1, 0 -; PC64LE9-NEXT: lfs 2, .LCPI2_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI2_3@toc@ha -; PC64LE9-NEXT: lfs 3, .LCPI2_3@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI2_4@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI2_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xsdivsp 2, 2, 0 ; PC64LE9-NEXT: xsdivsp 0, 3, 0 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 2 @@ -126,20 +119,19 @@ define <3 x double> @constrained_vector_fdiv_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fdiv_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI3_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI3_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI3_2@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI3_3@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI3_1@toc@ha -; PC64LE-NEXT: lfs 3, .LCPI3_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC4@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC4@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC5@toc@ha +; PC64LE-NEXT: ld 3, .LC5@toc@l(3) ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvdivdp 2, 1, 0 -; PC64LE-NEXT: lfs 0, .LCPI3_1@toc@l(4) -; PC64LE-NEXT: xsdivdp 3, 0, 3 +; PC64LE-NEXT: xvdivdp 2, 0, 1 +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 +; PC64LE-NEXT: xsdivdp 3, 0, 1 ; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -147,17 +139,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fdiv_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI3_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI3_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI3_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI3_2@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC4@toc@ha +; PC64LE9-NEXT: ld 3, .LC4@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: addis 3, 2, .LC5@toc@ha +; PC64LE9-NEXT: ld 3, .LC5@toc@l(3) ; PC64LE9-NEXT: xsdivdp 3, 1, 0 ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI3_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI3_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvdivdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -175,34 +165,28 @@ define <4 x double> @constrained_vector_fdiv_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fdiv_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI4_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI4_2@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI4_1@toc@l -; PC64LE-NEXT: addi 4, 5, .LCPI4_2@toc@l +; PC64LE-NEXT: addis 3, 2, .LC6@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC6@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: li 4, 32 ; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: lxvd2x 2, 0, 4 +; PC64LE-NEXT: lxvd2x 2, 3, 4 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 2, 2 -; PC64LE-NEXT: xvdivdp 35, 1, 0 -; PC64LE-NEXT: xvdivdp 34, 2, 0 +; PC64LE-NEXT: xvdivdp 35, 0, 1 +; PC64LE-NEXT: xvdivdp 34, 2, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fdiv_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI4_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC6@toc@ha +; PC64LE9-NEXT: ld 3, .LC6@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI4_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI4_2@toc@l +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvdivdp 35, 1, 0 -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 32(3) ; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -222,10 +206,10 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI5_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI5_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI5_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC7@toc@ha +; PC64LE-NEXT: ld 3, .LC7@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -238,10 +222,10 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI5_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI5_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC7@toc@ha +; PC64LE9-NEXT: ld 3, .LC7@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 0(3) ; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -261,60 +245,62 @@ ; PC64LE-LABEL: constrained_vector_frem_v2f64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -24(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) -; PC64LE-NEXT: addis 4, 2, .LCPI6_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI6_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI6_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -96(1) +; PC64LE-NEXT: addis 3, 2, .LC8@toc@ha +; PC64LE-NEXT: ld 30, .LC8@toc@l(3) +; PC64LE-NEXT: lfsx 31, 0, 30 +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI6_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI6_2@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_frem_v2f64: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI6_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI6_1@toc@l(3) +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC8@toc@ha +; PC64LE9-NEXT: ld 30, .LC8@toc@l(3) +; PC64LE9-NEXT: lfs 31, 0(30) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI6_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI6_2@toc@l(3) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -330,34 +316,33 @@ ; PC64LE-LABEL: constrained_vector_frem_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 4, 2, .LCPI7_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI7_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI7_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: addis 3, 2, .LC9@toc@ha +; PC64LE-NEXT: ld 30, .LC9@toc@l(3) +; PC64LE-NEXT: lfsx 31, 0, 30 +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI7_2@toc@ha ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI7_2@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI7_3@toc@ha ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 29, 1 -; PC64LE-NEXT: lfs 1, .LCPI7_3@toc@l(3) +; PC64LE-NEXT: lfs 1, 12(30) ; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 29 -; PC64LE-NEXT: addis 3, 2, .LCPI7_4@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC10@toc@ha ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI7_4@toc@l +; PC64LE-NEXT: ld 3, .LC10@toc@l(3) ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xscvdpspn 0, 30 @@ -365,10 +350,11 @@ ; PC64LE-NEXT: vmrghw 2, 2, 3 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 3, 2, 4 -; PC64LE-NEXT: addi 1, 1, 64 +; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -376,45 +362,45 @@ ; PC64LE9-LABEL: constrained_vector_frem_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI7_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI7_1@toc@l(3) +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC9@toc@ha +; PC64LE9-NEXT: ld 30, .LC9@toc@l(3) +; PC64LE9-NEXT: lfs 31, 0(30) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI7_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI7_2@toc@l(3) ; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI7_3@toc@ha ; PC64LE9-NEXT: fmr 29, 1 +; PC64LE9-NEXT: lfs 1, 12(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI7_3@toc@l(3) ; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: addis 3, 2, .LC10@toc@ha +; PC64LE9-NEXT: ld 3, .LC10@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 3, 2, 4 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr @@ -432,42 +418,42 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -96(1) -; PC64LE-NEXT: addis 4, 2, .LCPI8_1@toc@ha -; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stdu 1, -112(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stfd 31, 104(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI8_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI8_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC11@toc@ha +; PC64LE-NEXT: ld 30, .LC11@toc@l(3) +; PC64LE-NEXT: lfsx 31, 0, 30 +; PC64LE-NEXT: lfs 1, 12(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI8_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI8_2@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI8_3@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfs 1, .LCPI8_3@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 -; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload +; PC64LE-NEXT: lfd 31, 104(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 96 +; PC64LE-NEXT: addi 1, 1, 112 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -476,38 +462,38 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -80(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stdu 1, -96(1) +; PC64LE9-NEXT: addis 3, 2, .LC11@toc@ha +; PC64LE9-NEXT: std 30, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE9-NEXT: ld 30, .LC11@toc@l(3) ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI8_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI8_1@toc@l(3) +; PC64LE9-NEXT: lfs 31, 0(30) ; PC64LE9-NEXT: fmr 2, 31 +; PC64LE9-NEXT: lfs 1, 12(30) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI8_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI8_2@toc@l(3) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI8_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfs 1, .LCPI8_3@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 80 +; PC64LE9-NEXT: ld 30, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: addi 1, 1, 96 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -525,51 +511,50 @@ ; PC64LE: # %bb.0: ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -96(1) -; PC64LE-NEXT: addis 4, 2, .LCPI9_1@toc@ha -; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stdu 1, -112(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stfd 31, 104(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI9_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI9_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC12@toc@ha +; PC64LE-NEXT: ld 30, .LC12@toc@l(3) +; PC64LE-NEXT: lfsx 31, 0, 30 +; PC64LE-NEXT: lfs 1, 16(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI9_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI9_2@toc@l(3) +; PC64LE-NEXT: lfs 1, 12(30) ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI9_3@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfs 1, .LCPI9_3@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI9_4@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI9_4@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 2, 31 -; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload +; PC64LE-NEXT: lfd 31, 104(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 35, 1, 0 -; PC64LE-NEXT: addi 1, 1, 96 +; PC64LE-NEXT: addi 1, 1, 112 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -578,45 +563,44 @@ ; PC64LE9: # %bb.0: ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -80(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stdu 1, -96(1) +; PC64LE9-NEXT: addis 3, 2, .LC12@toc@ha +; PC64LE9-NEXT: std 30, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE9-NEXT: ld 30, .LC12@toc@l(3) ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI9_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI9_1@toc@l(3) +; PC64LE9-NEXT: lfs 31, 0(30) ; PC64LE9-NEXT: fmr 2, 31 +; PC64LE9-NEXT: lfs 1, 16(30) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI9_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfs 1, 12(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI9_2@toc@l(3) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI9_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfs 1, .LCPI9_3@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI9_4@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI9_4@toc@l(3) ; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE9-NEXT: ld 30, 72(1) # 8-byte Folded Reload ; PC64LE9-NEXT: xxmrghd 35, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 80 +; PC64LE9-NEXT: addi 1, 1, 96 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -633,19 +617,19 @@ define <1 x float> @constrained_vector_fmul_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fmul_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI10_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI10_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI10_1@toc@l(4) -; PC64LE-NEXT: xsmulsp 1, 1, 0 +; PC64LE-NEXT: addis 3, 2, .LC13@toc@ha +; PC64LE-NEXT: ld 3, .LC13@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 +; PC64LE-NEXT: xsmulsp 1, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fmul_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI10_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI10_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC13@toc@ha +; PC64LE9-NEXT: ld 3, .LC13@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 4(3) ; PC64LE9-NEXT: xsmulsp 1, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -660,25 +644,22 @@ define <2 x double> @constrained_vector_fmul_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fmul_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI11_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI11_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC14@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC14@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvmuldp 34, 1, 0 +; PC64LE-NEXT: xvmuldp 34, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fmul_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI11_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC14@toc@ha +; PC64LE9-NEXT: ld 3, .LC14@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -693,20 +674,18 @@ define <3 x float> @constrained_vector_fmul_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fmul_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI12_3@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI12_2@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI12_1@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI12_3@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI12_2@toc@l(5) -; PC64LE-NEXT: addis 3, 2, .LCPI12_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC15@toc@ha +; PC64LE-NEXT: ld 3, .LC15@toc@l(3) +; PC64LE-NEXT: lfs 0, 12(3) +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfs 2, 4(3) +; PC64LE-NEXT: lfsx 3, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC16@toc@ha +; PC64LE-NEXT: ld 3, .LC16@toc@l(3) ; PC64LE-NEXT: xsmulsp 1, 0, 1 -; PC64LE-NEXT: lfs 3, .LCPI12_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI12_4@toc@ha ; PC64LE-NEXT: xsmulsp 2, 0, 2 -; PC64LE-NEXT: addi 3, 3, .LCPI12_4@toc@l -; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xsmulsp 0, 0, 3 +; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 @@ -719,22 +698,20 @@ ; ; PC64LE9-LABEL: constrained_vector_fmul_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI12_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI12_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI12_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC15@toc@ha +; PC64LE9-NEXT: ld 3, .LC15@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 12(3) +; PC64LE9-NEXT: lfs 2, 4(3) +; PC64LE9-NEXT: lfs 3, 8(3) +; PC64LE9-NEXT: addis 3, 2, .LC16@toc@ha +; PC64LE9-NEXT: ld 3, .LC16@toc@l(3) ; PC64LE9-NEXT: xsmulsp 0, 1, 0 -; PC64LE9-NEXT: lfs 2, .LCPI12_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI12_3@toc@ha -; PC64LE9-NEXT: lfs 3, .LCPI12_3@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI12_4@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI12_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xsmulsp 2, 1, 2 ; PC64LE9-NEXT: xsmulsp 1, 1, 3 -; PC64LE9-NEXT: xscvdpspn 0, 0 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 1, 1, 3 ; PC64LE9-NEXT: xscvdpspn 1, 2 ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 @@ -755,20 +732,21 @@ define <3 x double> @constrained_vector_fmul_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fmul_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI13_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI13_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI13_2@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI13_3@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addis 3, 2, .LCPI13_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI13_1@toc@ha -; PC64LE-NEXT: lfd 3, .LCPI13_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC17@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC17@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC18@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC19@toc@ha +; PC64LE-NEXT: ld 3, .LC18@toc@l(3) +; PC64LE-NEXT: ld 4, .LC19@toc@l(4) ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvmuldp 2, 1, 0 -; PC64LE-NEXT: lfs 0, .LCPI13_1@toc@l(4) -; PC64LE-NEXT: xsmuldp 3, 3, 0 +; PC64LE-NEXT: xvmuldp 2, 0, 1 +; PC64LE-NEXT: lfdx 0, 0, 3 +; PC64LE-NEXT: lfsx 1, 0, 4 +; PC64LE-NEXT: xsmuldp 3, 0, 1 ; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -776,17 +754,17 @@ ; ; PC64LE9-LABEL: constrained_vector_fmul_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI13_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI13_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI13_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI13_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI13_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI13_2@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC17@toc@ha +; PC64LE9-NEXT: ld 3, .LC17@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC18@toc@ha +; PC64LE9-NEXT: ld 3, .LC18@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC19@toc@ha +; PC64LE9-NEXT: ld 3, .LC19@toc@l(3) ; PC64LE9-NEXT: xsmuldp 3, 0, 1 ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI13_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI13_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvmuldp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -805,34 +783,28 @@ define <4 x double> @constrained_vector_fmul_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fmul_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI14_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI14_2@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI14_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 5, .LCPI14_2@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC20@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: li 5, 32 +; PC64LE-NEXT: ld 3, .LC20@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 3, 5 ; PC64LE-NEXT: lxvd2x 2, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 2, 2 -; PC64LE-NEXT: xvmuldp 35, 1, 0 -; PC64LE-NEXT: xvmuldp 34, 1, 2 +; PC64LE-NEXT: xvmuldp 34, 1, 0 +; PC64LE-NEXT: xvmuldp 35, 1, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fmul_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI14_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC20@toc@ha +; PC64LE9-NEXT: ld 3, .LC20@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI14_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI14_2@toc@l +; PC64LE9-NEXT: lxv 1, 32(3) ; PC64LE9-NEXT: xvmuldp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -849,19 +821,19 @@ define <1 x float> @constrained_vector_fadd_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fadd_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI15_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI15_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI15_1@toc@l(4) -; PC64LE-NEXT: xsaddsp 1, 1, 0 +; PC64LE-NEXT: addis 3, 2, .LC21@toc@ha +; PC64LE-NEXT: ld 3, .LC21@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 +; PC64LE-NEXT: xsaddsp 1, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fadd_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI15_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI15_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC21@toc@ha +; PC64LE9-NEXT: ld 3, .LC21@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 4(3) ; PC64LE9-NEXT: xsaddsp 1, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -876,25 +848,22 @@ define <2 x double> @constrained_vector_fadd_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fadd_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI16_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI16_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC22@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC22@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvadddp 34, 1, 0 +; PC64LE-NEXT: xvadddp 34, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fadd_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI16_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC22@toc@ha +; PC64LE9-NEXT: ld 3, .LC22@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -909,23 +878,22 @@ define <3 x float> @constrained_vector_fadd_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fadd_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI17_2@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI17_1@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC23@toc@ha ; PC64LE-NEXT: xxlxor 3, 3, 3 -; PC64LE-NEXT: lfs 0, .LCPI17_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI17_2@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI17_1@toc@l(5) -; PC64LE-NEXT: addis 3, 2, .LCPI17_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI17_3@toc@l -; PC64LE-NEXT: xsaddsp 1, 0, 1 +; PC64LE-NEXT: ld 3, .LC23@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC24@toc@ha +; PC64LE-NEXT: ld 3, .LC24@toc@l(3) +; PC64LE-NEXT: xsaddsp 0, 1, 0 +; PC64LE-NEXT: xsaddsp 2, 1, 2 +; PC64LE-NEXT: xsaddsp 1, 1, 3 ; PC64LE-NEXT: lvx 4, 0, 3 -; PC64LE-NEXT: xsaddsp 2, 0, 2 -; PC64LE-NEXT: xsaddsp 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 -; PC64LE-NEXT: xxsldwi 34, 1, 1, 3 +; PC64LE-NEXT: xscvdpspn 2, 2 +; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 ; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 @@ -934,19 +902,18 @@ ; ; PC64LE9-LABEL: constrained_vector_fadd_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI17_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC23@toc@ha ; PC64LE9-NEXT: xxlxor 1, 1, 1 -; PC64LE9-NEXT: lfs 0, .LCPI17_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI17_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI17_2@toc@ha -; PC64LE9-NEXT: lfs 3, .LCPI17_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l +; PC64LE9-NEXT: ld 3, .LC23@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: lfs 2, 0(3) +; PC64LE9-NEXT: lfs 3, 4(3) +; PC64LE9-NEXT: addis 3, 2, .LC24@toc@ha +; PC64LE9-NEXT: ld 3, .LC24@toc@l(3) ; PC64LE9-NEXT: xsaddsp 1, 0, 1 -; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xsaddsp 2, 0, 2 ; PC64LE9-NEXT: xsaddsp 0, 0, 3 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 2 @@ -969,17 +936,17 @@ define <3 x double> @constrained_vector_fadd_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fadd_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI18_2@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI18_2@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PC64LE-NEXT: lfd 3, .LCPI18_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC25@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC25@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC26@toc@ha +; PC64LE-NEXT: ld 3, .LC26@toc@l(3) ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvadddp 2, 1, 0 +; PC64LE-NEXT: lfdx 3, 0, 3 +; PC64LE-NEXT: xvadddp 2, 0, 1 ; PC64LE-NEXT: xxlxor 0, 0, 0 ; PC64LE-NEXT: xsadddp 3, 3, 0 ; PC64LE-NEXT: xxswapd 1, 2 @@ -989,16 +956,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fadd_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI18_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC25@toc@ha ; PC64LE9-NEXT: xxlxor 1, 1, 1 -; PC64LE9-NEXT: lfd 0, .LCPI18_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l +; PC64LE9-NEXT: ld 3, .LC25@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC26@toc@ha +; PC64LE9-NEXT: ld 3, .LC26@toc@l(3) ; PC64LE9-NEXT: xsadddp 3, 0, 1 ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvadddp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1017,34 +983,28 @@ define <4 x double> @constrained_vector_fadd_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fadd_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI19_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI19_2@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI19_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 5, .LCPI19_2@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC27@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: li 5, 32 +; PC64LE-NEXT: ld 3, .LC27@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 3, 5 ; PC64LE-NEXT: lxvd2x 2, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 2, 2 -; PC64LE-NEXT: xvadddp 35, 1, 0 -; PC64LE-NEXT: xvadddp 34, 1, 2 +; PC64LE-NEXT: xvadddp 34, 1, 0 +; PC64LE-NEXT: xvadddp 35, 1, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fadd_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI19_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC27@toc@ha +; PC64LE9-NEXT: ld 3, .LC27@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI19_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI19_2@toc@l +; PC64LE9-NEXT: lxv 1, 32(3) ; PC64LE9-NEXT: xvadddp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1061,19 +1021,19 @@ define <1 x float> @constrained_vector_fsub_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fsub_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI20_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI20_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI20_1@toc@l(4) -; PC64LE-NEXT: xssubsp 1, 1, 0 +; PC64LE-NEXT: addis 3, 2, .LC28@toc@ha +; PC64LE-NEXT: ld 3, .LC28@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 +; PC64LE-NEXT: xssubsp 1, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fsub_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI20_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI20_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC28@toc@ha +; PC64LE9-NEXT: ld 3, .LC28@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: lfs 1, 4(3) ; PC64LE9-NEXT: xssubsp 1, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1088,25 +1048,22 @@ define <2 x double> @constrained_vector_fsub_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fsub_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI21_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI21_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC29@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC29@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvsubdp 34, 1, 0 +; PC64LE-NEXT: xvsubdp 34, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fsub_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC29@toc@ha +; PC64LE9-NEXT: ld 3, .LC29@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1121,23 +1078,22 @@ define <3 x float> @constrained_vector_fsub_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fsub_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI22_2@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI22_1@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC30@toc@ha ; PC64LE-NEXT: xxlxor 3, 3, 3 -; PC64LE-NEXT: lfs 0, .LCPI22_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI22_2@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI22_1@toc@l(5) -; PC64LE-NEXT: addis 3, 2, .LCPI22_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI22_3@toc@l -; PC64LE-NEXT: xssubsp 1, 0, 1 +; PC64LE-NEXT: ld 3, .LC30@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC31@toc@ha +; PC64LE-NEXT: ld 3, .LC31@toc@l(3) +; PC64LE-NEXT: xssubsp 0, 1, 0 +; PC64LE-NEXT: xssubsp 2, 1, 2 +; PC64LE-NEXT: xssubsp 1, 1, 3 ; PC64LE-NEXT: lvx 4, 0, 3 -; PC64LE-NEXT: xssubsp 2, 0, 2 -; PC64LE-NEXT: xssubsp 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 -; PC64LE-NEXT: xxsldwi 34, 1, 1, 3 +; PC64LE-NEXT: xscvdpspn 2, 2 +; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 ; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 @@ -1146,19 +1102,18 @@ ; ; PC64LE9-LABEL: constrained_vector_fsub_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI22_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC30@toc@ha ; PC64LE9-NEXT: xxlxor 1, 1, 1 -; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI22_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha -; PC64LE9-NEXT: lfs 3, .LCPI22_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l +; PC64LE9-NEXT: ld 3, .LC30@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: lfs 2, 0(3) +; PC64LE9-NEXT: lfs 3, 4(3) +; PC64LE9-NEXT: addis 3, 2, .LC31@toc@ha +; PC64LE9-NEXT: ld 3, .LC31@toc@l(3) ; PC64LE9-NEXT: xssubsp 1, 0, 1 -; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xssubsp 2, 0, 2 ; PC64LE9-NEXT: xssubsp 0, 0, 3 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 2 @@ -1181,17 +1136,17 @@ define <3 x double> @constrained_vector_fsub_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fsub_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI23_2@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI23_2@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PC64LE-NEXT: lfd 3, .LCPI23_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC32@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC32@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LC33@toc@ha +; PC64LE-NEXT: ld 3, .LC33@toc@l(3) ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvsubdp 2, 1, 0 +; PC64LE-NEXT: lfdx 3, 0, 3 +; PC64LE-NEXT: xvsubdp 2, 0, 1 ; PC64LE-NEXT: xxlxor 0, 0, 0 ; PC64LE-NEXT: xssubdp 3, 3, 0 ; PC64LE-NEXT: xxswapd 1, 2 @@ -1201,16 +1156,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fsub_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC32@toc@ha ; PC64LE9-NEXT: xxlxor 1, 1, 1 -; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l +; PC64LE9-NEXT: ld 3, .LC32@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC33@toc@ha +; PC64LE9-NEXT: ld 3, .LC33@toc@l(3) ; PC64LE9-NEXT: xssubdp 3, 0, 1 ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvsubdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1229,34 +1183,28 @@ define <4 x double> @constrained_vector_fsub_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fsub_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI24_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI24_2@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI24_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 5, .LCPI24_2@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC34@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: li 5, 32 +; PC64LE-NEXT: ld 3, .LC34@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 3, 5 ; PC64LE-NEXT: lxvd2x 2, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 2, 2 -; PC64LE-NEXT: xvsubdp 35, 1, 0 -; PC64LE-NEXT: xvsubdp 34, 1, 2 +; PC64LE-NEXT: xvsubdp 34, 1, 0 +; PC64LE-NEXT: xvsubdp 35, 1, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fsub_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC34@toc@ha +; PC64LE9-NEXT: ld 3, .LC34@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l +; PC64LE9-NEXT: lxv 1, 32(3) ; PC64LE9-NEXT: xvsubdp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1273,15 +1221,17 @@ define <1 x float> @constrained_vector_sqrt_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_sqrt_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI25_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC35@toc@ha +; PC64LE-NEXT: ld 3, .LC35@toc@l(3) +; PC64LE-NEXT: lfsx 0, 0, 3 ; PC64LE-NEXT: xssqrtsp 1, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_sqrt_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI25_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC35@toc@ha +; PC64LE9-NEXT: ld 3, .LC35@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xssqrtsp 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1295,8 +1245,8 @@ define <2 x double> @constrained_vector_sqrt_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_sqrt_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI26_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC36@toc@ha +; PC64LE-NEXT: ld 3, .LC36@toc@l(3) ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xvsqrtdp 34, 0 @@ -1304,8 +1254,8 @@ ; ; PC64LE9-LABEL: constrained_vector_sqrt_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI26_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC36@toc@ha +; PC64LE9-NEXT: ld 3, .LC36@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: blr @@ -1320,17 +1270,16 @@ define <3 x float> @constrained_vector_sqrt_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_sqrt_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI27_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI27_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI27_2@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI27_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI27_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC37@toc@ha +; PC64LE-NEXT: ld 3, .LC37@toc@l(3) +; PC64LE-NEXT: lfs 0, 8(3) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: addis 3, 2, .LC38@toc@ha +; PC64LE-NEXT: ld 3, .LC38@toc@l(3) ; PC64LE-NEXT: xssqrtsp 0, 0 -; PC64LE-NEXT: lfs 2, .LCPI27_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI27_3@toc@ha -; PC64LE-NEXT: xssqrtsp 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI27_3@toc@l ; PC64LE-NEXT: xssqrtsp 2, 2 +; PC64LE-NEXT: xssqrtsp 1, 1 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 @@ -1344,23 +1293,22 @@ ; ; PC64LE9-LABEL: constrained_vector_sqrt_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI27_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI27_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI27_2@toc@ha -; PC64LE9-NEXT: xssqrtsp 0, 0 -; PC64LE9-NEXT: lfs 2, .LCPI27_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI27_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI27_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC37@toc@ha +; PC64LE9-NEXT: ld 3, .LC37@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 8(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC38@toc@ha +; PC64LE9-NEXT: ld 3, .LC38@toc@l(3) ; PC64LE9-NEXT: xssqrtsp 1, 1 ; PC64LE9-NEXT: xssqrtsp 2, 2 -; PC64LE9-NEXT: xscvdpspn 0, 0 -; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xssqrtsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 -; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 -; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 +; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 +; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 +; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -1376,14 +1324,15 @@ define <3 x double> @constrained_vector_sqrt_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_sqrt_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI28_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC39@toc@ha +; PC64LE-NEXT: ld 3, .LC39@toc@l(3) ; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI28_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC40@toc@ha +; PC64LE-NEXT: ld 3, .LC40@toc@l(3) ; PC64LE-NEXT: xxswapd 0, 0 -; PC64LE-NEXT: xssqrtdp 3, 1 +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: xvsqrtdp 2, 0 +; PC64LE-NEXT: xssqrtdp 3, 1 ; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1391,10 +1340,11 @@ ; ; PC64LE9-LABEL: constrained_vector_sqrt_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI28_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI28_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC39@toc@ha +; PC64LE9-NEXT: ld 3, .LC39@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC40@toc@ha +; PC64LE9-NEXT: ld 3, .LC40@toc@l(3) ; PC64LE9-NEXT: xssqrtdp 3, 0 ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvsqrtdp 2, 0 @@ -1413,27 +1363,24 @@ define <4 x double> @constrained_vector_sqrt_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_sqrt_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI29_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI29_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC41@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC41@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvsqrtdp 35, 0 -; PC64LE-NEXT: xvsqrtdp 34, 1 +; PC64LE-NEXT: xvsqrtdp 34, 0 +; PC64LE-NEXT: xvsqrtdp 35, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_sqrt_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI29_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC41@toc@ha +; PC64LE9-NEXT: ld 3, .LC41@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI29_1@toc@l ; PC64LE9-NEXT: xvsqrtdp 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: blr entry: @@ -1451,10 +1398,10 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI30_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI30_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI30_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC42@toc@ha +; PC64LE-NEXT: ld 3, .LC42@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: bl powf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -1467,10 +1414,10 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI30_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI30_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC42@toc@ha +; PC64LE9-NEXT: ld 3, .LC42@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 0(3) ; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -1490,60 +1437,66 @@ ; PC64LE-LABEL: constrained_vector_pow_v2f64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -24(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) -; PC64LE-NEXT: addis 4, 2, .LCPI31_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI31_1@toc@l(4) -; PC64LE-NEXT: lfd 1, .LCPI31_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -96(1) +; PC64LE-NEXT: addis 3, 2, .LC43@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC44@toc@ha +; PC64LE-NEXT: ld 30, .LC43@toc@l(3) +; PC64LE-NEXT: ld 3, .LC44@toc@l(4) +; PC64LE-NEXT: lfsx 31, 0, 3 +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI31_2@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI31_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_pow_v2f64: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI31_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI31_1@toc@l(3) +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC43@toc@ha +; PC64LE9-NEXT: ld 30, .LC43@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC44@toc@ha +; PC64LE9-NEXT: ld 3, .LC44@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) +; PC64LE9-NEXT: lfs 31, 0(3) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI31_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfd 1, .LCPI31_2@toc@l(3) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -1559,34 +1512,33 @@ ; PC64LE-LABEL: constrained_vector_pow_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 4, 2, .LCPI32_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI32_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI32_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: addis 3, 2, .LC45@toc@ha +; PC64LE-NEXT: ld 30, .LC45@toc@l(3) +; PC64LE-NEXT: lfsx 31, 0, 30 +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl powf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI32_2@toc@ha ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI32_2@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl powf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI32_3@toc@ha ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 29, 1 -; PC64LE-NEXT: lfs 1, .LCPI32_3@toc@l(3) +; PC64LE-NEXT: lfs 1, 12(30) ; PC64LE-NEXT: bl powf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 29 -; PC64LE-NEXT: addis 3, 2, .LCPI32_4@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC46@toc@ha ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI32_4@toc@l +; PC64LE-NEXT: ld 3, .LC46@toc@l(3) ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xscvdpspn 0, 30 @@ -1594,10 +1546,11 @@ ; PC64LE-NEXT: vmrghw 2, 2, 3 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 3, 2, 4 -; PC64LE-NEXT: addi 1, 1, 64 +; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -1605,45 +1558,45 @@ ; PC64LE9-LABEL: constrained_vector_pow_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI32_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI32_1@toc@l(3) +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC45@toc@ha +; PC64LE9-NEXT: ld 30, .LC45@toc@l(3) +; PC64LE9-NEXT: lfs 31, 0(30) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI32_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI32_2@toc@l(3) ; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI32_3@toc@ha ; PC64LE9-NEXT: fmr 29, 1 +; PC64LE9-NEXT: lfs 1, 12(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfs 1, .LCPI32_3@toc@l(3) ; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: addis 3, 2, .LC46@toc@ha +; PC64LE9-NEXT: ld 3, .LC46@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 3, 2, 4 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr @@ -1661,14 +1614,15 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -96(1) -; PC64LE-NEXT: addis 4, 2, .LCPI33_1@toc@ha -; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stdu 1, -112(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: stfd 31, 104(1) # 8-byte Folded Spill +; PC64LE-NEXT: std 30, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI33_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI33_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC47@toc@ha +; PC64LE-NEXT: ld 3, .LC47@toc@l(3) +; PC64LE-NEXT: lfsx 31, 0, 3 +; PC64LE-NEXT: lfs 1, 4(3) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop @@ -1676,27 +1630,28 @@ ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI33_2@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI33_2@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC48@toc@ha +; PC64LE-NEXT: ld 30, .LC48@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI33_3@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI33_3@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 -; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload +; PC64LE-NEXT: lfd 31, 104(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 96 +; PC64LE-NEXT: addi 1, 1, 112 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -1705,38 +1660,40 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -80(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stdu 1, -96(1) +; PC64LE9-NEXT: addis 3, 2, .LC47@toc@ha +; PC64LE9-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE9-NEXT: std 30, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: ld 3, .LC47@toc@l(3) ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI33_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI33_1@toc@l(3) +; PC64LE9-NEXT: lfs 31, 0(3) ; PC64LE9-NEXT: fmr 2, 31 +; PC64LE9-NEXT: lfs 1, 4(3) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI33_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC48@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfd 1, .LCPI33_2@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC48@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI33_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI33_3@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 80 +; PC64LE9-NEXT: ld 30, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: addi 1, 1, 96 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -1754,51 +1711,52 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -96(1) -; PC64LE-NEXT: addis 4, 2, .LCPI34_1@toc@ha -; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stdu 1, -112(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: addis 4, 2, .LC49@toc@ha +; PC64LE-NEXT: std 30, 88(1) # 8-byte Folded Spill +; PC64LE-NEXT: stfd 31, 104(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI34_1@toc@l(4) -; PC64LE-NEXT: lfd 1, .LCPI34_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC50@toc@ha +; PC64LE-NEXT: ld 30, .LC50@toc@l(3) +; PC64LE-NEXT: ld 3, .LC49@toc@l(4) +; PC64LE-NEXT: lfsx 31, 0, 3 +; PC64LE-NEXT: lfd 1, 24(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI34_2@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI34_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI34_3@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI34_3@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI34_4@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI34_4@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 2, 31 -; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload +; PC64LE-NEXT: lfd 31, 104(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 35, 1, 0 -; PC64LE-NEXT: addi 1, 1, 96 +; PC64LE-NEXT: addi 1, 1, 112 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -1807,45 +1765,46 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -80(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stdu 1, -96(1) +; PC64LE9-NEXT: addis 3, 2, .LC49@toc@ha +; PC64LE9-NEXT: std 30, 72(1) # 8-byte Folded Spill +; PC64LE9-NEXT: stfd 31, 88(1) # 8-byte Folded Spill +; PC64LE9-NEXT: ld 30, .LC49@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC50@toc@ha ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI34_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI34_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC50@toc@l(3) +; PC64LE9-NEXT: lfd 1, 24(30) +; PC64LE9-NEXT: lfs 31, 0(3) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI34_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfd 1, .LCPI34_2@toc@l(3) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI34_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI34_3@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI34_4@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: fmr 2, 31 -; PC64LE9-NEXT: lfd 1, .LCPI34_4@toc@l(3) ; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE9-NEXT: ld 30, 72(1) # 8-byte Folded Reload ; PC64LE9-NEXT: xxmrghd 35, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 80 +; PC64LE9-NEXT: addi 1, 1, 96 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -1866,9 +1825,10 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI35_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC51@toc@ha ; PC64LE-NEXT: li 4, 3 -; PC64LE-NEXT: lfs 1, .LCPI35_0@toc@l(3) +; PC64LE-NEXT: ld 3, .LC51@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -1881,9 +1841,10 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI35_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC51@toc@ha ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfs 1, .LCPI35_0@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC51@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -1903,52 +1864,56 @@ ; PC64LE-LABEL: constrained_vector_powi_v2f64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha +; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: addis 3, 2, .LC52@toc@ha ; PC64LE-NEXT: li 4, 3 -; PC64LE-NEXT: lfd 1, .LCPI36_0@toc@l(3) +; PC64LE-NEXT: ld 30, .LC52@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI36_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 1, 0 -; PC64LE-NEXT: addi 1, 1, 64 +; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: ld 0, 16(1) +; PC64LE-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_powi_v2f64: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI36_0@toc@ha +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC52@toc@ha ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfd 1, .LCPI36_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC52@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfd 1, .LCPI36_1@toc@l(3) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) +; PC64LE9-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -1966,31 +1931,31 @@ ; PC64LE-LABEL: constrained_vector_powi_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI37_0@toc@ha +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC53@toc@ha ; PC64LE-NEXT: li 4, 3 -; PC64LE-NEXT: lfs 1, .LCPI37_0@toc@l(3) +; PC64LE-NEXT: ld 30, .LC53@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 ; PC64LE-NEXT: li 4, 3 -; PC64LE-NEXT: lfs 1, .LCPI37_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI37_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: li 4, 3 -; PC64LE-NEXT: lfs 1, .LCPI37_2@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI37_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC54@toc@ha ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI37_3@toc@l +; PC64LE-NEXT: ld 3, .LC54@toc@l(3) ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xscvdpspn 0, 31 @@ -1998,52 +1963,54 @@ ; PC64LE-NEXT: vmrghw 2, 2, 3 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 3, 2, 4 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_powi_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI37_0@toc@ha +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC53@toc@ha ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfs 1, .LCPI37_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC53@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfs 1, .LCPI37_1@toc@l(3) ; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI37_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfs 1, .LCPI37_2@toc@l(3) ; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: addis 3, 2, .LC54@toc@ha +; PC64LE9-NEXT: ld 3, .LC54@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 3, 2, 4 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -2060,38 +2027,41 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI38_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC55@toc@ha +; PC64LE-NEXT: ld 30, .LC55@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI38_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC56@toc@ha +; PC64LE-NEXT: ld 3, .LC56@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI38_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI38_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -2100,34 +2070,37 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI38_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC55@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI38_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC55@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI38_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC56@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfs 1, .LCPI38_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC56@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI38_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI38_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -2145,47 +2118,47 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI39_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC57@toc@ha +; PC64LE-NEXT: ld 30, .LC57@toc@l(3) +; PC64LE-NEXT: lfd 1, 24(30) ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI39_1@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI39_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI39_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 4, 3 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI39_3@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI39_3@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 2, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 35, 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -2194,41 +2167,41 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI39_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC57@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI39_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC57@toc@l(3) +; PC64LE9-NEXT: lfd 1, 24(30) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI39_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfd 1, .LCPI39_1@toc@l(3) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI39_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI39_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI39_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: li 4, 3 -; PC64LE9-NEXT: lfd 1, .LCPI39_3@toc@l(3) ; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 35, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -2248,8 +2221,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI40_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI40_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC58@toc@ha +; PC64LE-NEXT: ld 3, .LC58@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -2262,8 +2236,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI40_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI40_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC58@toc@ha +; PC64LE9-NEXT: ld 3, .LC58@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -2284,15 +2259,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI41_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI41_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC59@toc@ha +; PC64LE-NEXT: ld 3, .LC59@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI41_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI41_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC60@toc@ha +; PC64LE-NEXT: ld 3, .LC60@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -2309,14 +2286,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI41_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI41_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC59@toc@ha +; PC64LE9-NEXT: ld 3, .LC59@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI41_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC60@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI41_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC60@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -2338,66 +2317,67 @@ ; PC64LE-LABEL: constrained_vector_sin_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI42_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC61@toc@ha +; PC64LE-NEXT: ld 30, .LC61@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI42_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI42_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI42_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI42_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI42_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI42_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC62@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC62@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_sin_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI42_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC61@toc@ha +; PC64LE9-NEXT: ld 30, .LC61@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI42_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI42_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI42_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI42_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC62@toc@ha +; PC64LE9-NEXT: ld 3, .LC62@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -2406,10 +2386,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -2425,35 +2406,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI43_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI43_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC63@toc@ha +; PC64LE-NEXT: ld 30, .LC63@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI43_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC64@toc@ha +; PC64LE-NEXT: ld 3, .LC64@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI43_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI43_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -2462,31 +2446,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI43_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC63@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI43_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC63@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI43_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC64@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI43_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC64@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI43_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI43_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -2503,43 +2490,45 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI44_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI44_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC65@toc@ha +; PC64LE-NEXT: ld 30, .LC65@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI44_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI44_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI44_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI44_3@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI44_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC66@toc@ha +; PC64LE-NEXT: ld 3, .LC66@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl sin ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 3, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 0, 1 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -2548,37 +2537,39 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI44_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC65@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI44_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC65@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI44_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI44_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI44_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI44_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI44_3@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC66@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI44_3@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC66@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 3, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 0, 1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -2597,8 +2588,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI45_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC67@toc@ha +; PC64LE-NEXT: ld 3, .LC67@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -2611,8 +2603,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI45_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC67@toc@ha +; PC64LE9-NEXT: ld 3, .LC67@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -2633,15 +2626,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI46_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC68@toc@ha +; PC64LE-NEXT: ld 3, .LC68@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI46_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC69@toc@ha +; PC64LE-NEXT: ld 3, .LC69@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -2658,14 +2653,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI46_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC68@toc@ha +; PC64LE9-NEXT: ld 3, .LC68@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI46_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC69@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI46_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC69@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -2687,66 +2684,67 @@ ; PC64LE-LABEL: constrained_vector_cos_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI47_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC70@toc@ha +; PC64LE-NEXT: ld 30, .LC70@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI47_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI47_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI47_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI47_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI47_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI47_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC71@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC71@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_cos_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI47_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC70@toc@ha +; PC64LE9-NEXT: ld 30, .LC70@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI47_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI47_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI47_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI47_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC71@toc@ha +; PC64LE9-NEXT: ld 3, .LC71@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -2755,10 +2753,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -2774,35 +2773,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI48_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC72@toc@ha +; PC64LE-NEXT: ld 30, .LC72@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI48_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC73@toc@ha +; PC64LE-NEXT: ld 3, .LC73@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI48_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI48_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -2811,31 +2813,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI48_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC72@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI48_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC72@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI48_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC73@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI48_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC73@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI48_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI48_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -2852,43 +2857,45 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI49_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI49_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC74@toc@ha +; PC64LE-NEXT: ld 30, .LC74@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI49_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI49_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI49_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI49_3@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI49_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC75@toc@ha +; PC64LE-NEXT: ld 3, .LC75@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl cos ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 3, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 0, 1 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -2897,37 +2904,39 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI49_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC74@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI49_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC74@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI49_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI49_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI49_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI49_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI49_3@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC75@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI49_3@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC75@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 3, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 0, 1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -2946,8 +2955,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI50_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC76@toc@ha +; PC64LE-NEXT: ld 3, .LC76@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl expf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -2960,8 +2970,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI50_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC76@toc@ha +; PC64LE9-NEXT: ld 3, .LC76@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -2982,15 +2993,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI51_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC77@toc@ha +; PC64LE-NEXT: ld 3, .LC77@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI51_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC78@toc@ha +; PC64LE-NEXT: ld 3, .LC78@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -3007,14 +3020,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI51_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC77@toc@ha +; PC64LE9-NEXT: ld 3, .LC77@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI51_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC78@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI51_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC78@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -3036,66 +3051,67 @@ ; PC64LE-LABEL: constrained_vector_exp_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI52_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC79@toc@ha +; PC64LE-NEXT: ld 30, .LC79@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl expf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI52_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI52_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl expf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI52_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI52_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl expf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI52_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI52_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC80@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC80@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_exp_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI52_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC79@toc@ha +; PC64LE9-NEXT: ld 30, .LC79@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI52_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI52_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI52_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI52_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC80@toc@ha +; PC64LE9-NEXT: ld 3, .LC80@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -3104,10 +3120,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -3123,35 +3140,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI53_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI53_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC81@toc@ha +; PC64LE-NEXT: ld 30, .LC81@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI53_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC82@toc@ha +; PC64LE-NEXT: ld 3, .LC82@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI53_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI53_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -3160,31 +3180,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI53_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC81@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI53_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC81@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI53_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC82@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI53_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC82@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI53_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI53_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -3201,43 +3224,45 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI54_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI54_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC83@toc@ha +; PC64LE-NEXT: ld 30, .LC83@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI54_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI54_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI54_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI54_3@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI54_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC84@toc@ha +; PC64LE-NEXT: ld 3, .LC84@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl exp ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 3, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 0, 1 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -3246,37 +3271,39 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI54_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC83@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI54_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC83@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI54_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI54_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI54_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI54_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI54_3@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC84@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI54_3@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC84@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 3, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 0, 1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -3295,8 +3322,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI55_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC85@toc@ha +; PC64LE-NEXT: ld 3, .LC85@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -3309,8 +3337,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI55_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC85@toc@ha +; PC64LE9-NEXT: ld 3, .LC85@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -3331,15 +3360,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI56_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC86@toc@ha +; PC64LE-NEXT: ld 3, .LC86@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI56_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC87@toc@ha +; PC64LE-NEXT: ld 3, .LC87@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -3356,14 +3387,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI56_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC86@toc@ha +; PC64LE9-NEXT: ld 3, .LC86@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI56_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC87@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI56_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC87@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -3385,66 +3418,67 @@ ; PC64LE-LABEL: constrained_vector_exp2_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI57_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC88@toc@ha +; PC64LE-NEXT: ld 30, .LC88@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI57_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI57_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI57_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI57_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI57_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI57_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC89@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC89@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_exp2_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI57_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC88@toc@ha +; PC64LE9-NEXT: ld 30, .LC88@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI57_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI57_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI57_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI57_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC89@toc@ha +; PC64LE9-NEXT: ld 3, .LC89@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -3453,10 +3487,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -3472,35 +3507,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI58_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC90@toc@ha +; PC64LE-NEXT: ld 30, .LC90@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI58_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC91@toc@ha +; PC64LE-NEXT: ld 3, .LC91@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI58_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI58_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -3509,31 +3547,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI58_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC90@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI58_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC90@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI58_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC91@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI58_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC91@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI58_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI58_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -3550,43 +3591,43 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI59_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC92@toc@ha +; PC64LE-NEXT: ld 30, .LC92@toc@l(3) +; PC64LE-NEXT: lfd 1, 24(30) ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI59_1@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI59_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI59_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI59_3@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI59_3@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 2, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 35, 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -3595,37 +3636,37 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI59_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC92@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI59_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC92@toc@l(3) +; PC64LE9-NEXT: lfd 1, 24(30) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI59_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI59_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI59_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI59_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI59_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI59_3@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 35, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -3644,8 +3685,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI60_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC93@toc@ha +; PC64LE-NEXT: ld 3, .LC93@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl logf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -3658,8 +3700,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI60_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC93@toc@ha +; PC64LE9-NEXT: ld 3, .LC93@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -3680,15 +3723,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI61_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC94@toc@ha +; PC64LE-NEXT: ld 3, .LC94@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI61_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC95@toc@ha +; PC64LE-NEXT: ld 3, .LC95@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -3705,14 +3750,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI61_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC94@toc@ha +; PC64LE9-NEXT: ld 3, .LC94@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI61_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC95@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI61_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC95@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -3734,66 +3781,67 @@ ; PC64LE-LABEL: constrained_vector_log_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI62_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC96@toc@ha +; PC64LE-NEXT: ld 30, .LC96@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl logf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI62_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI62_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl logf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI62_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI62_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl logf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI62_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI62_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC97@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC97@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_log_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI62_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC96@toc@ha +; PC64LE9-NEXT: ld 30, .LC96@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI62_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI62_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI62_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI62_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC97@toc@ha +; PC64LE9-NEXT: ld 3, .LC97@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -3802,10 +3850,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -3821,35 +3870,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI63_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC98@toc@ha +; PC64LE-NEXT: ld 30, .LC98@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI63_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC99@toc@ha +; PC64LE-NEXT: ld 3, .LC99@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI63_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI63_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -3858,31 +3910,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI63_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC98@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI63_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC98@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI63_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC99@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI63_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC99@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI63_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI63_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -3899,43 +3954,45 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI64_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC100@toc@ha +; PC64LE-NEXT: ld 30, .LC100@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI64_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI64_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI64_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI64_3@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI64_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC101@toc@ha +; PC64LE-NEXT: ld 3, .LC101@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 3, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 0, 1 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -3944,37 +4001,39 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI64_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC100@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI64_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC100@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI64_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI64_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI64_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI64_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI64_3@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC101@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI64_3@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC101@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 3, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 0, 1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -3993,8 +4052,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI65_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC102@toc@ha +; PC64LE-NEXT: ld 3, .LC102@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -4007,8 +4067,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI65_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC102@toc@ha +; PC64LE9-NEXT: ld 3, .LC102@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -4029,15 +4090,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI66_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC103@toc@ha +; PC64LE-NEXT: ld 3, .LC103@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI66_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC104@toc@ha +; PC64LE-NEXT: ld 3, .LC104@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -4054,14 +4117,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI66_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC103@toc@ha +; PC64LE9-NEXT: ld 3, .LC103@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI66_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC104@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI66_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC104@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -4083,66 +4148,67 @@ ; PC64LE-LABEL: constrained_vector_log10_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI67_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC105@toc@ha +; PC64LE-NEXT: ld 30, .LC105@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI67_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI67_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI67_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI67_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI67_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI67_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC106@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC106@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_log10_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI67_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC105@toc@ha +; PC64LE9-NEXT: ld 30, .LC105@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI67_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI67_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI67_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI67_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC106@toc@ha +; PC64LE9-NEXT: ld 3, .LC106@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -4151,10 +4217,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -4170,35 +4237,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI68_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC107@toc@ha +; PC64LE-NEXT: ld 30, .LC107@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI68_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC108@toc@ha +; PC64LE-NEXT: ld 3, .LC108@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI68_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI68_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -4207,31 +4277,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI68_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC107@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI68_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC107@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI68_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC108@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI68_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC108@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI68_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI68_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -4248,43 +4321,45 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI69_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC109@toc@ha +; PC64LE-NEXT: ld 30, .LC109@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI69_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI69_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI69_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI69_3@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI69_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC110@toc@ha +; PC64LE-NEXT: ld 3, .LC110@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 3, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 0, 1 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -4293,37 +4368,39 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI69_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC109@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI69_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC109@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI69_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI69_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI69_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI69_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI69_3@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC110@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI69_3@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC110@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 3, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 0, 1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -4342,8 +4419,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI70_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC111@toc@ha +; PC64LE-NEXT: ld 3, .LC111@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -4356,8 +4434,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI70_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC111@toc@ha +; PC64LE9-NEXT: ld 3, .LC111@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -4378,15 +4457,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI71_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC112@toc@ha +; PC64LE-NEXT: ld 3, .LC112@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI71_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC113@toc@ha +; PC64LE-NEXT: ld 3, .LC113@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -4403,14 +4484,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI71_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC112@toc@ha +; PC64LE9-NEXT: ld 3, .LC112@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI71_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC113@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI71_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC113@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -4432,66 +4515,67 @@ ; PC64LE-LABEL: constrained_vector_log2_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI72_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC114@toc@ha +; PC64LE-NEXT: ld 30, .LC114@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI72_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI72_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI72_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI72_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI72_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI72_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC115@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC115@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_log2_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI72_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC114@toc@ha +; PC64LE9-NEXT: ld 30, .LC114@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI72_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI72_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI72_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI72_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC115@toc@ha +; PC64LE9-NEXT: ld 3, .LC115@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -4500,10 +4584,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -4519,35 +4604,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI73_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI73_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC116@toc@ha +; PC64LE-NEXT: ld 30, .LC116@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI73_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC117@toc@ha +; PC64LE-NEXT: ld 3, .LC117@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI73_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI73_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -4556,31 +4644,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI73_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC116@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI73_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC116@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI73_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC117@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI73_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC117@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI73_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI73_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -4597,43 +4688,45 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI74_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI74_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC118@toc@ha +; PC64LE-NEXT: ld 30, .LC118@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI74_1@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI74_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI74_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI74_3@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI74_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC119@toc@ha +; PC64LE-NEXT: ld 3, .LC119@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 3, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 34, 0, 1 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -4642,37 +4735,39 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI74_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC118@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI74_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC118@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI74_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI74_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI74_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI74_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI74_3@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC119@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI74_3@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC119@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 3, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 34, 0, 1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -4688,15 +4783,17 @@ define <1 x float> @constrained_vector_rint_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_rint_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI75_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC120@toc@ha +; PC64LE-NEXT: ld 3, .LC120@toc@l(3) +; PC64LE-NEXT: lfsx 0, 0, 3 ; PC64LE-NEXT: xsrdpic 1, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_rint_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI75_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC120@toc@ha +; PC64LE9-NEXT: ld 3, .LC120@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xsrdpic 1, 0 ; PC64LE9-NEXT: blr entry: @@ -4710,8 +4807,8 @@ define <2 x double> @constrained_vector_rint_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_rint_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI76_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC121@toc@ha +; PC64LE-NEXT: ld 3, .LC121@toc@l(3) ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xvrdpic 34, 0 @@ -4719,8 +4816,8 @@ ; ; PC64LE9-LABEL: constrained_vector_rint_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI76_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC121@toc@ha +; PC64LE9-NEXT: ld 3, .LC121@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvrdpic 34, 0 ; PC64LE9-NEXT: blr @@ -4735,16 +4832,15 @@ define <3 x float> @constrained_vector_rint_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_rint_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI77_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI77_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI77_2@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI77_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI77_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC122@toc@ha +; PC64LE-NEXT: ld 3, .LC122@toc@l(3) +; PC64LE-NEXT: lfs 0, 8(3) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: addis 3, 2, .LC123@toc@ha +; PC64LE-NEXT: ld 3, .LC123@toc@l(3) ; PC64LE-NEXT: xsrdpic 0, 0 -; PC64LE-NEXT: lfs 2, .LCPI77_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI77_3@toc@ha ; PC64LE-NEXT: xsrdpic 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI77_3@toc@l ; PC64LE-NEXT: xsrdpic 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -4759,23 +4855,22 @@ ; ; PC64LE9-LABEL: constrained_vector_rint_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI77_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI77_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI77_2@toc@ha -; PC64LE9-NEXT: xsrdpic 0, 0 -; PC64LE9-NEXT: lfs 2, .LCPI77_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI77_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI77_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC122@toc@ha +; PC64LE9-NEXT: ld 3, .LC122@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 8(3) +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC123@toc@ha +; PC64LE9-NEXT: ld 3, .LC123@toc@l(3) ; PC64LE9-NEXT: xsrdpic 1, 1 ; PC64LE9-NEXT: xsrdpic 2, 2 -; PC64LE9-NEXT: xscvdpspn 0, 0 -; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xsrdpic 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 -; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 -; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 +; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 +; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 +; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -4791,14 +4886,15 @@ define <3 x double> @constrained_vector_rint_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_rint_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI78_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC124@toc@ha +; PC64LE-NEXT: ld 3, .LC124@toc@l(3) ; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI78_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC125@toc@ha +; PC64LE-NEXT: ld 3, .LC125@toc@l(3) ; PC64LE-NEXT: xxswapd 0, 0 -; PC64LE-NEXT: xsrdpic 3, 1 +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: xvrdpic 2, 0 +; PC64LE-NEXT: xsrdpic 3, 1 ; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -4806,10 +4902,11 @@ ; ; PC64LE9-LABEL: constrained_vector_rint_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI78_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI78_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC124@toc@ha +; PC64LE9-NEXT: ld 3, .LC124@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: addis 3, 2, .LC125@toc@ha +; PC64LE9-NEXT: ld 3, .LC125@toc@l(3) ; PC64LE9-NEXT: xsrdpic 3, 0 ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvrdpic 2, 0 @@ -4828,11 +4925,10 @@ define <4 x double> @constrained_vector_rint_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_rint_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI79_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI79_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC126@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC126@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 @@ -4842,11 +4938,9 @@ ; ; PC64LE9-LABEL: constrained_vector_rint_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI79_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC126@toc@ha +; PC64LE9-NEXT: ld 3, .LC126@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvrdpic 34, 0 ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvrdpic 35, 0 @@ -4866,8 +4960,9 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI80_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC127@toc@ha +; PC64LE-NEXT: ld 3, .LC127@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -4880,8 +4975,9 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI80_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC127@toc@ha +; PC64LE9-NEXT: ld 3, .LC127@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -4902,15 +4998,17 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI81_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC128@toc@ha +; PC64LE-NEXT: ld 3, .LC128@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI81_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC129@toc@ha +; PC64LE-NEXT: ld 3, .LC129@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 @@ -4927,14 +5025,16 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI81_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC128@toc@ha +; PC64LE9-NEXT: ld 3, .LC128@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI81_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC129@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI81_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC129@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload @@ -4956,66 +5056,67 @@ ; PC64LE-LABEL: constrained_vector_nearbyint_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -48(1) -; PC64LE-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI82_0@toc@l(3) +; PC64LE-NEXT: stdu 1, -64(1) +; PC64LE-NEXT: addis 3, 2, .LC130@toc@ha +; PC64LE-NEXT: ld 30, .LC130@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(30) ; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI82_1@toc@ha ; PC64LE-NEXT: fmr 31, 1 -; PC64LE-NEXT: lfs 1, .LCPI82_1@toc@l(3) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI82_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI82_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 30 ; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: nop ; PC64LE-NEXT: xscvdpspn 0, 30 -; PC64LE-NEXT: addis 3, 2, .LCPI82_3@toc@ha -; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI82_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC131@toc@ha +; PC64LE-NEXT: xscvdpspn 2, 31 +; PC64LE-NEXT: ld 3, .LC131@toc@l(3) ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE-NEXT: xscvdpspn 0, 31 -; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: xscvdpspn 0, 1 +; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 -; PC64LE-NEXT: addi 1, 1, 48 +; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -48(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI82_0@toc@l(3) +; PC64LE9-NEXT: stdu 1, -64(1) +; PC64LE9-NEXT: addis 3, 2, .LC130@toc@ha +; PC64LE9-NEXT: ld 30, .LC130@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(30) ; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI82_1@toc@ha ; PC64LE9-NEXT: fmr 31, 1 -; PC64LE9-NEXT: lfs 1, .LCPI82_1@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(30) ; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI82_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI82_2@toc@l(3) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC131@toc@ha +; PC64LE9-NEXT: ld 3, .LC131@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -5024,10 +5125,11 @@ ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 -; PC64LE9-NEXT: addi 1, 1, 48 +; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: @@ -5043,35 +5145,38 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI83_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI83_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC132@toc@ha +; PC64LE-NEXT: ld 30, .LC132@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI83_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC133@toc@ha +; PC64LE-NEXT: ld 3, .LC133@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI83_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 0, 1 -; PC64LE-NEXT: lfd 1, .LCPI83_2@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: xxlor 2, 63, 63 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -5080,31 +5185,34 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI83_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC132@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI83_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC132@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI83_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC133@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfs 1, .LCPI83_1@toc@l(3) +; PC64LE9-NEXT: ld 3, .LC133@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI83_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1 -; PC64LE9-NEXT: lfd 1, .LCPI83_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -5121,43 +5229,43 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) -; PC64LE-NEXT: stdu 1, -80(1) +; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI84_0@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI84_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC134@toc@ha +; PC64LE-NEXT: ld 30, .LC134@toc@l(3) +; PC64LE-NEXT: lfd 1, 24(30) ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI84_1@toc@l(3) +; PC64LE-NEXT: lfd 1, 16(30) ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload -; PC64LE-NEXT: addis 3, 2, .LCPI84_2@toc@ha ; PC64LE-NEXT: xxmrghd 63, 1, 0 -; PC64LE-NEXT: lfd 1, .LCPI84_2@toc@l(3) +; PC64LE-NEXT: lfd 1, 8(30) ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop -; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill -; PC64LE-NEXT: addis 3, 2, .LCPI84_3@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI84_3@toc@l(3) +; PC64LE-NEXT: lfdx 1, 0, 30 ; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: vmr 2, 31 +; PC64LE-NEXT: ld 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: xxmrghd 35, 1, 0 -; PC64LE-NEXT: addi 1, 1, 80 +; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr @@ -5166,37 +5274,37 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI84_0@toc@ha +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC134@toc@ha +; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI84_0@toc@l(3) +; PC64LE9-NEXT: ld 30, .LC134@toc@l(3) +; PC64LE9-NEXT: lfd 1, 24(30) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI84_1@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI84_1@toc@l(3) +; PC64LE9-NEXT: lfd 1, 16(30) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: addis 3, 2, .LCPI84_2@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 63, 1, 0 -; PC64LE9-NEXT: lfd 1, .LCPI84_2@toc@l(3) +; PC64LE9-NEXT: lfd 1, 8(30) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI84_3@toc@ha ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill -; PC64LE9-NEXT: lfd 1, .LCPI84_3@toc@l(3) +; PC64LE9-NEXT: lfd 1, 0(30) ; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload +; PC64LE9-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: xxmrghd 35, 1, 0 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr @@ -5215,10 +5323,10 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI85_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI85_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI85_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC135@toc@ha +; PC64LE-NEXT: ld 3, .LC135@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -5231,10 +5339,10 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI85_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI85_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC135@toc@ha +; PC64LE9-NEXT: ld 3, .LC135@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 0(3) ; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -5251,25 +5359,22 @@ define <2 x double> @constrained_vector_maxnum_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_maxnum_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI86_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI86_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC136@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC136@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvmaxdp 34, 1, 0 +; PC64LE-NEXT: xvmaxdp 34, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_maxnum_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI86_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC136@toc@ha +; PC64LE9-NEXT: ld 3, .LC136@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvmaxdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5284,93 +5389,89 @@ ; PC64LE-LABEL: constrained_vector_maxnum_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 -; PC64LE-NEXT: stfd 29, -24(1) # 8-byte Folded Spill +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 4, 2, .LCPI87_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI87_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI87_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC137@toc@ha +; PC64LE-NEXT: ld 30, .LC137@toc@l(3) +; PC64LE-NEXT: lfs 31, 16(30) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI87_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI87_3@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI87_2@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI87_3@toc@l(4) +; PC64LE-NEXT: fmr 1, 31 +; PC64LE-NEXT: lfs 2, 4(30) ; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: nop -; PC64LE-NEXT: fmr 29, 1 -; PC64LE-NEXT: addis 3, 2, .LCPI87_4@toc@ha -; PC64LE-NEXT: fmr 1, 31 -; PC64LE-NEXT: lfs 2, .LCPI87_4@toc@l(3) +; PC64LE-NEXT: fmr 31, 1 +; PC64LE-NEXT: lfsx 2, 0, 30 +; PC64LE-NEXT: lfs 1, 12(30) ; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: nop -; PC64LE-NEXT: xscvdpspn 0, 29 -; PC64LE-NEXT: addis 3, 2, .LCPI87_5@toc@ha +; PC64LE-NEXT: xscvdpspn 0, 31 +; PC64LE-NEXT: addis 3, 2, .LC138@toc@ha ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI87_5@toc@l +; PC64LE-NEXT: ld 3, .LC138@toc@l(3) ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload -; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_maxnum_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI87_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI87_1@toc@l(3) +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC137@toc@ha +; PC64LE9-NEXT: ld 30, .LC137@toc@l(3) +; PC64LE9-NEXT: lfs 31, 16(30) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI87_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI87_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI87_3@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI87_3@toc@l(3) +; PC64LE9-NEXT: lfs 1, 12(30) +; PC64LE9-NEXT: lfs 2, 0(30) ; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI87_4@toc@ha +; PC64LE9-NEXT: lfs 2, 4(30) ; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 1, 31 -; PC64LE9-NEXT: lfs 2, .LCPI87_4@toc@l(3) ; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: addis 3, 2, .LC138@toc@ha +; PC64LE9-NEXT: ld 3, .LC138@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 3, 2, 4 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr @@ -5388,22 +5489,21 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI88_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI88_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI88_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC139@toc@ha +; PC64LE-NEXT: ld 3, .LC139@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: bl fmax ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI88_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI88_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC140@toc@ha +; PC64LE-NEXT: li 4, 16 ; PC64LE-NEXT: fmr 3, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI88_2@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI88_3@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 2, 0, 4 +; PC64LE-NEXT: ld 3, .LC140@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 2, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 2, 2 -; PC64LE-NEXT: xvmaxdp 2, 2, 0 +; PC64LE-NEXT: xvmaxdp 2, 0, 2 ; PC64LE-NEXT: xxswapd 0, 2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: fmr 1, 0 @@ -5417,19 +5517,17 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI88_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI88_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC139@toc@ha +; PC64LE9-NEXT: ld 3, .LC139@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 0(3) ; PC64LE9-NEXT: bl fmax ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC140@toc@ha ; PC64LE9-NEXT: fmr 3, 1 -; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l +; PC64LE9-NEXT: ld 3, .LC140@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvmaxdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -5449,41 +5547,32 @@ define <4 x double> @constrained_vector_maxnum_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_maxnum_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI89_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI89_2@toc@ha -; PC64LE-NEXT: addis 6, 2, .LCPI89_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI89_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addi 3, 5, .LCPI89_2@toc@l -; PC64LE-NEXT: addi 4, 6, .LCPI89_3@toc@l -; PC64LE-NEXT: lxvd2x 2, 0, 3 -; PC64LE-NEXT: lxvd2x 3, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC141@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: li 5, 48 +; PC64LE-NEXT: ld 3, .LC141@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: li 4, 32 +; PC64LE-NEXT: lxvd2x 1, 3, 5 +; PC64LE-NEXT: lxvd2x 2, 3, 4 +; PC64LE-NEXT: lxvd2x 3, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 2, 2 ; PC64LE-NEXT: xxswapd 3, 3 ; PC64LE-NEXT: xvmaxdp 34, 1, 0 -; PC64LE-NEXT: xvmaxdp 35, 3, 2 +; PC64LE-NEXT: xvmaxdp 35, 2, 3 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_maxnum_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI89_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI89_2@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC141@toc@ha +; PC64LE9-NEXT: ld 3, .LC141@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) +; PC64LE9-NEXT: lxv 1, 48(3) ; PC64LE9-NEXT: xvmaxdp 34, 1, 0 ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI89_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI89_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 32(3) ; PC64LE9-NEXT: xvmaxdp 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5502,10 +5591,10 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI90_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI90_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI90_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC142@toc@ha +; PC64LE-NEXT: ld 3, .LC142@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: nop ; PC64LE-NEXT: addi 1, 1, 32 @@ -5518,10 +5607,10 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI90_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI90_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC142@toc@ha +; PC64LE9-NEXT: ld 3, .LC142@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 0(3) ; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: addi 1, 1, 32 @@ -5538,25 +5627,22 @@ define <2 x double> @constrained_vector_minnum_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_minnum_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI91_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI91_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC143@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC143@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvmindp 34, 1, 0 +; PC64LE-NEXT: xvmindp 34, 0, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_minnum_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI91_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC143@toc@ha +; PC64LE9-NEXT: ld 3, .LC143@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvmindp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5571,93 +5657,89 @@ ; PC64LE-LABEL: constrained_vector_minnum_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mflr 0 -; PC64LE-NEXT: stfd 29, -24(1) # 8-byte Folded Spill +; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -64(1) -; PC64LE-NEXT: addis 4, 2, .LCPI92_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI92_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI92_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC144@toc@ha +; PC64LE-NEXT: ld 30, .LC144@toc@l(3) +; PC64LE-NEXT: lfs 31, 16(30) +; PC64LE-NEXT: lfs 1, 8(30) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI92_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI92_3@toc@ha ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: lfs 1, .LCPI92_2@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI92_3@toc@l(4) +; PC64LE-NEXT: fmr 1, 31 +; PC64LE-NEXT: lfs 2, 4(30) ; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: nop -; PC64LE-NEXT: fmr 29, 1 -; PC64LE-NEXT: addis 3, 2, .LCPI92_4@toc@ha -; PC64LE-NEXT: fmr 1, 31 -; PC64LE-NEXT: lfs 2, .LCPI92_4@toc@l(3) +; PC64LE-NEXT: fmr 31, 1 +; PC64LE-NEXT: lfsx 2, 0, 30 +; PC64LE-NEXT: lfs 1, 12(30) ; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: nop -; PC64LE-NEXT: xscvdpspn 0, 29 -; PC64LE-NEXT: addis 3, 2, .LCPI92_5@toc@ha +; PC64LE-NEXT: xscvdpspn 0, 31 +; PC64LE-NEXT: addis 3, 2, .LC145@toc@ha ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI92_5@toc@l +; PC64LE-NEXT: ld 3, .LC145@toc@l(3) ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 -; PC64LE-NEXT: vmrghw 2, 2, 3 +; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload -; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_minnum_v3f32: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mflr 0 +; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 0, 16(1) -; PC64LE9-NEXT: stdu 1, -64(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI92_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PC64LE9-NEXT: lfs 31, .LCPI92_1@toc@l(3) +; PC64LE9-NEXT: stdu 1, -80(1) +; PC64LE9-NEXT: addis 3, 2, .LC144@toc@ha +; PC64LE9-NEXT: ld 30, .LC144@toc@l(3) +; PC64LE9-NEXT: lfs 31, 16(30) +; PC64LE9-NEXT: lfs 1, 8(30) ; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI92_2@toc@ha ; PC64LE9-NEXT: fmr 30, 1 -; PC64LE9-NEXT: lfs 1, .LCPI92_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI92_3@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI92_3@toc@l(3) +; PC64LE9-NEXT: lfs 1, 12(30) +; PC64LE9-NEXT: lfs 2, 0(30) ; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI92_4@toc@ha +; PC64LE9-NEXT: lfs 2, 4(30) ; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 1, 31 -; PC64LE9-NEXT: lfs 2, .LCPI92_4@toc@l(3) ; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: nop ; PC64LE9-NEXT: xscvdpspn 0, 1 -; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: addis 3, 2, .LC145@toc@ha +; PC64LE9-NEXT: ld 3, .LC145@toc@l(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 +; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 3, 2, 4 -; PC64LE9-NEXT: addi 1, 1, 64 +; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr @@ -5675,22 +5757,21 @@ ; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: stdu 1, -32(1) -; PC64LE-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI93_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI93_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI93_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC146@toc@ha +; PC64LE-NEXT: ld 3, .LC146@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: bl fmin ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI93_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI93_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC147@toc@ha +; PC64LE-NEXT: li 4, 16 ; PC64LE-NEXT: fmr 3, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI93_2@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI93_3@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 2, 0, 4 +; PC64LE-NEXT: ld 3, .LC147@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: lxvd2x 2, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 2, 2 -; PC64LE-NEXT: xvmindp 2, 2, 0 +; PC64LE-NEXT: xvmindp 2, 0, 2 ; PC64LE-NEXT: xxswapd 0, 2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: fmr 1, 0 @@ -5704,19 +5785,17 @@ ; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: stdu 1, -32(1) -; PC64LE9-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI93_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI93_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC146@toc@ha +; PC64LE9-NEXT: ld 3, .LC146@toc@l(3) +; PC64LE9-NEXT: lfs 1, 4(3) +; PC64LE9-NEXT: lfs 2, 0(3) ; PC64LE9-NEXT: bl fmin ; PC64LE9-NEXT: nop -; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC147@toc@ha ; PC64LE9-NEXT: fmr 3, 1 -; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l +; PC64LE9-NEXT: ld 3, .LC147@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 16(3) ; PC64LE9-NEXT: xvmindp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -5736,41 +5815,32 @@ define <4 x double> @constrained_vector_minnum_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_minnum_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI94_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI94_2@toc@ha -; PC64LE-NEXT: addis 6, 2, .LCPI94_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PC64LE-NEXT: addi 4, 4, .LCPI94_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addi 3, 5, .LCPI94_2@toc@l -; PC64LE-NEXT: addi 4, 6, .LCPI94_3@toc@l -; PC64LE-NEXT: lxvd2x 2, 0, 3 -; PC64LE-NEXT: lxvd2x 3, 0, 4 +; PC64LE-NEXT: addis 3, 2, .LC148@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: li 5, 48 +; PC64LE-NEXT: ld 3, .LC148@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 +; PC64LE-NEXT: li 4, 32 +; PC64LE-NEXT: lxvd2x 1, 3, 5 +; PC64LE-NEXT: lxvd2x 2, 3, 4 +; PC64LE-NEXT: lxvd2x 3, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 2, 2 ; PC64LE-NEXT: xxswapd 3, 3 ; PC64LE-NEXT: xvmindp 34, 1, 0 -; PC64LE-NEXT: xvmindp 35, 3, 2 +; PC64LE-NEXT: xvmindp 35, 2, 3 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_minnum_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI94_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI94_2@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC148@toc@ha +; PC64LE9-NEXT: ld 3, .LC148@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) +; PC64LE9-NEXT: lxv 1, 48(3) ; PC64LE9-NEXT: xvmindp 34, 1, 0 ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI94_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI94_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 32(3) ; PC64LE9-NEXT: xvmindp 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5786,16 +5856,18 @@ define <1 x i32> @constrained_vector_fptosi_v1i32_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v1i32_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI95_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC149@toc@ha +; PC64LE-NEXT: ld 3, .LC149@toc@l(3) +; PC64LE-NEXT: lfsx 0, 0, 3 ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptosi_v1i32_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI95_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC149@toc@ha +; PC64LE9-NEXT: ld 3, .LC149@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: blr @@ -5809,10 +5881,10 @@ define <2 x i32> @constrained_vector_fptosi_v2i32_v2f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v2i32_v2f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI96_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI96_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI96_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC150@toc@ha +; PC64LE-NEXT: ld 3, .LC150@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 @@ -5824,13 +5896,13 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v2i32_v2f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI96_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC150@toc@ha +; PC64LE9-NEXT: ld 3, .LC150@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI96_1@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: mtvsrws 34, 4 ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 35, 3 @@ -5846,21 +5918,20 @@ define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI97_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI97_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI97_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI97_3@toc@ha -; PC64LE-NEXT: lfs 2, .LCPI97_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC151@toc@ha +; PC64LE-NEXT: ld 3, .LC151@toc@l(3) +; PC64LE-NEXT: lfs 0, 8(3) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: lfs 1, 4(3) ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: xscvdpsxws 2, 2 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mffprwz 4, 1 ; PC64LE-NEXT: mtvsrwz 34, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI97_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC152@toc@ha ; PC64LE-NEXT: mtvsrwz 35, 4 -; PC64LE-NEXT: addi 3, 3, .LCPI97_2@toc@l +; PC64LE-NEXT: ld 3, .LC152@toc@l(3) ; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 @@ -5870,23 +5941,22 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI97_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI97_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC151@toc@ha +; PC64LE9-NEXT: ld 3, .LC151@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: xscvdpsxws 0, 1 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 35, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI97_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI97_2@toc@l +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: mtvsrws 34, 4 +; PC64LE9-NEXT: xscvdpsxws 0, 0 +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: mtvsrws 35, 4 +; PC64LE9-NEXT: addis 4, 2, .LC152@toc@ha +; PC64LE9-NEXT: ld 4, .LC152@toc@l(4) ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI97_3@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI97_3@toc@l(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 +; PC64LE9-NEXT: lxvx 35, 0, 4 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -5902,16 +5972,16 @@ define <4 x i32> @constrained_vector_fptosi_v4i32_v4f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI98_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC153@toc@ha +; PC64LE-NEXT: ld 3, .LC153@toc@l(3) ; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xvcvspsxws 34, 34 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI98_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC153@toc@ha +; PC64LE9-NEXT: ld 3, .LC153@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvcvspsxws 34, 0 ; PC64LE9-NEXT: blr @@ -5926,16 +5996,18 @@ define <1 x i64> @constrained_vector_fptosi_v1i64_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v1i64_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI99_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC154@toc@ha +; PC64LE-NEXT: ld 3, .LC154@toc@l(3) +; PC64LE-NEXT: lfsx 0, 0, 3 ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptosi_v1i64_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI99_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC154@toc@ha +; PC64LE9-NEXT: ld 3, .LC154@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 ; PC64LE9-NEXT: blr @@ -5949,10 +6021,10 @@ define <2 x i64> @constrained_vector_fptosi_v2i64_v2f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v2i64_v2f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI100_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI100_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI100_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI100_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC155@toc@ha +; PC64LE-NEXT: ld 3, .LC155@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: mffprd 3, 0 @@ -5964,15 +6036,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI100_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI100_1@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI100_0@toc@l(3) -; PC64LE9-NEXT: xscvdpsxds 0, 0 -; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI100_1@toc@l(4) +; PC64LE9-NEXT: addis 3, 2, .LC155@toc@ha +; PC64LE9-NEXT: ld 3, .LC155@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: mtvsrdd 34, 4, 3 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: xscvdpsxds 0, 0 +; PC64LE9-NEXT: mffprd 3, 0 +; PC64LE9-NEXT: mtvsrdd 34, 3, 4 ; PC64LE9-NEXT: blr entry: %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32( @@ -5984,12 +6056,11 @@ define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI101_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI101_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI101_2@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI101_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI101_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI101_2@toc@l(5) +; PC64LE-NEXT: addis 3, 2, .LC156@toc@ha +; PC64LE-NEXT: ld 3, .LC156@toc@l(3) +; PC64LE-NEXT: lfs 0, 8(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 2, 2 @@ -6000,16 +6071,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v3i64_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI101_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI101_1@toc@ha -; PC64LE9-NEXT: addis 5, 2, .LCPI101_2@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI101_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC156@toc@ha +; PC64LE9-NEXT: ld 5, .LC156@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(5) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI101_1@toc@l(4) +; PC64LE9-NEXT: lfs 0, 4(5) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: lfs 0, .LCPI101_2@toc@l(5) +; PC64LE9-NEXT: lfs 0, 0(5) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 5, 0 ; PC64LE9-NEXT: blr @@ -6024,14 +6094,12 @@ define <4 x i64> @constrained_vector_fptosi_v4i64_v4f32() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI102_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI102_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI102_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI102_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI102_1@toc@l(4) -; PC64LE-NEXT: addis 4, 2, .LCPI102_3@toc@ha -; PC64LE-NEXT: lfs 2, .LCPI102_2@toc@l(3) -; PC64LE-NEXT: lfs 3, .LCPI102_3@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC157@toc@ha +; PC64LE-NEXT: ld 3, .LC157@toc@l(3) +; PC64LE-NEXT: lfs 0, 12(3) +; PC64LE-NEXT: lfsx 3, 0, 3 +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfs 2, 4(3) ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 2, 2 @@ -6050,24 +6118,22 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI102_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI102_1@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI102_0@toc@l(3) -; PC64LE9-NEXT: xscvdpsxds 0, 0 -; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI102_1@toc@l(4) +; PC64LE9-NEXT: addis 3, 2, .LC157@toc@ha +; PC64LE9-NEXT: ld 3, .LC157@toc@l(3) +; PC64LE9-NEXT: lfs 0, 12(3) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: mtvsrdd 34, 4, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI102_2@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI102_3@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI102_2@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(3) ; PC64LE9-NEXT: xscvdpsxds 0, 0 -; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI102_3@toc@l(4) +; PC64LE9-NEXT: mffprd 5, 0 +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: mtvsrdd 34, 5, 4 ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: mtvsrdd 35, 4, 3 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: xscvdpsxds 0, 0 +; PC64LE9-NEXT: mffprd 3, 0 +; PC64LE9-NEXT: mtvsrdd 35, 3, 4 ; PC64LE9-NEXT: blr entry: %result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f32( @@ -6080,16 +6146,18 @@ define <1 x i32> @constrained_vector_fptosi_v1i32_v1f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v1i32_v1f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI103_0@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI103_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC158@toc@ha +; PC64LE-NEXT: ld 3, .LC158@toc@l(3) +; PC64LE-NEXT: lfdx 0, 0, 3 ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptosi_v1i32_v1f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI103_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI103_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC158@toc@ha +; PC64LE9-NEXT: ld 3, .LC158@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: blr @@ -6104,10 +6172,10 @@ define <2 x i32> @constrained_vector_fptosi_v2i32_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v2i32_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI104_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI104_1@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI104_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI104_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC159@toc@ha +; PC64LE-NEXT: ld 3, .LC159@toc@l(3) +; PC64LE-NEXT: lfd 0, 8(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 @@ -6119,13 +6187,13 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v2i32_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI104_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI104_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC159@toc@ha +; PC64LE9-NEXT: ld 3, .LC159@toc@l(3) +; PC64LE9-NEXT: lfd 0, 8(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI104_1@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI104_1@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: mtvsrws 34, 4 ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 35, 3 @@ -6141,21 +6209,20 @@ define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI105_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI105_1@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI105_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI105_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI105_3@toc@ha -; PC64LE-NEXT: lfd 2, .LCPI105_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC160@toc@ha +; PC64LE-NEXT: ld 3, .LC160@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfdx 2, 0, 3 +; PC64LE-NEXT: lfd 1, 8(3) ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: xscvdpsxws 2, 2 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mffprwz 4, 1 ; PC64LE-NEXT: mtvsrwz 34, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI105_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC161@toc@ha ; PC64LE-NEXT: mtvsrwz 35, 4 -; PC64LE-NEXT: addi 3, 3, .LCPI105_2@toc@l +; PC64LE-NEXT: ld 3, .LC161@toc@l(3) ; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 @@ -6165,23 +6232,22 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI105_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI105_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC160@toc@ha +; PC64LE9-NEXT: ld 3, .LC160@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI105_1@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI105_1@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 8(3) +; PC64LE9-NEXT: mtvsrws 34, 4 ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 35, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI105_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI105_2@toc@l -; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI105_3@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI105_3@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: mtvsrws 35, 4 +; PC64LE9-NEXT: addis 4, 2, .LC161@toc@ha ; PC64LE9-NEXT: xscvdpsxws 0, 0 +; PC64LE9-NEXT: ld 4, .LC161@toc@l(4) +; PC64LE9-NEXT: vmrghw 2, 3, 2 +; PC64LE9-NEXT: lxvx 35, 0, 4 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -6197,14 +6263,12 @@ define <4 x i32> @constrained_vector_fptosi_v4i32_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI106_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI106_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI106_2@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI106_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI106_3@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI106_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI106_2@toc@l(5) -; PC64LE-NEXT: lfd 3, .LCPI106_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC162@toc@ha +; PC64LE-NEXT: ld 3, .LC162@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfd 1, 24(3) +; PC64LE-NEXT: lfdx 2, 0, 3 +; PC64LE-NEXT: lfd 3, 8(3) ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: xscvdpsxws 2, 2 @@ -6222,25 +6286,23 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI106_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI106_1@toc@ha -; PC64LE9-NEXT: addis 5, 2, .LCPI106_3@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI106_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC162@toc@ha +; PC64LE9-NEXT: ld 3, .LC162@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: lfd 0, .LCPI106_1@toc@l(4) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 24(3) +; PC64LE9-NEXT: xscvdpsxws 0, 0 +; PC64LE9-NEXT: mffprwz 5, 0 +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: rldimi 5, 4, 32, 0 ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: mffprwz 4, 0 -; PC64LE9-NEXT: rldimi 4, 3, 32, 0 -; PC64LE9-NEXT: addis 3, 2, .LCPI106_2@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI106_2@toc@l(3) +; PC64LE9-NEXT: lfd 0, 8(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: lfd 0, .LCPI106_3@toc@l(5) -; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 5, 0 -; PC64LE9-NEXT: rldimi 5, 3, 32, 0 -; PC64LE9-NEXT: mtvsrdd 34, 5, 4 +; PC64LE9-NEXT: rldimi 3, 4, 32, 0 +; PC64LE9-NEXT: mtvsrdd 34, 3, 5 ; PC64LE9-NEXT: blr entry: %result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f64( @@ -6253,16 +6315,18 @@ define <1 x i64> @constrained_vector_fptosi_v1i64_v1f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v1i64_v1f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI107_0@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI107_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC163@toc@ha +; PC64LE-NEXT: ld 3, .LC163@toc@l(3) +; PC64LE-NEXT: lfdx 0, 0, 3 ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptosi_v1i64_v1f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI107_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI107_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC163@toc@ha +; PC64LE9-NEXT: ld 3, .LC163@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 ; PC64LE9-NEXT: blr @@ -6276,8 +6340,8 @@ define <2 x i64> @constrained_vector_fptosi_v2i64_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v2i64_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI108_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI108_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC164@toc@ha +; PC64LE-NEXT: ld 3, .LC164@toc@l(3) ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xvcvdpsxds 34, 0 @@ -6285,8 +6349,8 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI108_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI108_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC164@toc@ha +; PC64LE9-NEXT: ld 3, .LC164@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: blr @@ -6300,12 +6364,11 @@ define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI109_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI109_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI109_2@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI109_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI109_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI109_2@toc@l(5) +; PC64LE-NEXT: addis 3, 2, .LC165@toc@ha +; PC64LE-NEXT: ld 3, .LC165@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfd 1, 8(3) +; PC64LE-NEXT: lfdx 2, 0, 3 ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 2, 2 @@ -6316,16 +6379,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fptosi_v3i64_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI109_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI109_1@toc@ha -; PC64LE9-NEXT: addis 5, 2, .LCPI109_2@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI109_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC165@toc@ha +; PC64LE9-NEXT: ld 5, .LC165@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(5) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfd 0, .LCPI109_1@toc@l(4) +; PC64LE9-NEXT: lfd 0, 8(5) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: lfd 0, .LCPI109_2@toc@l(5) +; PC64LE9-NEXT: lfd 0, 0(5) ; PC64LE9-NEXT: xscvdpsxds 0, 0 ; PC64LE9-NEXT: mffprd 5, 0 ; PC64LE9-NEXT: blr @@ -6340,27 +6402,24 @@ define <4 x i64> @constrained_vector_fptosi_v4i64_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI110_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI110_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI110_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI110_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC166@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC166@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvcvdpsxds 35, 0 -; PC64LE-NEXT: xvcvdpsxds 34, 1 +; PC64LE-NEXT: xvcvdpsxds 34, 0 +; PC64LE-NEXT: xvcvdpsxds 35, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI110_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI110_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC166@toc@ha +; PC64LE9-NEXT: ld 3, .LC166@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI110_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI110_1@toc@l ; PC64LE9-NEXT: xvcvdpsxds 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6374,16 +6433,18 @@ define <1 x i32> @constrained_vector_fptoui_v1i32_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v1i32_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI111_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI111_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC167@toc@ha +; PC64LE-NEXT: ld 3, .LC167@toc@l(3) +; PC64LE-NEXT: lfsx 0, 0, 3 ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptoui_v1i32_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI111_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI111_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC167@toc@ha +; PC64LE9-NEXT: ld 3, .LC167@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: blr @@ -6397,10 +6458,10 @@ define <2 x i32> @constrained_vector_fptoui_v2i32_v2f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v2i32_v2f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI112_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI112_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI112_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI112_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC168@toc@ha +; PC64LE-NEXT: ld 3, .LC168@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 @@ -6412,13 +6473,13 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v2i32_v2f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI112_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI112_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC168@toc@ha +; PC64LE9-NEXT: ld 3, .LC168@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI112_1@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI112_1@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: mtvsrws 34, 4 ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 35, 3 @@ -6434,21 +6495,20 @@ define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI113_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI113_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI113_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI113_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI113_3@toc@ha -; PC64LE-NEXT: lfs 2, .LCPI113_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC169@toc@ha +; PC64LE-NEXT: ld 3, .LC169@toc@l(3) +; PC64LE-NEXT: lfs 0, 8(3) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: lfs 1, 4(3) ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: xscvdpuxws 2, 2 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mffprwz 4, 1 ; PC64LE-NEXT: mtvsrwz 34, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI113_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC170@toc@ha ; PC64LE-NEXT: mtvsrwz 35, 4 -; PC64LE-NEXT: addi 3, 3, .LCPI113_2@toc@l +; PC64LE-NEXT: ld 3, .LC170@toc@l(3) ; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 @@ -6458,23 +6518,22 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI113_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI113_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI113_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI113_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC169@toc@ha +; PC64LE9-NEXT: ld 3, .LC169@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: xscvdpuxws 0, 1 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 35, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI113_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI113_2@toc@l +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: mtvsrws 34, 4 +; PC64LE9-NEXT: xscvdpuxws 0, 0 +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: mtvsrws 35, 4 +; PC64LE9-NEXT: addis 4, 2, .LC170@toc@ha +; PC64LE9-NEXT: ld 4, .LC170@toc@l(4) ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI113_3@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI113_3@toc@l(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 +; PC64LE9-NEXT: lxvx 35, 0, 4 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -6490,16 +6549,16 @@ define <4 x i32> @constrained_vector_fptoui_v4i32_v4f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI114_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI114_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC171@toc@ha +; PC64LE-NEXT: ld 3, .LC171@toc@l(3) ; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xvcvspuxws 34, 34 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI114_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI114_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC171@toc@ha +; PC64LE9-NEXT: ld 3, .LC171@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvcvspuxws 34, 0 ; PC64LE9-NEXT: blr @@ -6514,16 +6573,18 @@ define <1 x i64> @constrained_vector_fptoui_v1i64_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v1i64_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI115_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI115_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC172@toc@ha +; PC64LE-NEXT: ld 3, .LC172@toc@l(3) +; PC64LE-NEXT: lfsx 0, 0, 3 ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptoui_v1i64_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI115_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI115_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC172@toc@ha +; PC64LE9-NEXT: ld 3, .LC172@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 ; PC64LE9-NEXT: blr @@ -6537,10 +6598,10 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v2i64_v2f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI116_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI116_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI116_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI116_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC173@toc@ha +; PC64LE-NEXT: ld 3, .LC173@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: mffprd 3, 0 @@ -6552,15 +6613,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI116_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI116_1@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI116_0@toc@l(3) -; PC64LE9-NEXT: xscvdpuxds 0, 0 -; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI116_1@toc@l(4) +; PC64LE9-NEXT: addis 3, 2, .LC173@toc@ha +; PC64LE9-NEXT: ld 3, .LC173@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: mtvsrdd 34, 4, 3 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: xscvdpuxds 0, 0 +; PC64LE9-NEXT: mffprd 3, 0 +; PC64LE9-NEXT: mtvsrdd 34, 3, 4 ; PC64LE9-NEXT: blr entry: %result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32( @@ -6572,12 +6633,11 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI117_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI117_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI117_2@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI117_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI117_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI117_2@toc@l(5) +; PC64LE-NEXT: addis 3, 2, .LC174@toc@ha +; PC64LE-NEXT: ld 3, .LC174@toc@l(3) +; PC64LE-NEXT: lfs 0, 8(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 2, 0, 3 ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 2, 2 @@ -6588,16 +6648,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v3i64_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI117_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI117_1@toc@ha -; PC64LE9-NEXT: addis 5, 2, .LCPI117_2@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI117_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC174@toc@ha +; PC64LE9-NEXT: ld 5, .LC174@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(5) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI117_1@toc@l(4) +; PC64LE9-NEXT: lfs 0, 4(5) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: lfs 0, .LCPI117_2@toc@l(5) +; PC64LE9-NEXT: lfs 0, 0(5) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 5, 0 ; PC64LE9-NEXT: blr @@ -6612,14 +6671,12 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI118_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI118_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI118_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI118_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI118_1@toc@l(4) -; PC64LE-NEXT: addis 4, 2, .LCPI118_3@toc@ha -; PC64LE-NEXT: lfs 2, .LCPI118_2@toc@l(3) -; PC64LE-NEXT: lfs 3, .LCPI118_3@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC175@toc@ha +; PC64LE-NEXT: ld 3, .LC175@toc@l(3) +; PC64LE-NEXT: lfs 0, 12(3) +; PC64LE-NEXT: lfsx 3, 0, 3 +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfs 2, 4(3) ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 2, 2 @@ -6638,24 +6695,22 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI118_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI118_1@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI118_0@toc@l(3) -; PC64LE9-NEXT: xscvdpuxds 0, 0 -; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI118_1@toc@l(4) +; PC64LE9-NEXT: addis 3, 2, .LC175@toc@ha +; PC64LE9-NEXT: ld 3, .LC175@toc@l(3) +; PC64LE9-NEXT: lfs 0, 12(3) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: mtvsrdd 34, 4, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI118_2@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI118_3@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI118_2@toc@l(3) +; PC64LE9-NEXT: lfs 0, 8(3) ; PC64LE9-NEXT: xscvdpuxds 0, 0 -; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfs 0, .LCPI118_3@toc@l(4) +; PC64LE9-NEXT: mffprd 5, 0 +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: mtvsrdd 34, 5, 4 ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: mtvsrdd 35, 4, 3 +; PC64LE9-NEXT: lfs 0, 0(3) +; PC64LE9-NEXT: xscvdpuxds 0, 0 +; PC64LE9-NEXT: mffprd 3, 0 +; PC64LE9-NEXT: mtvsrdd 35, 3, 4 ; PC64LE9-NEXT: blr entry: %result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f32( @@ -6668,16 +6723,18 @@ define <1 x i32> @constrained_vector_fptoui_v1i32_v1f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v1i32_v1f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI119_0@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI119_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC176@toc@ha +; PC64LE-NEXT: ld 3, .LC176@toc@l(3) +; PC64LE-NEXT: lfdx 0, 0, 3 ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptoui_v1i32_v1f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI119_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI119_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC176@toc@ha +; PC64LE9-NEXT: ld 3, .LC176@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: blr @@ -6691,10 +6748,10 @@ define <2 x i32> @constrained_vector_fptoui_v2i32_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v2i32_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI120_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI120_1@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI120_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI120_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC177@toc@ha +; PC64LE-NEXT: ld 3, .LC177@toc@l(3) +; PC64LE-NEXT: lfd 0, 8(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 @@ -6706,13 +6763,13 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v2i32_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI120_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI120_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC177@toc@ha +; PC64LE9-NEXT: ld 3, .LC177@toc@l(3) +; PC64LE9-NEXT: lfd 0, 8(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI120_1@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI120_1@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: mtvsrws 34, 4 ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 35, 3 @@ -6728,21 +6785,20 @@ define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI121_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI121_1@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI121_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI121_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI121_3@toc@ha -; PC64LE-NEXT: lfd 2, .LCPI121_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC178@toc@ha +; PC64LE-NEXT: ld 3, .LC178@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfdx 2, 0, 3 +; PC64LE-NEXT: lfd 1, 8(3) ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: xscvdpuxws 2, 2 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mffprwz 4, 1 ; PC64LE-NEXT: mtvsrwz 34, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI121_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC179@toc@ha ; PC64LE-NEXT: mtvsrwz 35, 4 -; PC64LE-NEXT: addi 3, 3, .LCPI121_2@toc@l +; PC64LE-NEXT: ld 3, .LC179@toc@l(3) ; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: lvx 3, 0, 3 @@ -6752,23 +6808,22 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI121_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI121_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC178@toc@ha +; PC64LE9-NEXT: ld 3, .LC178@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 34, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI121_1@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI121_1@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 8(3) +; PC64LE9-NEXT: mtvsrws 34, 4 ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrws 35, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI121_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI121_2@toc@l -; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI121_3@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI121_3@toc@l(3) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: mtvsrws 35, 4 +; PC64LE9-NEXT: addis 4, 2, .LC179@toc@ha ; PC64LE9-NEXT: xscvdpuxws 0, 0 +; PC64LE9-NEXT: ld 4, .LC179@toc@l(4) +; PC64LE9-NEXT: vmrghw 2, 3, 2 +; PC64LE9-NEXT: lxvx 35, 0, 4 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -6784,14 +6839,12 @@ define <4 x i32> @constrained_vector_fptoui_v4i32_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI122_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI122_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI122_2@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI122_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI122_3@toc@ha -; PC64LE-NEXT: lfd 1, .LCPI122_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI122_2@toc@l(5) -; PC64LE-NEXT: lfd 3, .LCPI122_3@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC180@toc@ha +; PC64LE-NEXT: ld 3, .LC180@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfd 1, 24(3) +; PC64LE-NEXT: lfdx 2, 0, 3 +; PC64LE-NEXT: lfd 3, 8(3) ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: xscvdpuxws 2, 2 @@ -6809,25 +6862,23 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI122_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI122_1@toc@ha -; PC64LE9-NEXT: addis 5, 2, .LCPI122_3@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI122_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC180@toc@ha +; PC64LE9-NEXT: ld 3, .LC180@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: lfd 0, .LCPI122_1@toc@l(4) +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: lfd 0, 24(3) +; PC64LE9-NEXT: xscvdpuxws 0, 0 +; PC64LE9-NEXT: mffprwz 5, 0 +; PC64LE9-NEXT: lfd 0, 0(3) +; PC64LE9-NEXT: rldimi 5, 4, 32, 0 ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: mffprwz 4, 0 -; PC64LE9-NEXT: rldimi 4, 3, 32, 0 -; PC64LE9-NEXT: addis 3, 2, .LCPI122_2@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI122_2@toc@l(3) +; PC64LE9-NEXT: lfd 0, 8(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: lfd 0, .LCPI122_3@toc@l(5) -; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 5, 0 -; PC64LE9-NEXT: rldimi 5, 3, 32, 0 -; PC64LE9-NEXT: mtvsrdd 34, 5, 4 +; PC64LE9-NEXT: rldimi 3, 4, 32, 0 +; PC64LE9-NEXT: mtvsrdd 34, 3, 5 ; PC64LE9-NEXT: blr entry: %result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f64( @@ -6840,16 +6891,18 @@ define <1 x i64> @constrained_vector_fptoui_v1i64_v1f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v1i64_v1f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI123_0@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI123_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC181@toc@ha +; PC64LE-NEXT: ld 3, .LC181@toc@l(3) +; PC64LE-NEXT: lfdx 0, 0, 3 ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptoui_v1i64_v1f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI123_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI123_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC181@toc@ha +; PC64LE9-NEXT: ld 3, .LC181@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 ; PC64LE9-NEXT: blr @@ -6863,8 +6916,8 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v2i64_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI124_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI124_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC182@toc@ha +; PC64LE-NEXT: ld 3, .LC182@toc@l(3) ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xvcvdpuxds 34, 0 @@ -6872,8 +6925,8 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI124_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI124_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC182@toc@ha +; PC64LE9-NEXT: ld 3, .LC182@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: blr @@ -6887,12 +6940,11 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI125_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI125_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI125_2@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI125_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI125_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI125_2@toc@l(5) +; PC64LE-NEXT: addis 3, 2, .LC183@toc@ha +; PC64LE-NEXT: ld 3, .LC183@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfd 1, 8(3) +; PC64LE-NEXT: lfdx 2, 0, 3 ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 2, 2 @@ -6903,16 +6955,15 @@ ; ; PC64LE9-LABEL: constrained_vector_fptoui_v3i64_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI125_0@toc@ha -; PC64LE9-NEXT: addis 4, 2, .LCPI125_1@toc@ha -; PC64LE9-NEXT: addis 5, 2, .LCPI125_2@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI125_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC183@toc@ha +; PC64LE9-NEXT: ld 5, .LC183@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(5) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 3, 0 -; PC64LE9-NEXT: lfd 0, .LCPI125_1@toc@l(4) +; PC64LE9-NEXT: lfd 0, 8(5) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 4, 0 -; PC64LE9-NEXT: lfd 0, .LCPI125_2@toc@l(5) +; PC64LE9-NEXT: lfd 0, 0(5) ; PC64LE9-NEXT: xscvdpuxds 0, 0 ; PC64LE9-NEXT: mffprd 5, 0 ; PC64LE9-NEXT: blr @@ -6927,27 +6978,24 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI126_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI126_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI126_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI126_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC184@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC184@toc@l(3) +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: lxvd2x 1, 0, 3 ; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 1, 1 -; PC64LE-NEXT: xvcvdpuxds 35, 0 -; PC64LE-NEXT: xvcvdpuxds 34, 1 +; PC64LE-NEXT: xvcvdpuxds 34, 0 +; PC64LE-NEXT: xvcvdpuxds 35, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI126_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI126_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC184@toc@ha +; PC64LE9-NEXT: ld 3, .LC184@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI126_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI126_1@toc@l ; PC64LE9-NEXT: xvcvdpuxds 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6961,15 +7009,17 @@ define <1 x float> @constrained_vector_fptrunc_v1f64() #0 { ; PC64LE-LABEL: constrained_vector_fptrunc_v1f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI127_0@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI127_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC185@toc@ha +; PC64LE-NEXT: ld 3, .LC185@toc@l(3) +; PC64LE-NEXT: lfdx 0, 0, 3 ; PC64LE-NEXT: xsrsp 1, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI127_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI127_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC185@toc@ha +; PC64LE9-NEXT: ld 3, .LC185@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: xsrsp 1, 0 ; PC64LE9-NEXT: blr entry: @@ -6983,10 +7033,10 @@ define <2 x float> @constrained_vector_fptrunc_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_fptrunc_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI128_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI128_1@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI128_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI128_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC186@toc@ha +; PC64LE-NEXT: ld 3, .LC186@toc@l(3) +; PC64LE-NEXT: lfd 0, 8(3) +; PC64LE-NEXT: lfdx 1, 0, 3 ; PC64LE-NEXT: xsrsp 0, 0 ; PC64LE-NEXT: xsrsp 1, 1 ; PC64LE-NEXT: xscvdpspn 0, 0 @@ -6998,13 +7048,13 @@ ; ; PC64LE9-LABEL: constrained_vector_fptrunc_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI128_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI128_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI128_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC186@toc@ha +; PC64LE9-NEXT: ld 3, .LC186@toc@l(3) +; PC64LE9-NEXT: lfd 0, 8(3) ; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE9-NEXT: lfd 0, .LCPI128_1@toc@l(3) +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -7021,16 +7071,15 @@ define <3 x float> @constrained_vector_fptrunc_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI129_1@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI129_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI129_1@toc@l(4) -; PC64LE-NEXT: addis 3, 2, .LCPI129_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC187@toc@ha +; PC64LE-NEXT: ld 3, .LC187@toc@l(3) +; PC64LE-NEXT: lfd 0, 16(3) +; PC64LE-NEXT: lfdx 2, 0, 3 +; PC64LE-NEXT: lfd 1, 8(3) +; PC64LE-NEXT: addis 3, 2, .LC188@toc@ha +; PC64LE-NEXT: ld 3, .LC188@toc@l(3) ; PC64LE-NEXT: xsrsp 0, 0 -; PC64LE-NEXT: lfd 2, .LCPI129_3@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI129_2@toc@ha ; PC64LE-NEXT: xsrsp 1, 1 -; PC64LE-NEXT: addi 3, 3, .LCPI129_2@toc@l ; PC64LE-NEXT: xsrsp 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -7045,22 +7094,21 @@ ; ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI129_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI129_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI129_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC187@toc@ha +; PC64LE9-NEXT: addis 4, 2, .LC188@toc@ha +; PC64LE9-NEXT: ld 3, .LC187@toc@l(3) +; PC64LE9-NEXT: ld 4, .LC188@toc@l(4) +; PC64LE9-NEXT: lfd 0, 16(3) ; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 -; PC64LE9-NEXT: lfd 0, .LCPI129_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI129_2@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI129_2@toc@l +; PC64LE9-NEXT: lfd 0, 8(3) ; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 +; PC64LE9-NEXT: lfd 0, 0(3) ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI129_3@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI129_3@toc@l(3) +; PC64LE9-NEXT: lxvx 35, 0, 4 ; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 @@ -7078,14 +7126,12 @@ define <4 x float> @constrained_vector_fptrunc_v4f64() #0 { ; PC64LE-LABEL: constrained_vector_fptrunc_v4f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI130_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI130_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI130_2@toc@ha -; PC64LE-NEXT: addis 6, 2, .LCPI130_3@toc@ha -; PC64LE-NEXT: lfd 0, .LCPI130_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI130_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI130_2@toc@l(5) -; PC64LE-NEXT: lfd 3, .LCPI130_3@toc@l(6) +; PC64LE-NEXT: addis 3, 2, .LC189@toc@ha +; PC64LE-NEXT: ld 3, .LC189@toc@l(3) +; PC64LE-NEXT: lfd 0, 24(3) +; PC64LE-NEXT: lfd 1, 8(3) +; PC64LE-NEXT: lfd 2, 16(3) +; PC64LE-NEXT: lfdx 3, 0, 3 ; PC64LE-NEXT: xxmrghd 0, 1, 0 ; PC64LE-NEXT: xxmrghd 1, 3, 2 ; PC64LE-NEXT: xvcvdpsp 34, 0 @@ -7095,16 +7141,14 @@ ; ; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI130_0@toc@ha -; PC64LE9-NEXT: lfd 0, .LCPI130_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI130_1@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI130_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI130_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC189@toc@ha +; PC64LE9-NEXT: ld 3, .LC189@toc@l(3) +; PC64LE9-NEXT: lfd 0, 24(3) +; PC64LE9-NEXT: lfd 1, 8(3) ; PC64LE9-NEXT: xxmrghd 0, 1, 0 +; PC64LE9-NEXT: lfd 1, 0(3) ; PC64LE9-NEXT: xvcvdpsp 34, 0 -; PC64LE9-NEXT: lfd 0, .LCPI130_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI130_3@toc@ha -; PC64LE9-NEXT: lfd 1, .LCPI130_3@toc@l(3) +; PC64LE9-NEXT: lfd 0, 16(3) ; PC64LE9-NEXT: xxmrghd 0, 1, 0 ; PC64LE9-NEXT: xvcvdpsp 35, 0 ; PC64LE9-NEXT: vmrgew 2, 3, 2 @@ -7121,14 +7165,16 @@ define <1 x double> @constrained_vector_fpext_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_fpext_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI131_0@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI131_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC190@toc@ha +; PC64LE-NEXT: ld 3, .LC190@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fpext_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI131_0@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI131_0@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC190@toc@ha +; PC64LE9-NEXT: ld 3, .LC190@toc@l(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: blr entry: %result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32( @@ -7140,19 +7186,19 @@ define <2 x double> @constrained_vector_fpext_v2f32() #0 { ; PC64LE-LABEL: constrained_vector_fpext_v2f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI132_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI132_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI132_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI132_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LC191@toc@ha +; PC64LE-NEXT: ld 3, .LC191@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fpext_v2f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI132_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI132_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI132_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI132_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC191@toc@ha +; PC64LE9-NEXT: ld 3, .LC191@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -7165,22 +7211,20 @@ define <3 x double> @constrained_vector_fpext_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_fpext_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI133_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI133_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI133_2@toc@ha -; PC64LE-NEXT: lfs 3, .LCPI133_0@toc@l(3) -; PC64LE-NEXT: lfs 2, .LCPI133_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI133_2@toc@l(5) +; PC64LE-NEXT: addis 3, 2, .LC192@toc@ha +; PC64LE-NEXT: ld 3, .LC192@toc@l(3) +; PC64LE-NEXT: lfs 2, 4(3) +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfsx 3, 0, 3 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fpext_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI133_0@toc@ha -; PC64LE9-NEXT: lfs 3, .LCPI133_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI133_1@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI133_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI133_2@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI133_2@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC192@toc@ha +; PC64LE9-NEXT: ld 3, .LC192@toc@l(3) +; PC64LE9-NEXT: lfs 3, 0(3) +; PC64LE9-NEXT: lfs 2, 4(3) +; PC64LE9-NEXT: lfs 1, 8(3) ; PC64LE9-NEXT: blr entry: %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32( @@ -7193,29 +7237,25 @@ define <4 x double> @constrained_vector_fpext_v4f32() #0 { ; PC64LE-LABEL: constrained_vector_fpext_v4f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI134_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI134_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI134_2@toc@ha -; PC64LE-NEXT: addis 6, 2, .LCPI134_3@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI134_0@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI134_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI134_2@toc@l(5) -; PC64LE-NEXT: lfs 3, .LCPI134_3@toc@l(6) +; PC64LE-NEXT: addis 3, 2, .LC193@toc@ha +; PC64LE-NEXT: ld 3, .LC193@toc@l(3) +; PC64LE-NEXT: lfs 0, 12(3) +; PC64LE-NEXT: lfs 1, 8(3) +; PC64LE-NEXT: lfs 2, 4(3) +; PC64LE-NEXT: lfsx 3, 0, 3 ; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: xxmrghd 35, 3, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fpext_v4f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI134_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI134_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI134_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI134_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI134_2@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC193@toc@ha +; PC64LE9-NEXT: ld 3, .LC193@toc@l(3) +; PC64LE9-NEXT: lfs 0, 12(3) +; PC64LE9-NEXT: lfs 1, 8(3) ; PC64LE9-NEXT: xxmrghd 34, 1, 0 -; PC64LE9-NEXT: lfs 0, .LCPI134_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI134_3@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI134_3@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: xxmrghd 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -7229,19 +7269,19 @@ define <1 x float> @constrained_vector_ceil_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_ceil_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI135_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI135_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI135_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI135_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC194@toc@ha +; PC64LE-NEXT: ld 3, .LC194@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xsrdpip 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_ceil_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI135_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI135_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI135_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI135_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC194@toc@ha +; PC64LE9-NEXT: ld 3, .LC194@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7254,23 +7294,20 @@ define <2 x double> @constrained_vector_ceil_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_ceil_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI136_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI136_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI136_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC195@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC195@toc@l(3) ; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: xvrdpip 0, 0 +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: xxswapd 34, 1 +; PC64LE-NEXT: xvrdpip 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_ceil_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI136_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI136_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI136_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC195@toc@ha +; PC64LE9-NEXT: ld 3, .LC195@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xvrdpip 0, 0 ; PC64LE9-NEXT: blr @@ -7284,32 +7321,30 @@ define <3 x float> @constrained_vector_ceil_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_ceil_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI137_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI137_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI137_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI137_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI137_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI137_2@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI137_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI137_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC196@toc@ha +; PC64LE-NEXT: ld 3, .LC196@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 0, 0, 3 +; PC64LE-NEXT: lfs 2, 8(3) +; PC64LE-NEXT: addis 3, 2, .LC197@toc@ha +; PC64LE-NEXT: ld 3, .LC197@toc@l(3) ; PC64LE-NEXT: xsrdpip 0, 0 -; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpip 0, 1 +; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpip 0, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_ceil_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI137_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI137_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI137_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC196@toc@ha +; PC64LE9-NEXT: ld 3, .LC196@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xsrdpip 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI137_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI137_2@toc@ha +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xsrdpip 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI137_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI137_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI137_3@toc@l +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: addis 3, 2, .LC197@toc@ha +; PC64LE9-NEXT: ld 3, .LC197@toc@l(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: blr @@ -7323,32 +7358,32 @@ define <3 x double> @constrained_vector_ceil_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_ceil_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI138_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI138_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI138_0@toc@l(3) -; PC64LE-NEXT: addi 3, 4, .LCPI138_1@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI138_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC198@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC199@toc@ha +; PC64LE-NEXT: ld 3, .LC198@toc@l(3) +; PC64LE-NEXT: ld 4, .LC199@toc@l(4) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lxvd2x 1, 0, 4 ; PC64LE-NEXT: xsrdpip 0, 0 ; PC64LE-NEXT: xvrdpip 0, 1 -; PC64LE-NEXT: lfs 1, .LCPI138_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: fmr 2, 1 ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_ceil_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI138_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI138_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI138_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI138_1@toc@l -; PC64LE9-NEXT: xsrdpip 0, 0 +; PC64LE9-NEXT: addis 3, 2, .LC198@toc@ha +; PC64LE9-NEXT: ld 3, .LC198@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI138_2@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI138_2@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC199@toc@ha +; PC64LE9-NEXT: ld 3, .LC199@toc@l(3) ; PC64LE9-NEXT: xvrdpip 0, 0 +; PC64LE9-NEXT: lfs 1, 0(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: fmr 2, 1 ; PC64LE9-NEXT: fmr 3, 1 +; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: blr entry: %ceil = call <3 x double> @llvm.experimental.constrained.ceil.v3f64( @@ -7360,19 +7395,19 @@ define <1 x float> @constrained_vector_floor_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_floor_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI139_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI139_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI139_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI139_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC200@toc@ha +; PC64LE-NEXT: ld 3, .LC200@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xsrdpim 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_floor_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI139_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI139_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI139_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI139_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC200@toc@ha +; PC64LE9-NEXT: ld 3, .LC200@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7386,23 +7421,20 @@ define <2 x double> @constrained_vector_floor_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_floor_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI140_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI140_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI140_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC201@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC201@toc@l(3) ; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: xvrdpim 0, 0 +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: xxswapd 34, 1 +; PC64LE-NEXT: xvrdpim 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_floor_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI140_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI140_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI140_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC201@toc@ha +; PC64LE9-NEXT: ld 3, .LC201@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xvrdpim 0, 0 ; PC64LE9-NEXT: blr @@ -7416,32 +7448,30 @@ define <3 x float> @constrained_vector_floor_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_floor_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI141_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI141_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI141_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI141_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI141_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI141_2@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI141_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI141_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC202@toc@ha +; PC64LE-NEXT: ld 3, .LC202@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 0, 0, 3 +; PC64LE-NEXT: lfs 2, 8(3) +; PC64LE-NEXT: addis 3, 2, .LC203@toc@ha +; PC64LE-NEXT: ld 3, .LC203@toc@l(3) ; PC64LE-NEXT: xsrdpim 0, 0 -; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpim 0, 1 +; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpim 0, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_floor_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI141_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI141_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI141_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC202@toc@ha +; PC64LE9-NEXT: ld 3, .LC202@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xsrdpim 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI141_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI141_2@toc@ha +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xsrdpim 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI141_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI141_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI141_3@toc@l +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: addis 3, 2, .LC203@toc@ha +; PC64LE9-NEXT: ld 3, .LC203@toc@l(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: blr @@ -7455,32 +7485,32 @@ define <3 x double> @constrained_vector_floor_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_floor_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI142_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI142_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI142_0@toc@l(3) -; PC64LE-NEXT: addi 3, 4, .LCPI142_1@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI142_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC204@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC205@toc@ha +; PC64LE-NEXT: ld 3, .LC204@toc@l(3) +; PC64LE-NEXT: ld 4, .LC205@toc@l(4) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lxvd2x 1, 0, 4 ; PC64LE-NEXT: xsrdpim 0, 0 ; PC64LE-NEXT: xvrdpim 0, 1 -; PC64LE-NEXT: lfs 1, .LCPI142_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: fmr 2, 1 ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_floor_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI142_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI142_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI142_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI142_1@toc@l -; PC64LE9-NEXT: xsrdpim 0, 0 +; PC64LE9-NEXT: addis 3, 2, .LC204@toc@ha +; PC64LE9-NEXT: ld 3, .LC204@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI142_2@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI142_2@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC205@toc@ha +; PC64LE9-NEXT: ld 3, .LC205@toc@l(3) ; PC64LE9-NEXT: xvrdpim 0, 0 +; PC64LE9-NEXT: lfs 1, 0(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: fmr 2, 1 ; PC64LE9-NEXT: fmr 3, 1 +; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: blr entry: %floor = call <3 x double> @llvm.experimental.constrained.floor.v3f64( @@ -7492,19 +7522,19 @@ define <1 x float> @constrained_vector_round_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_round_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI143_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI143_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI143_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI143_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC206@toc@ha +; PC64LE-NEXT: ld 3, .LC206@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xsrdpi 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_round_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI143_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI143_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI143_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI143_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC206@toc@ha +; PC64LE9-NEXT: ld 3, .LC206@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7517,23 +7547,20 @@ define <2 x double> @constrained_vector_round_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_round_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI144_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI144_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI144_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC207@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC207@toc@l(3) ; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: xvrdpi 0, 0 +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: xxswapd 34, 1 +; PC64LE-NEXT: xvrdpi 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_round_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI144_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI144_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI144_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC207@toc@ha +; PC64LE9-NEXT: ld 3, .LC207@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xvrdpi 0, 0 ; PC64LE9-NEXT: blr @@ -7547,32 +7574,30 @@ define <3 x float> @constrained_vector_round_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_round_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI145_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI145_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI145_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI145_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI145_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI145_2@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI145_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI145_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC208@toc@ha +; PC64LE-NEXT: ld 3, .LC208@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 0, 0, 3 +; PC64LE-NEXT: lfs 2, 8(3) +; PC64LE-NEXT: addis 3, 2, .LC209@toc@ha +; PC64LE-NEXT: ld 3, .LC209@toc@l(3) ; PC64LE-NEXT: xsrdpi 0, 0 -; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpi 0, 1 +; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpi 0, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_round_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI145_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI145_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI145_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC208@toc@ha +; PC64LE9-NEXT: ld 3, .LC208@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xsrdpi 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI145_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI145_2@toc@ha +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xsrdpi 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI145_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI145_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI145_3@toc@l +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: addis 3, 2, .LC209@toc@ha +; PC64LE9-NEXT: ld 3, .LC209@toc@l(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: blr @@ -7587,34 +7612,32 @@ define <3 x double> @constrained_vector_round_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_round_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 4, 2, .LCPI146_1@toc@ha -; PC64LE-NEXT: addis 3, 2, .LCPI146_0@toc@ha -; PC64LE-NEXT: addi 4, 4, .LCPI146_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC210@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC211@toc@ha +; PC64LE-NEXT: ld 3, .LC210@toc@l(3) +; PC64LE-NEXT: ld 4, .LC211@toc@l(4) +; PC64LE-NEXT: lfsx 2, 0, 3 +; PC64LE-NEXT: lfs 0, 8(3) ; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addis 4, 2, .LCPI146_3@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI146_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI146_2@toc@ha -; PC64LE-NEXT: lfs 2, .LCPI146_3@toc@l(4) +; PC64LE-NEXT: fmr 3, 2 ; PC64LE-NEXT: xsrdpi 0, 0 ; PC64LE-NEXT: xvrdpi 0, 1 -; PC64LE-NEXT: lfs 1, .LCPI146_2@toc@l(3) -; PC64LE-NEXT: fmr 3, 2 +; PC64LE-NEXT: lfs 1, 4(3) ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_round_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI146_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI146_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI146_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI146_1@toc@l -; PC64LE9-NEXT: xsrdpi 0, 0 +; PC64LE9-NEXT: addis 3, 2, .LC210@toc@ha +; PC64LE9-NEXT: ld 3, .LC210@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI146_2@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI146_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI146_3@toc@ha -; PC64LE9-NEXT: lfs 2, .LCPI146_3@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC211@toc@ha +; PC64LE9-NEXT: ld 3, .LC211@toc@l(3) ; PC64LE9-NEXT: xvrdpi 0, 0 +; PC64LE9-NEXT: lfs 2, 0(3) +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: lfs 1, 4(3) ; PC64LE9-NEXT: fmr 3, 2 +; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: blr entry: %round = call <3 x double> @llvm.experimental.constrained.round.v3f64( @@ -7626,19 +7649,19 @@ define <1 x float> @constrained_vector_trunc_v1f32() #0 { ; PC64LE-LABEL: constrained_vector_trunc_v1f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI147_0@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI147_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI147_1@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI147_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LC212@toc@ha +; PC64LE-NEXT: ld 3, .LC212@toc@l(3) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: xsrdpiz 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_trunc_v1f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI147_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI147_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI147_1@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI147_1@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC212@toc@ha +; PC64LE9-NEXT: ld 3, .LC212@toc@l(3) +; PC64LE9-NEXT: lfs 0, 4(3) +; PC64LE9-NEXT: lfs 1, 0(3) ; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7651,23 +7674,20 @@ define <2 x double> @constrained_vector_trunc_v2f64() #0 { ; PC64LE-LABEL: constrained_vector_trunc_v2f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI148_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI148_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: addi 3, 4, .LCPI148_1@toc@l +; PC64LE-NEXT: addis 3, 2, .LC213@toc@ha +; PC64LE-NEXT: li 4, 16 +; PC64LE-NEXT: ld 3, .LC213@toc@l(3) ; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: xvrdpiz 0, 0 +; PC64LE-NEXT: lxvd2x 0, 3, 4 ; PC64LE-NEXT: xxswapd 34, 1 +; PC64LE-NEXT: xvrdpiz 0, 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_trunc_v2f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI148_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI148_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI148_1@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC213@toc@ha +; PC64LE9-NEXT: ld 3, .LC213@toc@l(3) +; PC64LE9-NEXT: lxv 0, 16(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xvrdpiz 0, 0 ; PC64LE9-NEXT: blr @@ -7681,32 +7701,30 @@ define <3 x float> @constrained_vector_trunc_v3f32() #0 { ; PC64LE-LABEL: constrained_vector_trunc_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI149_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI149_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI149_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI149_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI149_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI149_2@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI149_3@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI149_3@toc@l +; PC64LE-NEXT: addis 3, 2, .LC214@toc@ha +; PC64LE-NEXT: ld 3, .LC214@toc@l(3) +; PC64LE-NEXT: lfs 1, 4(3) +; PC64LE-NEXT: lfsx 0, 0, 3 +; PC64LE-NEXT: lfs 2, 8(3) +; PC64LE-NEXT: addis 3, 2, .LC215@toc@ha +; PC64LE-NEXT: ld 3, .LC215@toc@l(3) ; PC64LE-NEXT: xsrdpiz 0, 0 -; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpiz 0, 1 +; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: xsrdpiz 0, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_trunc_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI149_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI149_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI149_1@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC214@toc@ha +; PC64LE9-NEXT: ld 3, .LC214@toc@l(3) +; PC64LE9-NEXT: lfs 0, 0(3) ; PC64LE9-NEXT: xsrdpiz 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI149_1@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI149_2@toc@ha +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: xsrdpiz 0, 0 -; PC64LE9-NEXT: lfs 0, .LCPI149_2@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI149_3@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI149_3@toc@l +; PC64LE9-NEXT: lfs 0, 8(3) +; PC64LE9-NEXT: addis 3, 2, .LC215@toc@ha +; PC64LE9-NEXT: ld 3, .LC215@toc@l(3) ; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: blr @@ -7720,32 +7738,32 @@ define <3 x double> @constrained_vector_trunc_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_trunc_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI150_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI150_1@toc@ha -; PC64LE-NEXT: lfs 0, .LCPI150_0@toc@l(3) -; PC64LE-NEXT: addi 3, 4, .LCPI150_1@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI150_2@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC216@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC217@toc@ha +; PC64LE-NEXT: ld 3, .LC216@toc@l(3) +; PC64LE-NEXT: ld 4, .LC217@toc@l(4) +; PC64LE-NEXT: lfs 0, 4(3) +; PC64LE-NEXT: lxvd2x 1, 0, 4 ; PC64LE-NEXT: xsrdpiz 0, 0 ; PC64LE-NEXT: xvrdpiz 0, 1 -; PC64LE-NEXT: lfs 1, .LCPI150_2@toc@l(3) +; PC64LE-NEXT: lfsx 1, 0, 3 ; PC64LE-NEXT: fmr 2, 1 ; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_trunc_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI150_0@toc@ha -; PC64LE9-NEXT: lfs 0, .LCPI150_0@toc@l(3) -; PC64LE9-NEXT: addis 3, 2, .LCPI150_1@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI150_1@toc@l -; PC64LE9-NEXT: xsrdpiz 0, 0 +; PC64LE9-NEXT: addis 3, 2, .LC216@toc@ha +; PC64LE9-NEXT: ld 3, .LC216@toc@l(3) ; PC64LE9-NEXT: lxvx 0, 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI150_2@toc@ha -; PC64LE9-NEXT: lfs 1, .LCPI150_2@toc@l(3) +; PC64LE9-NEXT: addis 3, 2, .LC217@toc@ha +; PC64LE9-NEXT: ld 3, .LC217@toc@l(3) ; PC64LE9-NEXT: xvrdpiz 0, 0 +; PC64LE9-NEXT: lfs 1, 0(3) +; PC64LE9-NEXT: lfs 0, 4(3) ; PC64LE9-NEXT: fmr 2, 1 ; PC64LE9-NEXT: fmr 3, 1 +; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: blr entry: %trunc = call <3 x double> @llvm.experimental.constrained.trunc.v3f64( @@ -7837,13 +7855,13 @@ define <2 x double> @constrained_vector_sitofp_v2f64_v2i16(<2 x i16> %x) #0 { ; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i16: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI155_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI155_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC218@toc@ha +; PC64LE-NEXT: addis 4, 2, .LC219@toc@ha +; PC64LE-NEXT: ld 3, .LC218@toc@l(3) ; PC64LE-NEXT: lvx 3, 0, 3 -; PC64LE-NEXT: addis 3, 2, .LCPI155_1@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI155_1@toc@l -; PC64LE-NEXT: lxvd2x 0, 0, 3 +; PC64LE-NEXT: ld 3, .LC219@toc@l(4) ; PC64LE-NEXT: vperm 2, 2, 2, 3 +; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 35, 0 ; PC64LE-NEXT: vsld 2, 2, 3 ; PC64LE-NEXT: vsrad 2, 2, 3 @@ -7852,8 +7870,8 @@ ; ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI155_0@toc@ha -; PC64LE9-NEXT: addi 3, 3, .LCPI155_0@toc@l +; PC64LE9-NEXT: addis 3, 2, .LC218@toc@ha +; PC64LE9-NEXT: ld 3, .LC218@toc@l(3) ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: vperm 2, 2, 2, 3 ; PC64LE9-NEXT: vextsh2d 2, 2 @@ -8043,8 +8061,8 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: xxswapd 0, 34 ; PC64LE-NEXT: xxsldwi 1, 34, 34, 1 -; PC64LE-NEXT: addis 3, 2, .LCPI161_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI161_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC220@toc@ha +; PC64LE-NEXT: ld 3, .LC220@toc@l(3) ; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mtfprwa 0, 4 @@ -8076,9 +8094,9 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: mtfprwa 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI161_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC219@toc@ha ; PC64LE9-NEXT: xscvsxdsp 0, 0 -; PC64LE9-NEXT: addi 3, 3, .LCPI161_0@toc@l +; PC64LE9-NEXT: ld 3, .LC219@toc@l(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3 @@ -8130,9 +8148,9 @@ ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mtfprd 0, 3 -; PC64LE-NEXT: addis 6, 2, .LCPI163_0@toc@ha +; PC64LE-NEXT: addis 6, 2, .LC221@toc@ha ; PC64LE-NEXT: mtfprd 1, 4 -; PC64LE-NEXT: addi 3, 6, .LCPI163_0@toc@l +; PC64LE-NEXT: ld 3, .LC221@toc@l(6) ; PC64LE-NEXT: xscvsxdsp 0, 0 ; PC64LE-NEXT: xscvsxdsp 1, 1 ; PC64LE-NEXT: mtfprd 2, 5 @@ -8151,9 +8169,9 @@ ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mtfprd 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI163_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC220@toc@ha ; PC64LE9-NEXT: xscvsxdsp 0, 0 -; PC64LE9-NEXT: addi 3, 3, .LCPI163_0@toc@l +; PC64LE9-NEXT: ld 3, .LC220@toc@l(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: mtfprd 0, 4 @@ -8425,9 +8443,9 @@ define <2 x double> @constrained_vector_uitofp_v2f64_v2i16(<2 x i16> %x) #0 { ; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i16: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 3, 2, .LCPI173_0@toc@ha +; PC64LE-NEXT: addis 3, 2, .LC222@toc@ha ; PC64LE-NEXT: xxlxor 36, 36, 36 -; PC64LE-NEXT: addi 3, 3, .LCPI173_0@toc@l +; PC64LE-NEXT: ld 3, .LC222@toc@l(3) ; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: xvcvuxddp 34, 34 @@ -8435,9 +8453,9 @@ ; ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC221@toc@ha ; PC64LE9-NEXT: xxlxor 36, 36, 36 -; PC64LE9-NEXT: addi 3, 3, .LCPI173_0@toc@l +; PC64LE9-NEXT: ld 3, .LC221@toc@l(3) ; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: xvcvuxddp 34, 34 @@ -8626,8 +8644,8 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: xxswapd 0, 34 ; PC64LE-NEXT: xxsldwi 1, 34, 34, 1 -; PC64LE-NEXT: addis 3, 2, .LCPI179_0@toc@ha -; PC64LE-NEXT: addi 3, 3, .LCPI179_0@toc@l +; PC64LE-NEXT: addis 3, 2, .LC223@toc@ha +; PC64LE-NEXT: ld 3, .LC223@toc@l(3) ; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mtfprwz 0, 4 @@ -8659,9 +8677,9 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI179_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC222@toc@ha ; PC64LE9-NEXT: xscvuxdsp 0, 0 -; PC64LE9-NEXT: addi 3, 3, .LCPI179_0@toc@l +; PC64LE9-NEXT: ld 3, .LC222@toc@l(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3 @@ -8713,9 +8731,9 @@ ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: mtfprd 0, 3 -; PC64LE-NEXT: addis 6, 2, .LCPI181_0@toc@ha +; PC64LE-NEXT: addis 6, 2, .LC224@toc@ha ; PC64LE-NEXT: mtfprd 1, 4 -; PC64LE-NEXT: addi 3, 6, .LCPI181_0@toc@l +; PC64LE-NEXT: ld 3, .LC224@toc@l(6) ; PC64LE-NEXT: xscvuxdsp 0, 0 ; PC64LE-NEXT: xscvuxdsp 1, 1 ; PC64LE-NEXT: mtfprd 2, 5 @@ -8734,9 +8752,9 @@ ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: mtfprd 0, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI181_0@toc@ha +; PC64LE9-NEXT: addis 3, 2, .LC223@toc@ha ; PC64LE9-NEXT: xscvuxdsp 0, 0 -; PC64LE9-NEXT: addi 3, 3, .LCPI181_0@toc@l +; PC64LE9-NEXT: ld 3, .LC223@toc@l(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: mtfprd 0, 4 diff --git a/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll b/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll --- a/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll +++ b/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll @@ -77,8 +77,8 @@ ; ; CHECK-P8-LABEL: test_vextsb2d: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI2_0@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-P8-NEXT: lxvd2x 0, 0, 3 ; CHECK-P8-NEXT: xxswapd 35, 0 ; CHECK-P8-NEXT: vsld 2, 2, 3 @@ -104,8 +104,8 @@ ; ; CHECK-P8-LABEL: test_vextsh2d: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI3_0@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC1@toc@ha +; CHECK-P8-NEXT: ld 3, .LC1@toc@l(3) ; CHECK-P8-NEXT: lxvd2x 0, 0, 3 ; CHECK-P8-NEXT: xxswapd 35, 0 ; CHECK-P8-NEXT: vsld 2, 2, 3 @@ -131,8 +131,8 @@ ; ; CHECK-P8-LABEL: test_vextsw2d: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI4_0@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC2@toc@ha +; CHECK-P8-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-P8-NEXT: lxvd2x 0, 0, 3 ; CHECK-P8-NEXT: xxswapd 35, 0 ; CHECK-P8-NEXT: vsld 2, 2, 3 @@ -147,8 +147,8 @@ define <2 x i64> @test_none(<2 x i64> %m) { ; CHECK-P9-LABEL: test_none: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI5_0@toc@l +; CHECK-P9-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-P9-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-P9-NEXT: lxvx 35, 0, 3 ; CHECK-P9-NEXT: vsld 2, 2, 3 ; CHECK-P9-NEXT: vsrad 2, 2, 3 @@ -164,8 +164,8 @@ ; ; CHECK-P8-LABEL: test_none: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI5_0@toc@l +; CHECK-P8-NEXT: addis 3, 2, .LC3@toc@ha +; CHECK-P8-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-P8-NEXT: lxvd2x 0, 0, 3 ; CHECK-P8-NEXT: xxswapd 35, 0 ; CHECK-P8-NEXT: vsld 2, 2, 3 diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll --- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll +++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll @@ -106,14 +106,13 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_2_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC0@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI2_0@toc@l +; PWR5-NEXT: ld 3, .LC0@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI2_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -131,14 +130,13 @@ ; ; PWR6-LABEL: ugt_2_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC0@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI2_0@toc@l +; PWR6-NEXT: ld 3, .LC0@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI2_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -157,14 +155,13 @@ ; PWR7-LABEL: ugt_2_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI2_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC0@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC0@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI2_1@toc@ha ; PWR7-NEXT: vspltisb 5, 4 ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI2_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -201,14 +198,13 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_3_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC1@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI3_0@toc@l +; PWR5-NEXT: ld 3, .LC1@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI3_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -227,14 +223,13 @@ ; ; PWR6-LABEL: ult_3_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC1@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI3_0@toc@l +; PWR6-NEXT: ld 3, .LC1@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI3_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -254,13 +249,12 @@ ; PWR7-LABEL: ult_3_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI3_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC1@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC1@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI3_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI3_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -299,14 +293,13 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_3_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC2@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI4_0@toc@l +; PWR5-NEXT: ld 3, .LC2@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI4_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -325,14 +318,13 @@ ; ; PWR6-LABEL: ugt_3_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC2@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI4_0@toc@l +; PWR6-NEXT: ld 3, .LC2@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI4_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -352,13 +344,12 @@ ; PWR7-LABEL: ugt_3_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI4_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC2@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC2@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI4_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI4_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -397,14 +388,13 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_4_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC3@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI5_0@toc@l +; PWR5-NEXT: ld 3, .LC3@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI5_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -422,14 +412,13 @@ ; ; PWR6-LABEL: ult_4_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC3@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI5_0@toc@l +; PWR6-NEXT: ld 3, .LC3@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI5_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -448,14 +437,13 @@ ; PWR7-LABEL: ult_4_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI5_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC3@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC3@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI5_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI5_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -492,14 +480,13 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_4_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC4@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI6_0@toc@l +; PWR5-NEXT: ld 3, .LC4@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI6_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -517,14 +504,13 @@ ; ; PWR6-LABEL: ugt_4_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC4@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI6_0@toc@l +; PWR6-NEXT: ld 3, .LC4@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI6_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -543,14 +529,13 @@ ; PWR7-LABEL: ugt_4_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI6_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC4@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC4@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI6_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI6_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -587,14 +572,13 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_5_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI7_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC5@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI7_0@toc@l +; PWR5-NEXT: ld 3, .LC5@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI7_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -613,14 +597,13 @@ ; ; PWR6-LABEL: ult_5_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI7_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC5@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI7_0@toc@l +; PWR6-NEXT: ld 3, .LC5@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI7_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -640,13 +623,12 @@ ; PWR7-LABEL: ult_5_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI7_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC5@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC5@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI7_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI7_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -685,14 +667,13 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_5_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI8_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC6@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI8_0@toc@l +; PWR5-NEXT: ld 3, .LC6@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI8_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -711,14 +692,13 @@ ; ; PWR6-LABEL: ugt_5_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI8_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC6@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI8_0@toc@l +; PWR6-NEXT: ld 3, .LC6@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI8_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -738,13 +718,12 @@ ; PWR7-LABEL: ugt_5_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI8_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC6@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC6@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI8_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI8_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -783,14 +762,13 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_6_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI9_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC7@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI9_0@toc@l +; PWR5-NEXT: ld 3, .LC7@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI9_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -809,14 +787,13 @@ ; ; PWR6-LABEL: ult_6_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI9_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC7@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI9_0@toc@l +; PWR6-NEXT: ld 3, .LC7@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI9_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -836,13 +813,12 @@ ; PWR7-LABEL: ult_6_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI9_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC7@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC7@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI9_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI9_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -881,14 +857,13 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_6_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI10_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC8@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI10_0@toc@l +; PWR5-NEXT: ld 3, .LC8@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI10_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -907,14 +882,13 @@ ; ; PWR6-LABEL: ugt_6_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI10_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC8@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI10_0@toc@l +; PWR6-NEXT: ld 3, .LC8@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI10_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -934,13 +908,12 @@ ; PWR7-LABEL: ugt_6_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI10_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC8@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC8@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI10_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI10_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -979,14 +952,13 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_7_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI11_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC9@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI11_0@toc@l +; PWR5-NEXT: ld 3, .LC9@toc@l(3) ; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI11_1@toc@l ; PWR5-NEXT: vspltisb 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsububm 2, 2, 3 @@ -1005,14 +977,13 @@ ; ; PWR6-LABEL: ult_7_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI11_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC9@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI11_0@toc@l +; PWR6-NEXT: ld 3, .LC9@toc@l(3) ; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI11_1@toc@l ; PWR6-NEXT: vspltisb 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsububm 2, 2, 3 @@ -1032,13 +1003,12 @@ ; PWR7-LABEL: ult_7_v16i8: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI11_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC9@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC9@toc@l(3) ; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI11_1@toc@ha ; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI11_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsububm 2, 2, 3 @@ -1174,14 +1144,13 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_2_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI14_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC10@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltish 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI14_0@toc@l +; PWR5-NEXT: ld 3, .LC10@toc@l(3) ; PWR5-NEXT: vsrh 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI14_1@toc@l ; PWR5-NEXT: vspltish 5, 2 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: vand 3, 3, 4 ; PWR5-NEXT: lvx 4, 0, 3 ; PWR5-NEXT: vsubuhm 2, 2, 3 @@ -1204,14 +1173,13 @@ ; ; PWR6-LABEL: ugt_2_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI14_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC10@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltish 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI14_0@toc@l +; PWR6-NEXT: ld 3, .LC10@toc@l(3) ; PWR6-NEXT: vsrh 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI14_1@toc@l ; PWR6-NEXT: vspltish 5, 2 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: vand 3, 3, 4 ; PWR6-NEXT: lvx 4, 0, 3 ; PWR6-NEXT: vsubuhm 2, 2, 3 @@ -1235,14 +1203,13 @@ ; PWR7-LABEL: ugt_2_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI14_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC10@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC10@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI14_1@toc@ha ; PWR7-NEXT: vspltish 5, 4 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI14_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -1284,29 +1251,28 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_3_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI15_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI15_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC11@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC11@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 3 @@ -1315,29 +1281,28 @@ ; ; PWR6-LABEL: ult_3_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI15_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI15_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC11@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC11@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 3 @@ -1347,14 +1312,13 @@ ; PWR7-LABEL: ult_3_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI15_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC11@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC11@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI15_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI15_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -1397,29 +1361,28 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_3_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC12@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC12@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 3 @@ -1428,29 +1391,28 @@ ; ; PWR6-LABEL: ugt_3_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC12@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC12@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 3 @@ -1460,14 +1422,13 @@ ; PWR7-LABEL: ugt_3_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI16_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC12@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC12@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI16_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI16_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -1510,29 +1471,28 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_4_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI17_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI17_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC13@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC13@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 15 +; PWR5-NEXT: vxor 4, 4, 4 +; PWR5-NEXT: vand 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vcmpgtuh 2, 5, 2 @@ -1540,29 +1500,28 @@ ; ; PWR6-LABEL: ult_4_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI17_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI17_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC13@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC13@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 15 +; PWR6-NEXT: vxor 4, 4, 4 +; PWR6-NEXT: vand 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vcmpgtuh 2, 5, 2 @@ -1571,15 +1530,14 @@ ; PWR7-LABEL: ult_4_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI17_0@toc@ha +; PWR7-NEXT: addis 3, 2, .LC13@toc@ha +; PWR7-NEXT: li 4, 16 ; PWR7-NEXT: vxor 5, 5, 5 -; PWR7-NEXT: addi 3, 3, .LCPI17_0@toc@l +; PWR7-NEXT: ld 3, .LC13@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI17_1@toc@ha ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI17_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -1620,29 +1578,28 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_4_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI18_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC14@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC14@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 15 +; PWR5-NEXT: vxor 4, 4, 4 +; PWR5-NEXT: vand 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vcmpgtuh 2, 2, 5 @@ -1650,29 +1607,28 @@ ; ; PWR6-LABEL: ugt_4_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI18_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC14@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC14@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 15 +; PWR6-NEXT: vxor 4, 4, 4 +; PWR6-NEXT: vand 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vcmpgtuh 2, 2, 5 @@ -1681,15 +1637,14 @@ ; PWR7-LABEL: ugt_4_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI18_0@toc@ha +; PWR7-NEXT: addis 3, 2, .LC14@toc@ha +; PWR7-NEXT: li 4, 16 ; PWR7-NEXT: vxor 5, 5, 5 -; PWR7-NEXT: addi 3, 3, .LCPI18_0@toc@l +; PWR7-NEXT: ld 3, .LC14@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI18_1@toc@ha ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI18_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -1730,29 +1685,28 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_5_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC15@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC15@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 5 @@ -1761,29 +1715,28 @@ ; ; PWR6-LABEL: ult_5_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC15@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC15@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 5 @@ -1793,14 +1746,13 @@ ; PWR7-LABEL: ult_5_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI19_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC15@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC15@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI19_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI19_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -1843,29 +1795,28 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_5_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI20_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI20_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC16@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC16@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 5 @@ -1874,29 +1825,28 @@ ; ; PWR6-LABEL: ugt_5_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI20_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI20_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC16@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC16@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 5 @@ -1906,14 +1856,13 @@ ; PWR7-LABEL: ugt_5_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI20_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC16@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC16@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI20_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI20_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -1956,29 +1905,28 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_6_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC17@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC17@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 6 @@ -1987,29 +1935,28 @@ ; ; PWR6-LABEL: ult_6_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC17@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC17@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 6 @@ -2019,14 +1966,13 @@ ; PWR7-LABEL: ult_6_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI21_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC17@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC17@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI21_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI21_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2069,29 +2015,28 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_6_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI22_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI22_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC18@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC18@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 6 @@ -2100,29 +2045,28 @@ ; ; PWR6-LABEL: ugt_6_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI22_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI22_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC18@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC18@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 6 @@ -2132,14 +2076,13 @@ ; PWR7-LABEL: ugt_6_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI22_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC18@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC18@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI22_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI22_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2182,29 +2125,28 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_7_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI23_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC19@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC19@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 7 @@ -2213,29 +2155,28 @@ ; ; PWR6-LABEL: ult_7_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI23_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC19@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC19@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 7 @@ -2245,14 +2186,13 @@ ; PWR7-LABEL: ult_7_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI23_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC19@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC19@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI23_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2295,29 +2235,28 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_7_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC20@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC20@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 7 @@ -2326,29 +2265,28 @@ ; ; PWR6-LABEL: ugt_7_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC20@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC20@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 7 @@ -2358,14 +2296,13 @@ ; PWR7-LABEL: ugt_7_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI24_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC20@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC20@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI24_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2408,29 +2345,28 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_8_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI25_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI25_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC21@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC21@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vcmpgtuh 2, 3, 2 @@ -2438,29 +2374,28 @@ ; ; PWR6-LABEL: ult_8_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI25_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI25_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC21@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC21@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vcmpgtuh 2, 3, 2 @@ -2469,14 +2404,13 @@ ; PWR7-LABEL: ult_8_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI25_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC21@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC21@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI25_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI25_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2518,29 +2452,28 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_8_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI26_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI26_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC22@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC22@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vcmpgtuh 2, 2, 3 @@ -2548,29 +2481,28 @@ ; ; PWR6-LABEL: ugt_8_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI26_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI26_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC22@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC22@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vcmpgtuh 2, 2, 3 @@ -2579,14 +2511,13 @@ ; PWR7-LABEL: ugt_8_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI26_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC22@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC22@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI26_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI26_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2628,29 +2559,28 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_9_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI27_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI27_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC23@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC23@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 9 @@ -2659,29 +2589,28 @@ ; ; PWR6-LABEL: ult_9_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI27_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI27_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC23@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC23@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 9 @@ -2691,14 +2620,13 @@ ; PWR7-LABEL: ult_9_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI27_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC23@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC23@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI27_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI27_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2741,29 +2669,28 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_9_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI28_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI28_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC24@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC24@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 9 @@ -2772,29 +2699,28 @@ ; ; PWR6-LABEL: ugt_9_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI28_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI28_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC24@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC24@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 9 @@ -2804,14 +2730,13 @@ ; PWR7-LABEL: ugt_9_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI28_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC24@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC24@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI28_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI28_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2854,29 +2779,28 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_10_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI29_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC25@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC25@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 10 @@ -2885,29 +2809,28 @@ ; ; PWR6-LABEL: ult_10_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI29_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC25@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC25@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 10 @@ -2917,14 +2840,13 @@ ; PWR7-LABEL: ult_10_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI29_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC25@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC25@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI29_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI29_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -2967,29 +2889,28 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_10_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI30_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI30_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC26@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC26@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 10 @@ -2998,29 +2919,28 @@ ; ; PWR6-LABEL: ugt_10_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI30_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI30_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC26@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC26@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 10 @@ -3030,14 +2950,13 @@ ; PWR7-LABEL: ugt_10_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI30_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC26@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC26@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI30_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI30_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3080,29 +2999,28 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_11_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI31_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI31_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC27@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC27@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 11 @@ -3111,29 +3029,28 @@ ; ; PWR6-LABEL: ult_11_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI31_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI31_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC27@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC27@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 11 @@ -3143,14 +3060,13 @@ ; PWR7-LABEL: ult_11_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI31_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC27@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC27@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI31_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI31_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3193,29 +3109,28 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_11_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI32_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI32_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC28@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC28@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 11 @@ -3224,29 +3139,28 @@ ; ; PWR6-LABEL: ugt_11_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI32_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI32_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC28@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC28@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 11 @@ -3256,14 +3170,13 @@ ; PWR7-LABEL: ugt_11_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI32_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC28@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC28@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI32_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI32_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3306,29 +3219,28 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_12_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI33_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI33_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC29@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC29@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 12 @@ -3337,29 +3249,28 @@ ; ; PWR6-LABEL: ult_12_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI33_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI33_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC29@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC29@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 12 @@ -3369,14 +3280,13 @@ ; PWR7-LABEL: ult_12_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI33_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC29@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC29@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI33_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI33_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3419,29 +3329,28 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_12_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI34_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI34_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC30@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC30@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 12 @@ -3450,29 +3359,28 @@ ; ; PWR6-LABEL: ugt_12_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI34_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI34_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC30@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC30@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 12 @@ -3482,14 +3390,13 @@ ; PWR7-LABEL: ugt_12_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI34_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC30@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC30@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI34_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI34_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3532,29 +3439,28 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_13_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI35_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI35_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC31@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC31@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 13 @@ -3563,29 +3469,28 @@ ; ; PWR6-LABEL: ult_13_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI35_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI35_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC31@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC31@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 13 @@ -3595,14 +3500,13 @@ ; PWR7-LABEL: ult_13_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI35_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC31@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC31@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI35_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI35_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3645,29 +3549,28 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_13_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI36_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI36_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC32@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC32@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 13 @@ -3676,29 +3579,28 @@ ; ; PWR6-LABEL: ugt_13_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI36_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI36_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC32@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC32@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 13 @@ -3708,14 +3610,13 @@ ; PWR7-LABEL: ugt_13_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI36_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC32@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC32@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI36_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3758,60 +3659,58 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_14_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI37_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI37_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC33@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC33@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 14 ; PWR5-NEXT: vcmpgtuh 2, 3, 2 ; PWR5-NEXT: blr -; -; PWR6-LABEL: ult_14_v8i16: -; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI37_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI37_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; +; PWR6-LABEL: ult_14_v8i16: +; PWR6: # %bb.0: +; PWR6-NEXT: addis 3, 2, .LC33@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC33@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 14 @@ -3821,14 +3720,13 @@ ; PWR7-LABEL: ult_14_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI37_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC33@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC33@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI37_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3871,29 +3769,28 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_14_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI38_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI38_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC34@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC34@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 14 @@ -3902,29 +3799,28 @@ ; ; PWR6-LABEL: ugt_14_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI38_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI38_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC34@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC34@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 14 @@ -3934,14 +3830,13 @@ ; PWR7-LABEL: ugt_14_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI38_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC34@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC34@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI38_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI38_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -3984,29 +3879,28 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_15_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI39_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI39_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: addis 3, 2, .LC35@toc@ha +; PWR5-NEXT: li 4, 16 +; PWR5-NEXT: vspltish 3, 1 +; PWR5-NEXT: ld 3, .LC35@toc@l(3) +; PWR5-NEXT: vsrh 3, 2, 3 +; PWR5-NEXT: lvx 4, 3, 4 ; PWR5-NEXT: lvx 5, 0, 3 +; PWR5-NEXT: vand 3, 3, 4 +; PWR5-NEXT: vsubuhm 2, 2, 3 +; PWR5-NEXT: vspltish 3, 2 +; PWR5-NEXT: vsrh 3, 2, 3 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 +; PWR5-NEXT: vand 3, 3, 5 ; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vsrh 3, 2, 5 ; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 +; PWR5-NEXT: vadduhm 2, 2, 3 +; PWR5-NEXT: vspltisb 3, 1 +; PWR5-NEXT: vxor 4, 4, 4 ; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 +; PWR5-NEXT: vmladduhm 2, 2, 3, 4 ; PWR5-NEXT: vspltish 3, 8 ; PWR5-NEXT: vsrh 2, 2, 3 ; PWR5-NEXT: vspltish 3, 15 @@ -4015,29 +3909,28 @@ ; ; PWR6-LABEL: ult_15_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI39_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI39_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: addis 3, 2, .LC35@toc@ha +; PWR6-NEXT: li 4, 16 +; PWR6-NEXT: vspltish 3, 1 +; PWR6-NEXT: ld 3, .LC35@toc@l(3) +; PWR6-NEXT: vsrh 3, 2, 3 +; PWR6-NEXT: lvx 4, 3, 4 ; PWR6-NEXT: lvx 5, 0, 3 +; PWR6-NEXT: vand 3, 3, 4 +; PWR6-NEXT: vsubuhm 2, 2, 3 +; PWR6-NEXT: vspltish 3, 2 +; PWR6-NEXT: vsrh 3, 2, 3 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 +; PWR6-NEXT: vand 3, 3, 5 ; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vsrh 3, 2, 5 ; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 +; PWR6-NEXT: vadduhm 2, 2, 3 +; PWR6-NEXT: vspltisb 3, 1 +; PWR6-NEXT: vxor 4, 4, 4 ; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 +; PWR6-NEXT: vmladduhm 2, 2, 3, 4 ; PWR6-NEXT: vspltish 3, 8 ; PWR6-NEXT: vsrh 2, 2, 3 ; PWR6-NEXT: vspltish 3, 15 @@ -4047,14 +3940,13 @@ ; PWR7-LABEL: ult_15_v8i16: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI39_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC35@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC35@toc@l(3) ; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI39_1@toc@ha ; PWR7-NEXT: vspltisb 5, 15 ; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI39_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 ; PWR7-NEXT: vsubuhm 2, 2, 3 @@ -4194,14 +4086,13 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_2_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI42_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC36@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI42_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI42_1@toc@l +; PWR5-NEXT: ld 3, .LC36@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -4230,14 +4121,13 @@ ; ; PWR6-LABEL: ugt_2_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI42_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC36@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI42_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI42_1@toc@l +; PWR6-NEXT: ld 3, .LC36@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -4267,14 +4157,13 @@ ; PWR7-LABEL: ugt_2_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI42_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC36@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC36@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI42_1@toc@ha ; PWR7-NEXT: vspltisw 5, 4 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI42_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisw 0, -16 ; PWR7-NEXT: vspltisb 1, 15 ; PWR7-NEXT: xxland 35, 35, 0 @@ -4322,14 +4211,13 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_3_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI43_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC37@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI43_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI43_1@toc@l +; PWR5-NEXT: ld 3, .LC37@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -4359,14 +4247,13 @@ ; ; PWR6-LABEL: ult_3_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI43_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC37@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI43_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI43_1@toc@l +; PWR6-NEXT: ld 3, .LC37@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -4397,14 +4284,13 @@ ; PWR7-LABEL: ult_3_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI43_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI43_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC37@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC37@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI43_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI43_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -4453,14 +4339,13 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_3_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI44_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC38@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI44_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI44_1@toc@l +; PWR5-NEXT: ld 3, .LC38@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -4490,14 +4375,13 @@ ; ; PWR6-LABEL: ugt_3_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI44_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC38@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI44_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI44_1@toc@l +; PWR6-NEXT: ld 3, .LC38@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -4528,14 +4412,13 @@ ; PWR7-LABEL: ugt_3_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI44_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI44_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC38@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC38@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI44_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI44_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -4584,14 +4467,13 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_4_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI45_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC39@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI45_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI45_1@toc@l +; PWR5-NEXT: ld 3, .LC39@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -4620,14 +4502,13 @@ ; ; PWR6-LABEL: ult_4_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI45_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC39@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI45_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI45_1@toc@l +; PWR6-NEXT: ld 3, .LC39@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -4657,14 +4538,13 @@ ; PWR7-LABEL: ult_4_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI45_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC39@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC39@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI45_1@toc@ha ; PWR7-NEXT: vspltisb 5, 1 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI45_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisw 0, -16 ; PWR7-NEXT: vspltisb 1, 15 ; PWR7-NEXT: vrlw 6, 5, 0 @@ -4712,14 +4592,13 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_4_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI46_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC40@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI46_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI46_1@toc@l +; PWR5-NEXT: ld 3, .LC40@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -4748,14 +4627,13 @@ ; ; PWR6-LABEL: ugt_4_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI46_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC40@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI46_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI46_1@toc@l +; PWR6-NEXT: ld 3, .LC40@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -4785,14 +4663,13 @@ ; PWR7-LABEL: ugt_4_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI46_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC40@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC40@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI46_1@toc@ha ; PWR7-NEXT: vspltisb 5, 1 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI46_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisw 0, -16 ; PWR7-NEXT: vspltisb 1, 15 ; PWR7-NEXT: vrlw 6, 5, 0 @@ -4840,14 +4717,13 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_5_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI47_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC41@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI47_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI47_1@toc@l +; PWR5-NEXT: ld 3, .LC41@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -4877,14 +4753,13 @@ ; ; PWR6-LABEL: ult_5_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI47_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC41@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI47_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI47_1@toc@l +; PWR6-NEXT: ld 3, .LC41@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -4915,14 +4790,13 @@ ; PWR7-LABEL: ult_5_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI47_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC41@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC41@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI47_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI47_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -4971,14 +4845,13 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_5_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI48_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC42@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI48_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI48_1@toc@l +; PWR5-NEXT: ld 3, .LC42@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5008,14 +4881,13 @@ ; ; PWR6-LABEL: ugt_5_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI48_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC42@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI48_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI48_1@toc@l +; PWR6-NEXT: ld 3, .LC42@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5046,14 +4918,13 @@ ; PWR7-LABEL: ugt_5_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI48_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC42@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC42@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI48_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI48_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5102,14 +4973,13 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_6_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI49_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC43@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI49_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI49_1@toc@l +; PWR5-NEXT: ld 3, .LC43@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5139,14 +5009,13 @@ ; ; PWR6-LABEL: ult_6_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI49_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC43@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI49_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI49_1@toc@l +; PWR6-NEXT: ld 3, .LC43@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5177,14 +5046,13 @@ ; PWR7-LABEL: ult_6_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI49_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI49_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC43@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC43@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI49_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI49_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5233,14 +5101,13 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_6_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI50_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC44@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI50_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI50_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI50_1@toc@l +; PWR5-NEXT: ld 3, .LC44@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5270,14 +5137,13 @@ ; ; PWR6-LABEL: ugt_6_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI50_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC44@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI50_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI50_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI50_1@toc@l +; PWR6-NEXT: ld 3, .LC44@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5308,14 +5174,13 @@ ; PWR7-LABEL: ugt_6_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI50_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC44@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC44@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI50_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI50_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5364,14 +5229,13 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_7_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI51_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC45@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI51_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI51_1@toc@l +; PWR5-NEXT: ld 3, .LC45@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5401,14 +5265,13 @@ ; ; PWR6-LABEL: ult_7_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI51_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC45@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI51_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI51_1@toc@l +; PWR6-NEXT: ld 3, .LC45@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5439,14 +5302,13 @@ ; PWR7-LABEL: ult_7_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI51_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC45@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC45@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI51_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI51_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5495,14 +5357,13 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_7_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI52_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC46@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI52_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI52_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI52_1@toc@l +; PWR5-NEXT: ld 3, .LC46@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5532,14 +5393,13 @@ ; ; PWR6-LABEL: ugt_7_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI52_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC46@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI52_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI52_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI52_1@toc@l +; PWR6-NEXT: ld 3, .LC46@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5570,14 +5430,13 @@ ; PWR7-LABEL: ugt_7_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI52_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC46@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC46@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI52_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI52_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5626,14 +5485,13 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_8_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI53_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC47@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI53_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI53_1@toc@l +; PWR5-NEXT: ld 3, .LC47@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5663,14 +5521,13 @@ ; ; PWR6-LABEL: ult_8_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI53_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC47@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI53_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI53_1@toc@l +; PWR6-NEXT: ld 3, .LC47@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5701,14 +5558,13 @@ ; PWR7-LABEL: ult_8_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI53_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI53_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC47@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC47@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI53_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI53_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5757,14 +5613,13 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_8_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI54_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC48@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI54_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI54_1@toc@l +; PWR5-NEXT: ld 3, .LC48@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5794,14 +5649,13 @@ ; ; PWR6-LABEL: ugt_8_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI54_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC48@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI54_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI54_1@toc@l +; PWR6-NEXT: ld 3, .LC48@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5832,14 +5686,13 @@ ; PWR7-LABEL: ugt_8_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI54_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI54_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC48@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC48@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI54_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI54_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -5888,14 +5741,13 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_9_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI55_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC49@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI55_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI55_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI55_1@toc@l +; PWR5-NEXT: ld 3, .LC49@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -5925,14 +5777,13 @@ ; ; PWR6-LABEL: ult_9_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI55_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC49@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI55_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI55_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI55_1@toc@l +; PWR6-NEXT: ld 3, .LC49@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -5963,14 +5814,13 @@ ; PWR7-LABEL: ult_9_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI55_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC49@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC49@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI55_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI55_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6019,14 +5869,13 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_9_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI56_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC50@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI56_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI56_1@toc@l +; PWR5-NEXT: ld 3, .LC50@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6056,14 +5905,13 @@ ; ; PWR6-LABEL: ugt_9_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI56_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC50@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI56_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI56_1@toc@l +; PWR6-NEXT: ld 3, .LC50@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6094,14 +5942,13 @@ ; PWR7-LABEL: ugt_9_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI56_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC50@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC50@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI56_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI56_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6150,14 +5997,13 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_10_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI57_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC51@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI57_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI57_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI57_1@toc@l +; PWR5-NEXT: ld 3, .LC51@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6187,14 +6033,13 @@ ; ; PWR6-LABEL: ult_10_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI57_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC51@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI57_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI57_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI57_1@toc@l +; PWR6-NEXT: ld 3, .LC51@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6225,14 +6070,13 @@ ; PWR7-LABEL: ult_10_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI57_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC51@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC51@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI57_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI57_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6281,14 +6125,13 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_10_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI58_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC52@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI58_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI58_1@toc@l +; PWR5-NEXT: ld 3, .LC52@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6318,14 +6161,13 @@ ; ; PWR6-LABEL: ugt_10_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI58_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC52@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI58_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI58_1@toc@l +; PWR6-NEXT: ld 3, .LC52@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6356,14 +6198,13 @@ ; PWR7-LABEL: ugt_10_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI58_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC52@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC52@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI58_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI58_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6412,14 +6253,13 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_11_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI59_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC53@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI59_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI59_1@toc@l +; PWR5-NEXT: ld 3, .LC53@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6449,14 +6289,13 @@ ; ; PWR6-LABEL: ult_11_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI59_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC53@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI59_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI59_1@toc@l +; PWR6-NEXT: ld 3, .LC53@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6487,14 +6326,13 @@ ; PWR7-LABEL: ult_11_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI59_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC53@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC53@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI59_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI59_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6543,14 +6381,13 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_11_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI60_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC54@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI60_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI60_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI60_1@toc@l +; PWR5-NEXT: ld 3, .LC54@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6580,14 +6417,13 @@ ; ; PWR6-LABEL: ugt_11_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI60_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC54@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI60_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI60_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI60_1@toc@l +; PWR6-NEXT: ld 3, .LC54@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6618,14 +6454,13 @@ ; PWR7-LABEL: ugt_11_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI60_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC54@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC54@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI60_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI60_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6674,14 +6509,13 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_12_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI61_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC55@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI61_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI61_1@toc@l +; PWR5-NEXT: ld 3, .LC55@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6710,14 +6544,13 @@ ; ; PWR6-LABEL: ult_12_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI61_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC55@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI61_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI61_1@toc@l +; PWR6-NEXT: ld 3, .LC55@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6747,14 +6580,13 @@ ; PWR7-LABEL: ult_12_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI61_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC55@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC55@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI61_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI61_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6802,14 +6634,13 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_12_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI62_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC56@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI62_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI62_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI62_1@toc@l +; PWR5-NEXT: ld 3, .LC56@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6838,14 +6669,13 @@ ; ; PWR6-LABEL: ugt_12_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI62_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC56@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI62_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI62_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI62_1@toc@l +; PWR6-NEXT: ld 3, .LC56@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -6875,14 +6705,13 @@ ; PWR7-LABEL: ugt_12_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI62_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC56@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC56@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI62_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI62_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -6930,14 +6759,13 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_13_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI63_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC57@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI63_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI63_1@toc@l +; PWR5-NEXT: ld 3, .LC57@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -6967,14 +6795,13 @@ ; ; PWR6-LABEL: ult_13_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI63_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC57@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI63_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI63_1@toc@l +; PWR6-NEXT: ld 3, .LC57@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7005,14 +6832,13 @@ ; PWR7-LABEL: ult_13_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI63_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC57@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC57@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI63_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI63_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7061,14 +6887,13 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_13_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI64_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC58@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI64_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI64_1@toc@l +; PWR5-NEXT: ld 3, .LC58@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7098,14 +6923,13 @@ ; ; PWR6-LABEL: ugt_13_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI64_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC58@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI64_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI64_1@toc@l +; PWR6-NEXT: ld 3, .LC58@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7136,14 +6960,13 @@ ; PWR7-LABEL: ugt_13_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI64_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC58@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC58@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI64_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI64_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7192,14 +7015,13 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_14_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI65_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC59@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI65_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI65_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI65_1@toc@l +; PWR5-NEXT: ld 3, .LC59@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7229,14 +7051,13 @@ ; ; PWR6-LABEL: ult_14_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI65_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC59@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI65_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI65_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI65_1@toc@l +; PWR6-NEXT: ld 3, .LC59@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7267,14 +7088,13 @@ ; PWR7-LABEL: ult_14_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI65_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC59@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC59@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI65_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI65_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7323,14 +7143,13 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_14_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI66_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC60@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI66_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI66_1@toc@l +; PWR5-NEXT: ld 3, .LC60@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7360,14 +7179,13 @@ ; ; PWR6-LABEL: ugt_14_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI66_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC60@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI66_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI66_1@toc@l +; PWR6-NEXT: ld 3, .LC60@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7398,14 +7216,13 @@ ; PWR7-LABEL: ugt_14_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI66_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC60@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC60@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI66_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI66_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7454,14 +7271,13 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_15_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI67_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC61@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI67_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI67_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI67_1@toc@l +; PWR5-NEXT: ld 3, .LC61@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7491,14 +7307,13 @@ ; ; PWR6-LABEL: ult_15_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI67_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC61@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI67_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI67_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI67_1@toc@l +; PWR6-NEXT: ld 3, .LC61@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7529,14 +7344,13 @@ ; PWR7-LABEL: ult_15_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI67_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC61@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC61@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI67_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI67_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7585,14 +7399,13 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_15_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI68_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC62@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI68_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI68_1@toc@l +; PWR5-NEXT: ld 3, .LC62@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7622,14 +7435,13 @@ ; ; PWR6-LABEL: ugt_15_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI68_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC62@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI68_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI68_1@toc@l +; PWR6-NEXT: ld 3, .LC62@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7660,14 +7472,13 @@ ; PWR7-LABEL: ugt_15_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI68_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC62@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC62@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI68_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI68_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7716,14 +7527,13 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_16_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI69_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC63@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI69_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI69_1@toc@l +; PWR5-NEXT: ld 3, .LC63@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7754,14 +7564,13 @@ ; ; PWR6-LABEL: ult_16_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI69_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC63@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI69_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI69_1@toc@l +; PWR6-NEXT: ld 3, .LC63@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7793,14 +7602,13 @@ ; PWR7-LABEL: ult_16_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI69_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC63@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC63@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI69_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI69_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7852,14 +7660,13 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_16_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI70_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC64@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI70_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI70_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI70_1@toc@l +; PWR5-NEXT: ld 3, .LC64@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -7890,14 +7697,13 @@ ; ; PWR6-LABEL: ugt_16_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI70_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC64@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI70_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI70_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI70_1@toc@l +; PWR6-NEXT: ld 3, .LC64@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -7929,14 +7735,13 @@ ; PWR7-LABEL: ugt_16_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI70_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC64@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC64@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI70_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI70_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -7988,14 +7793,13 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_17_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI71_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC65@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI71_0@toc@l -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI71_1@toc@l +; PWR5-NEXT: ld 3, .LC65@toc@l(3) ; PWR5-NEXT: vspltisw 1, 2 +; PWR5-NEXT: lvx 0, 3, 4 ; PWR5-NEXT: vsrw 5, 2, 4 ; PWR5-NEXT: vand 5, 5, 0 ; PWR5-NEXT: lvx 0, 0, 3 @@ -8025,14 +7829,13 @@ ; ; PWR6-LABEL: ult_17_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI71_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC65@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI71_0@toc@l -; PWR6-NEXT: lvx 0, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI71_1@toc@l +; PWR6-NEXT: ld 3, .LC65@toc@l(3) ; PWR6-NEXT: vspltisw 1, 2 +; PWR6-NEXT: lvx 0, 3, 4 ; PWR6-NEXT: vsrw 5, 2, 4 ; PWR6-NEXT: vand 5, 5, 0 ; PWR6-NEXT: lvx 0, 0, 3 @@ -8063,14 +7866,13 @@ ; PWR7-LABEL: ult_17_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI71_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC65@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC65@toc@l(3) ; PWR7-NEXT: vspltisw 5, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI71_1@toc@ha ; PWR7-NEXT: vspltisw 0, -16 ; PWR7-NEXT: vsrw 4, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI71_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 1, 15 ; PWR7-NEXT: vsubuwm 3, 3, 0 ; PWR7-NEXT: xxland 36, 36, 0 @@ -8123,14 +7925,13 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_17_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI72_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC66@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI72_0@toc@l -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI72_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI72_1@toc@l +; PWR5-NEXT: ld 3, .LC66@toc@l(3) ; PWR5-NEXT: vspltisw 1, 2 +; PWR5-NEXT: lvx 0, 3, 4 ; PWR5-NEXT: vsrw 5, 2, 4 ; PWR5-NEXT: vand 5, 5, 0 ; PWR5-NEXT: lvx 0, 0, 3 @@ -8160,14 +7961,13 @@ ; ; PWR6-LABEL: ugt_17_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI72_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC66@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI72_0@toc@l -; PWR6-NEXT: lvx 0, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI72_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI72_1@toc@l +; PWR6-NEXT: ld 3, .LC66@toc@l(3) ; PWR6-NEXT: vspltisw 1, 2 +; PWR6-NEXT: lvx 0, 3, 4 ; PWR6-NEXT: vsrw 5, 2, 4 ; PWR6-NEXT: vand 5, 5, 0 ; PWR6-NEXT: lvx 0, 0, 3 @@ -8198,14 +7998,13 @@ ; PWR7-LABEL: ugt_17_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI72_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC66@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC66@toc@l(3) ; PWR7-NEXT: vspltisw 5, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI72_1@toc@ha ; PWR7-NEXT: vspltisw 0, -16 ; PWR7-NEXT: vsrw 4, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI72_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 1, 15 ; PWR7-NEXT: vsubuwm 3, 3, 0 ; PWR7-NEXT: xxland 36, 36, 0 @@ -8258,14 +8057,13 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_18_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI73_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC67@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI73_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI73_1@toc@l +; PWR5-NEXT: ld 3, .LC67@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -8296,14 +8094,13 @@ ; ; PWR6-LABEL: ult_18_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI73_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC67@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI73_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI73_1@toc@l +; PWR6-NEXT: ld 3, .LC67@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -8335,14 +8132,13 @@ ; PWR7-LABEL: ult_18_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI73_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI73_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC67@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC67@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI73_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI73_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -8394,14 +8190,13 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_18_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI74_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC68@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI74_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI74_1@toc@l +; PWR5-NEXT: ld 3, .LC68@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -8432,14 +8227,13 @@ ; ; PWR6-LABEL: ugt_18_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI74_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC68@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI74_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI74_1@toc@l +; PWR6-NEXT: ld 3, .LC68@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -8471,14 +8265,13 @@ ; PWR7-LABEL: ugt_18_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI74_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI74_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC68@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC68@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI74_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI74_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -8530,14 +8323,13 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_19_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI75_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC69@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI75_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI75_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI75_1@toc@l +; PWR5-NEXT: ld 3, .LC69@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -8568,14 +8360,13 @@ ; ; PWR6-LABEL: ult_19_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI75_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC69@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI75_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI75_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI75_1@toc@l +; PWR6-NEXT: ld 3, .LC69@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -8607,14 +8398,13 @@ ; PWR7-LABEL: ult_19_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI75_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC69@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC69@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI75_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI75_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -8668,14 +8458,13 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_19_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI76_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC70@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI76_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI76_1@toc@l +; PWR5-NEXT: ld 3, .LC70@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -8706,14 +8495,13 @@ ; ; PWR6-LABEL: ugt_19_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI76_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC70@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI76_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI76_1@toc@l +; PWR6-NEXT: ld 3, .LC70@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -8745,14 +8533,13 @@ ; PWR7-LABEL: ugt_19_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI76_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC70@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC70@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI76_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI76_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -8806,14 +8593,13 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_20_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI77_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC71@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI77_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI77_1@toc@l +; PWR5-NEXT: ld 3, .LC71@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -8844,14 +8630,13 @@ ; ; PWR6-LABEL: ult_20_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI77_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC71@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI77_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI77_1@toc@l +; PWR6-NEXT: ld 3, .LC71@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -8883,14 +8668,13 @@ ; PWR7-LABEL: ult_20_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI77_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC71@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC71@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI77_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI77_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -8942,14 +8726,13 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_20_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI78_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC72@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI78_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI78_1@toc@l +; PWR5-NEXT: ld 3, .LC72@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -8980,14 +8763,13 @@ ; ; PWR6-LABEL: ugt_20_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI78_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC72@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI78_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI78_1@toc@l +; PWR6-NEXT: ld 3, .LC72@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9019,14 +8801,13 @@ ; PWR7-LABEL: ugt_20_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI78_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC72@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC72@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI78_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI78_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9078,14 +8859,13 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_21_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI79_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC73@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI79_1@toc@l +; PWR5-NEXT: ld 3, .LC73@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9116,14 +8896,13 @@ ; ; PWR6-LABEL: ult_21_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI79_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC73@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI79_1@toc@l +; PWR6-NEXT: ld 3, .LC73@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9155,14 +8934,13 @@ ; PWR7-LABEL: ult_21_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI79_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC73@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC73@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI79_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI79_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9216,14 +8994,13 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_21_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI80_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC74@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI80_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI80_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI80_1@toc@l +; PWR5-NEXT: ld 3, .LC74@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9254,14 +9031,13 @@ ; ; PWR6-LABEL: ugt_21_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI80_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC74@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI80_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI80_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI80_1@toc@l +; PWR6-NEXT: ld 3, .LC74@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9293,14 +9069,13 @@ ; PWR7-LABEL: ugt_21_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI80_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC74@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC74@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI80_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI80_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9354,14 +9129,13 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_22_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI81_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC75@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI81_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI81_1@toc@l +; PWR5-NEXT: ld 3, .LC75@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9392,14 +9166,13 @@ ; ; PWR6-LABEL: ult_22_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI81_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC75@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI81_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI81_1@toc@l +; PWR6-NEXT: ld 3, .LC75@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9431,14 +9204,13 @@ ; PWR7-LABEL: ult_22_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI81_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC75@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC75@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI81_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI81_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9490,14 +9262,13 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_22_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI82_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC76@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI82_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI82_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI82_1@toc@l +; PWR5-NEXT: ld 3, .LC76@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9528,14 +9299,13 @@ ; ; PWR6-LABEL: ugt_22_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI82_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC76@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI82_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI82_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI82_1@toc@l +; PWR6-NEXT: ld 3, .LC76@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9567,14 +9337,13 @@ ; PWR7-LABEL: ugt_22_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI82_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC76@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC76@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI82_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI82_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9626,14 +9395,13 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_23_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI83_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC77@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI83_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI83_1@toc@l +; PWR5-NEXT: ld 3, .LC77@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9664,14 +9432,13 @@ ; ; PWR6-LABEL: ult_23_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI83_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC77@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI83_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI83_1@toc@l +; PWR6-NEXT: ld 3, .LC77@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9703,14 +9470,13 @@ ; PWR7-LABEL: ult_23_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI83_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI83_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC77@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC77@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI83_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI83_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9764,14 +9530,13 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_23_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI84_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC78@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI84_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI84_1@toc@l +; PWR5-NEXT: ld 3, .LC78@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9802,14 +9567,13 @@ ; ; PWR6-LABEL: ugt_23_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI84_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC78@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI84_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI84_1@toc@l +; PWR6-NEXT: ld 3, .LC78@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9841,14 +9605,13 @@ ; PWR7-LABEL: ugt_23_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI84_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI84_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC78@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC78@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI84_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI84_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -9902,14 +9665,13 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_24_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI85_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC79@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI85_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI85_1@toc@l +; PWR5-NEXT: ld 3, .LC79@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -9938,14 +9700,13 @@ ; ; PWR6-LABEL: ult_24_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI85_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC79@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI85_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI85_1@toc@l +; PWR6-NEXT: ld 3, .LC79@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -9975,14 +9736,13 @@ ; PWR7-LABEL: ult_24_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI85_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC79@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC79@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI85_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI85_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10032,14 +9792,13 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_24_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI86_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC80@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI86_1@toc@l +; PWR5-NEXT: ld 3, .LC80@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10068,14 +9827,13 @@ ; ; PWR6-LABEL: ugt_24_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI86_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC80@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI86_1@toc@l +; PWR6-NEXT: ld 3, .LC80@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10105,14 +9863,13 @@ ; PWR7-LABEL: ugt_24_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI86_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC80@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC80@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI86_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI86_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10162,14 +9919,13 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_25_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI87_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC81@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI87_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI87_1@toc@l +; PWR5-NEXT: ld 3, .LC81@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10200,14 +9956,13 @@ ; ; PWR6-LABEL: ult_25_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI87_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC81@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI87_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI87_1@toc@l +; PWR6-NEXT: ld 3, .LC81@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10239,14 +9994,13 @@ ; PWR7-LABEL: ult_25_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI87_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC81@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC81@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI87_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI87_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10300,14 +10054,13 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_25_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI88_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC82@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI88_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI88_1@toc@l +; PWR5-NEXT: ld 3, .LC82@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10338,14 +10091,13 @@ ; ; PWR6-LABEL: ugt_25_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI88_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC82@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI88_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI88_1@toc@l +; PWR6-NEXT: ld 3, .LC82@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10377,14 +10129,13 @@ ; PWR7-LABEL: ugt_25_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI88_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC82@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC82@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI88_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI88_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10438,14 +10189,13 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_26_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI89_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC83@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI89_1@toc@l +; PWR5-NEXT: ld 3, .LC83@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10476,14 +10226,13 @@ ; ; PWR6-LABEL: ult_26_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI89_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC83@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI89_1@toc@l +; PWR6-NEXT: ld 3, .LC83@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10515,14 +10264,13 @@ ; PWR7-LABEL: ult_26_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI89_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC83@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC83@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI89_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI89_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10574,14 +10322,13 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_26_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI90_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC84@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI90_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI90_1@toc@l +; PWR5-NEXT: ld 3, .LC84@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10612,14 +10359,13 @@ ; ; PWR6-LABEL: ugt_26_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI90_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC84@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI90_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI90_1@toc@l +; PWR6-NEXT: ld 3, .LC84@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10651,14 +10397,13 @@ ; PWR7-LABEL: ugt_26_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI90_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC84@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC84@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI90_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI90_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10710,14 +10455,13 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_27_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI91_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC85@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI91_1@toc@l +; PWR5-NEXT: ld 3, .LC85@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10748,14 +10492,13 @@ ; ; PWR6-LABEL: ult_27_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI91_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC85@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI91_1@toc@l +; PWR6-NEXT: ld 3, .LC85@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10787,14 +10530,13 @@ ; PWR7-LABEL: ult_27_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI91_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC85@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC85@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI91_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI91_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10848,14 +10590,13 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_27_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI92_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC86@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI92_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI92_1@toc@l +; PWR5-NEXT: ld 3, .LC86@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -10886,14 +10627,13 @@ ; ; PWR6-LABEL: ugt_27_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI92_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC86@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI92_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI92_1@toc@l +; PWR6-NEXT: ld 3, .LC86@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -10925,14 +10665,13 @@ ; PWR7-LABEL: ugt_27_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI92_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC86@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC86@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI92_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI92_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -10986,14 +10725,13 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_28_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI93_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC87@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI93_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI93_1@toc@l +; PWR5-NEXT: ld 3, .LC87@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11024,14 +10762,13 @@ ; ; PWR6-LABEL: ult_28_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI93_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC87@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI93_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI93_1@toc@l +; PWR6-NEXT: ld 3, .LC87@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11063,14 +10800,13 @@ ; PWR7-LABEL: ult_28_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI93_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC87@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC87@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI93_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI93_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11122,14 +10858,13 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_28_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI94_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC88@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI94_1@toc@l +; PWR5-NEXT: ld 3, .LC88@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11160,14 +10895,13 @@ ; ; PWR6-LABEL: ugt_28_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI94_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC88@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI94_1@toc@l +; PWR6-NEXT: ld 3, .LC88@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11199,14 +10933,13 @@ ; PWR7-LABEL: ugt_28_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI94_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC88@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC88@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI94_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI94_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11258,14 +10991,13 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_29_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI95_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC89@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI95_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI95_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI95_1@toc@l +; PWR5-NEXT: ld 3, .LC89@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11296,14 +11028,13 @@ ; ; PWR6-LABEL: ult_29_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI95_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC89@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI95_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI95_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI95_1@toc@l +; PWR6-NEXT: ld 3, .LC89@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11335,14 +11066,13 @@ ; PWR7-LABEL: ult_29_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI95_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC89@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC89@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI95_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI95_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11396,14 +11126,13 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_29_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI96_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC90@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI96_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI96_1@toc@l +; PWR5-NEXT: ld 3, .LC90@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11434,14 +11163,13 @@ ; ; PWR6-LABEL: ugt_29_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI96_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC90@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI96_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI96_1@toc@l +; PWR6-NEXT: ld 3, .LC90@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11473,14 +11201,13 @@ ; PWR7-LABEL: ugt_29_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI96_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC90@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC90@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI96_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI96_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11534,14 +11261,13 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_30_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI97_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC91@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI97_1@toc@l +; PWR5-NEXT: ld 3, .LC91@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11572,14 +11298,13 @@ ; ; PWR6-LABEL: ult_30_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI97_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC91@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI97_1@toc@l +; PWR6-NEXT: ld 3, .LC91@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11611,14 +11336,13 @@ ; PWR7-LABEL: ult_30_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI97_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC91@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC91@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI97_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI97_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11670,14 +11394,13 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_30_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI98_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC92@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI98_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI98_1@toc@l +; PWR5-NEXT: ld 3, .LC92@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11708,14 +11431,13 @@ ; ; PWR6-LABEL: ugt_30_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI98_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC92@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI98_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI98_1@toc@l +; PWR6-NEXT: ld 3, .LC92@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11747,14 +11469,13 @@ ; PWR7-LABEL: ugt_30_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI98_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC92@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC92@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI98_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI98_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11806,14 +11527,13 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_31_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI99_0@toc@ha +; PWR5-NEXT: addis 3, 2, .LC93@toc@ha +; PWR5-NEXT: li 4, 16 ; PWR5-NEXT: vspltisw 4, 1 ; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI99_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI99_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI99_1@toc@l +; PWR5-NEXT: ld 3, .LC93@toc@l(3) ; PWR5-NEXT: vspltisw 0, 2 +; PWR5-NEXT: lvx 5, 3, 4 ; PWR5-NEXT: vsrw 4, 2, 4 ; PWR5-NEXT: vand 4, 4, 5 ; PWR5-NEXT: lvx 5, 0, 3 @@ -11844,14 +11564,13 @@ ; ; PWR6-LABEL: ult_31_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI99_0@toc@ha +; PWR6-NEXT: addis 3, 2, .LC93@toc@ha +; PWR6-NEXT: li 4, 16 ; PWR6-NEXT: vspltisw 4, 1 ; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI99_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI99_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI99_1@toc@l +; PWR6-NEXT: ld 3, .LC93@toc@l(3) ; PWR6-NEXT: vspltisw 0, 2 +; PWR6-NEXT: lvx 5, 3, 4 ; PWR6-NEXT: vsrw 4, 2, 4 ; PWR6-NEXT: vand 4, 4, 5 ; PWR6-NEXT: lvx 5, 0, 3 @@ -11883,14 +11602,13 @@ ; PWR7-LABEL: ult_31_v4i32: ; PWR7: # %bb.0: ; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI99_0@toc@l +; PWR7-NEXT: addis 3, 2, .LC93@toc@ha +; PWR7-NEXT: li 4, 16 +; PWR7-NEXT: ld 3, .LC93@toc@l(3) ; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI99_1@toc@ha ; PWR7-NEXT: vspltisw 5, -16 ; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: addi 3, 3, .LCPI99_1@toc@l +; PWR7-NEXT: lxvw4x 0, 3, 4 ; PWR7-NEXT: vspltisb 0, 15 ; PWR7-NEXT: xxland 35, 35, 0 ; PWR7-NEXT: lxvw4x 0, 0, 3 @@ -11969,18 +11687,18 @@ ; PWR7-LABEL: ugt_1_v2i64: ; PWR7: # %bb.0: ; PWR7-NEXT: addi 3, 1, -32 +; PWR7-NEXT: addis 4, 2, .LC94@toc@ha ; PWR7-NEXT: stxvd2x 34, 0, 3 +; PWR7-NEXT: ld 4, .LC94@toc@l(4) ; PWR7-NEXT: ld 3, -24(1) ; PWR7-NEXT: addi 3, 3, -1 +; PWR7-NEXT: lxvw4x 35, 0, 4 ; PWR7-NEXT: std 3, -8(1) ; PWR7-NEXT: ld 3, -32(1) ; PWR7-NEXT: addi 3, 3, -1 ; PWR7-NEXT: std 3, -16(1) ; PWR7-NEXT: addi 3, 1, -16 ; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI100_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI100_0@toc@l -; PWR7-NEXT: lxvw4x 35, 0, 3 ; PWR7-NEXT: xxland 34, 34, 0 ; PWR7-NEXT: vcmpequw 2, 2, 3 ; PWR7-NEXT: xxlnor 34, 34, 34 @@ -11988,18 +11706,18 @@ ; ; PWR8-LABEL: ugt_1_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI100_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC0@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI100_0@toc@l +; PWR8-NEXT: ld 3, .LC0@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_1_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI100_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI100_0@toc@l +; PWR9-NEXT: ld 3, .LC0@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -12037,36 +11755,36 @@ ; PWR7-LABEL: ult_2_v2i64: ; PWR7: # %bb.0: ; PWR7-NEXT: addi 3, 1, -32 +; PWR7-NEXT: addis 4, 2, .LC95@toc@ha ; PWR7-NEXT: stxvd2x 34, 0, 3 +; PWR7-NEXT: ld 4, .LC95@toc@l(4) ; PWR7-NEXT: ld 3, -24(1) ; PWR7-NEXT: addi 3, 3, -1 +; PWR7-NEXT: lxvw4x 35, 0, 4 ; PWR7-NEXT: std 3, -8(1) ; PWR7-NEXT: ld 3, -32(1) ; PWR7-NEXT: addi 3, 3, -1 ; PWR7-NEXT: std 3, -16(1) ; PWR7-NEXT: addi 3, 1, -16 ; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI101_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI101_0@toc@l -; PWR7-NEXT: lxvw4x 35, 0, 3 ; PWR7-NEXT: xxland 34, 34, 0 ; PWR7-NEXT: vcmpequw 2, 2, 3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_2_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI101_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC1@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI101_0@toc@l +; PWR8-NEXT: ld 3, .LC1@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_2_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI101_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC1@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI101_0@toc@l +; PWR9-NEXT: ld 3, .LC1@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -12189,18 +11907,18 @@ ; ; PWR8-LABEL: ugt_2_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI102_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC2@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI102_0@toc@l +; PWR8-NEXT: ld 3, .LC2@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_2_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI102_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC2@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI102_0@toc@l +; PWR9-NEXT: ld 3, .LC2@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -12323,18 +12041,18 @@ ; ; PWR8-LABEL: ult_3_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI103_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC3@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI103_0@toc@l +; PWR8-NEXT: ld 3, .LC3@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_3_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI103_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC3@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI103_0@toc@l +; PWR9-NEXT: ld 3, .LC3@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -12457,18 +12175,18 @@ ; ; PWR8-LABEL: ugt_3_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI104_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC4@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI104_0@toc@l +; PWR8-NEXT: ld 3, .LC4@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_3_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI104_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC4@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI104_0@toc@l +; PWR9-NEXT: ld 3, .LC4@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -12591,18 +12309,18 @@ ; ; PWR8-LABEL: ult_4_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI105_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC5@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI105_0@toc@l +; PWR8-NEXT: ld 3, .LC5@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_4_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI105_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC5@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI105_0@toc@l +; PWR9-NEXT: ld 3, .LC5@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -12725,18 +12443,18 @@ ; ; PWR8-LABEL: ugt_4_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI106_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC6@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI106_0@toc@l +; PWR8-NEXT: ld 3, .LC6@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_4_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI106_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC6@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI106_0@toc@l +; PWR9-NEXT: ld 3, .LC6@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -12859,18 +12577,18 @@ ; ; PWR8-LABEL: ult_5_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI107_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC7@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI107_0@toc@l +; PWR8-NEXT: ld 3, .LC7@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_5_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI107_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC7@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI107_0@toc@l +; PWR9-NEXT: ld 3, .LC7@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -12993,18 +12711,18 @@ ; ; PWR8-LABEL: ugt_5_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI108_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC8@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI108_0@toc@l +; PWR8-NEXT: ld 3, .LC8@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_5_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI108_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC8@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI108_0@toc@l +; PWR9-NEXT: ld 3, .LC8@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -13127,18 +12845,18 @@ ; ; PWR8-LABEL: ult_6_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI109_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC9@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI109_0@toc@l +; PWR8-NEXT: ld 3, .LC9@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_6_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI109_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC9@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI109_0@toc@l +; PWR9-NEXT: ld 3, .LC9@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -13261,18 +12979,18 @@ ; ; PWR8-LABEL: ugt_6_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI110_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC10@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI110_0@toc@l +; PWR8-NEXT: ld 3, .LC10@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_6_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI110_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC10@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI110_0@toc@l +; PWR9-NEXT: ld 3, .LC10@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -13395,18 +13113,18 @@ ; ; PWR8-LABEL: ult_7_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI111_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC11@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI111_0@toc@l +; PWR8-NEXT: ld 3, .LC11@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_7_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI111_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC11@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI111_0@toc@l +; PWR9-NEXT: ld 3, .LC11@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -13529,18 +13247,18 @@ ; ; PWR8-LABEL: ugt_7_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI112_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC12@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI112_0@toc@l +; PWR8-NEXT: ld 3, .LC12@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_7_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI112_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC12@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI112_0@toc@l +; PWR9-NEXT: ld 3, .LC12@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -13663,18 +13381,18 @@ ; ; PWR8-LABEL: ult_8_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI113_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC13@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI113_0@toc@l +; PWR8-NEXT: ld 3, .LC13@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_8_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI113_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC13@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI113_0@toc@l +; PWR9-NEXT: ld 3, .LC13@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -13797,18 +13515,18 @@ ; ; PWR8-LABEL: ugt_8_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI114_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC14@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI114_0@toc@l +; PWR8-NEXT: ld 3, .LC14@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_8_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI114_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC14@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI114_0@toc@l +; PWR9-NEXT: ld 3, .LC14@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -13931,18 +13649,18 @@ ; ; PWR8-LABEL: ult_9_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI115_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC15@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI115_0@toc@l +; PWR8-NEXT: ld 3, .LC15@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_9_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI115_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC15@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI115_0@toc@l +; PWR9-NEXT: ld 3, .LC15@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -14065,18 +13783,18 @@ ; ; PWR8-LABEL: ugt_9_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI116_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC16@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI116_0@toc@l +; PWR8-NEXT: ld 3, .LC16@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_9_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI116_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC16@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI116_0@toc@l +; PWR9-NEXT: ld 3, .LC16@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -14199,18 +13917,18 @@ ; ; PWR8-LABEL: ult_10_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI117_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC17@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI117_0@toc@l +; PWR8-NEXT: ld 3, .LC17@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_10_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI117_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC17@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI117_0@toc@l +; PWR9-NEXT: ld 3, .LC17@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -14333,18 +14051,18 @@ ; ; PWR8-LABEL: ugt_10_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI118_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC18@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI118_0@toc@l +; PWR8-NEXT: ld 3, .LC18@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_10_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI118_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC18@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI118_0@toc@l +; PWR9-NEXT: ld 3, .LC18@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -14467,18 +14185,18 @@ ; ; PWR8-LABEL: ult_11_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI119_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC19@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI119_0@toc@l +; PWR8-NEXT: ld 3, .LC19@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_11_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI119_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC19@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI119_0@toc@l +; PWR9-NEXT: ld 3, .LC19@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -14601,18 +14319,18 @@ ; ; PWR8-LABEL: ugt_11_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI120_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC20@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI120_0@toc@l +; PWR8-NEXT: ld 3, .LC20@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_11_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI120_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC20@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI120_0@toc@l +; PWR9-NEXT: ld 3, .LC20@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -14735,18 +14453,18 @@ ; ; PWR8-LABEL: ult_12_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI121_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC21@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI121_0@toc@l +; PWR8-NEXT: ld 3, .LC21@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_12_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI121_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC21@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI121_0@toc@l +; PWR9-NEXT: ld 3, .LC21@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -14869,18 +14587,18 @@ ; ; PWR8-LABEL: ugt_12_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI122_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC22@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI122_0@toc@l +; PWR8-NEXT: ld 3, .LC22@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_12_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI122_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC22@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI122_0@toc@l +; PWR9-NEXT: ld 3, .LC22@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -15003,18 +14721,18 @@ ; ; PWR8-LABEL: ult_13_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI123_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC23@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI123_0@toc@l +; PWR8-NEXT: ld 3, .LC23@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_13_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI123_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC23@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI123_0@toc@l +; PWR9-NEXT: ld 3, .LC23@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -15137,18 +14855,18 @@ ; ; PWR8-LABEL: ugt_13_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI124_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC24@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI124_0@toc@l +; PWR8-NEXT: ld 3, .LC24@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_13_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI124_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC24@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI124_0@toc@l +; PWR9-NEXT: ld 3, .LC24@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -15271,18 +14989,18 @@ ; ; PWR8-LABEL: ult_14_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI125_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC25@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI125_0@toc@l +; PWR8-NEXT: ld 3, .LC25@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_14_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI125_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC25@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI125_0@toc@l +; PWR9-NEXT: ld 3, .LC25@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -15405,18 +15123,18 @@ ; ; PWR8-LABEL: ugt_14_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI126_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC26@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI126_0@toc@l +; PWR8-NEXT: ld 3, .LC26@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_14_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI126_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC26@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI126_0@toc@l +; PWR9-NEXT: ld 3, .LC26@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -15539,18 +15257,18 @@ ; ; PWR8-LABEL: ult_15_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI127_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC27@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI127_0@toc@l +; PWR8-NEXT: ld 3, .LC27@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_15_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI127_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC27@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI127_0@toc@l +; PWR9-NEXT: ld 3, .LC27@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -15673,18 +15391,18 @@ ; ; PWR8-LABEL: ugt_15_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI128_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC28@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI128_0@toc@l +; PWR8-NEXT: ld 3, .LC28@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_15_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI128_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC28@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI128_0@toc@l +; PWR9-NEXT: ld 3, .LC28@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -15807,18 +15525,18 @@ ; ; PWR8-LABEL: ult_16_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI129_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC29@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI129_0@toc@l +; PWR8-NEXT: ld 3, .LC29@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_16_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI129_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC29@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI129_0@toc@l +; PWR9-NEXT: ld 3, .LC29@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -15941,18 +15659,18 @@ ; ; PWR8-LABEL: ugt_16_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI130_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC30@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI130_0@toc@l +; PWR8-NEXT: ld 3, .LC30@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_16_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI130_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC30@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI130_0@toc@l +; PWR9-NEXT: ld 3, .LC30@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -16075,18 +15793,18 @@ ; ; PWR8-LABEL: ult_17_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI131_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC31@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI131_0@toc@l +; PWR8-NEXT: ld 3, .LC31@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_17_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI131_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC31@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI131_0@toc@l +; PWR9-NEXT: ld 3, .LC31@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -16209,18 +15927,18 @@ ; ; PWR8-LABEL: ugt_17_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI132_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC32@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI132_0@toc@l +; PWR8-NEXT: ld 3, .LC32@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_17_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI132_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC32@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI132_0@toc@l +; PWR9-NEXT: ld 3, .LC32@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -16343,18 +16061,18 @@ ; ; PWR8-LABEL: ult_18_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI133_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC33@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI133_0@toc@l +; PWR8-NEXT: ld 3, .LC33@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_18_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI133_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC33@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI133_0@toc@l +; PWR9-NEXT: ld 3, .LC33@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -16477,18 +16195,18 @@ ; ; PWR8-LABEL: ugt_18_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI134_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC34@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI134_0@toc@l +; PWR8-NEXT: ld 3, .LC34@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_18_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI134_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC34@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI134_0@toc@l +; PWR9-NEXT: ld 3, .LC34@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -16611,18 +16329,18 @@ ; ; PWR8-LABEL: ult_19_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI135_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC35@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI135_0@toc@l +; PWR8-NEXT: ld 3, .LC35@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_19_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI135_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC35@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI135_0@toc@l +; PWR9-NEXT: ld 3, .LC35@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -16745,18 +16463,18 @@ ; ; PWR8-LABEL: ugt_19_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI136_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC36@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI136_0@toc@l +; PWR8-NEXT: ld 3, .LC36@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_19_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI136_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC36@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI136_0@toc@l +; PWR9-NEXT: ld 3, .LC36@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -16879,18 +16597,18 @@ ; ; PWR8-LABEL: ult_20_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI137_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC37@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI137_0@toc@l +; PWR8-NEXT: ld 3, .LC37@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_20_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI137_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC37@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI137_0@toc@l +; PWR9-NEXT: ld 3, .LC37@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -17013,18 +16731,18 @@ ; ; PWR8-LABEL: ugt_20_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI138_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC38@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI138_0@toc@l +; PWR8-NEXT: ld 3, .LC38@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_20_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI138_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC38@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI138_0@toc@l +; PWR9-NEXT: ld 3, .LC38@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -17147,18 +16865,18 @@ ; ; PWR8-LABEL: ult_21_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI139_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC39@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI139_0@toc@l +; PWR8-NEXT: ld 3, .LC39@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_21_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI139_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC39@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI139_0@toc@l +; PWR9-NEXT: ld 3, .LC39@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -17281,18 +16999,18 @@ ; ; PWR8-LABEL: ugt_21_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI140_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC40@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI140_0@toc@l +; PWR8-NEXT: ld 3, .LC40@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_21_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI140_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC40@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI140_0@toc@l +; PWR9-NEXT: ld 3, .LC40@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -17415,18 +17133,18 @@ ; ; PWR8-LABEL: ult_22_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI141_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC41@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI141_0@toc@l +; PWR8-NEXT: ld 3, .LC41@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_22_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI141_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC41@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI141_0@toc@l +; PWR9-NEXT: ld 3, .LC41@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -17549,18 +17267,18 @@ ; ; PWR8-LABEL: ugt_22_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI142_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC42@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI142_0@toc@l +; PWR8-NEXT: ld 3, .LC42@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_22_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI142_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC42@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI142_0@toc@l +; PWR9-NEXT: ld 3, .LC42@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -17683,18 +17401,18 @@ ; ; PWR8-LABEL: ult_23_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI143_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC43@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI143_0@toc@l +; PWR8-NEXT: ld 3, .LC43@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_23_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI143_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC43@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI143_0@toc@l +; PWR9-NEXT: ld 3, .LC43@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -17817,18 +17535,18 @@ ; ; PWR8-LABEL: ugt_23_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI144_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC44@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI144_0@toc@l +; PWR8-NEXT: ld 3, .LC44@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_23_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI144_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC44@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI144_0@toc@l +; PWR9-NEXT: ld 3, .LC44@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -17951,18 +17669,18 @@ ; ; PWR8-LABEL: ult_24_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI145_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC45@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI145_0@toc@l +; PWR8-NEXT: ld 3, .LC45@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_24_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI145_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC45@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI145_0@toc@l +; PWR9-NEXT: ld 3, .LC45@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -18085,18 +17803,18 @@ ; ; PWR8-LABEL: ugt_24_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI146_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC46@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI146_0@toc@l +; PWR8-NEXT: ld 3, .LC46@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_24_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI146_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC46@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI146_0@toc@l +; PWR9-NEXT: ld 3, .LC46@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -18219,18 +17937,18 @@ ; ; PWR8-LABEL: ult_25_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI147_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC47@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI147_0@toc@l +; PWR8-NEXT: ld 3, .LC47@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_25_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI147_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC47@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI147_0@toc@l +; PWR9-NEXT: ld 3, .LC47@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -18353,18 +18071,18 @@ ; ; PWR8-LABEL: ugt_25_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI148_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC48@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI148_0@toc@l +; PWR8-NEXT: ld 3, .LC48@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_25_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI148_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC48@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI148_0@toc@l +; PWR9-NEXT: ld 3, .LC48@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -18487,18 +18205,18 @@ ; ; PWR8-LABEL: ult_26_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI149_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC49@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI149_0@toc@l +; PWR8-NEXT: ld 3, .LC49@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_26_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI149_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC49@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI149_0@toc@l +; PWR9-NEXT: ld 3, .LC49@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -18621,18 +18339,18 @@ ; ; PWR8-LABEL: ugt_26_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI150_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC50@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI150_0@toc@l +; PWR8-NEXT: ld 3, .LC50@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_26_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI150_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC50@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI150_0@toc@l +; PWR9-NEXT: ld 3, .LC50@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -18755,18 +18473,18 @@ ; ; PWR8-LABEL: ult_27_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI151_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC51@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI151_0@toc@l +; PWR8-NEXT: ld 3, .LC51@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_27_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI151_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC51@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI151_0@toc@l +; PWR9-NEXT: ld 3, .LC51@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -18889,18 +18607,18 @@ ; ; PWR8-LABEL: ugt_27_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI152_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC52@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI152_0@toc@l +; PWR8-NEXT: ld 3, .LC52@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_27_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI152_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC52@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI152_0@toc@l +; PWR9-NEXT: ld 3, .LC52@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -19023,18 +18741,18 @@ ; ; PWR8-LABEL: ult_28_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI153_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC53@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI153_0@toc@l +; PWR8-NEXT: ld 3, .LC53@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_28_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI153_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC53@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI153_0@toc@l +; PWR9-NEXT: ld 3, .LC53@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -19157,18 +18875,18 @@ ; ; PWR8-LABEL: ugt_28_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI154_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC54@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI154_0@toc@l +; PWR8-NEXT: ld 3, .LC54@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_28_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI154_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC54@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI154_0@toc@l +; PWR9-NEXT: ld 3, .LC54@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -19291,18 +19009,18 @@ ; ; PWR8-LABEL: ult_29_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI155_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC55@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI155_0@toc@l +; PWR8-NEXT: ld 3, .LC55@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_29_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI155_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC55@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI155_0@toc@l +; PWR9-NEXT: ld 3, .LC55@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -19425,18 +19143,18 @@ ; ; PWR8-LABEL: ugt_29_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI156_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC56@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI156_0@toc@l +; PWR8-NEXT: ld 3, .LC56@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_29_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI156_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC56@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI156_0@toc@l +; PWR9-NEXT: ld 3, .LC56@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -19559,18 +19277,18 @@ ; ; PWR8-LABEL: ult_30_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI157_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC57@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI157_0@toc@l +; PWR8-NEXT: ld 3, .LC57@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_30_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI157_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC57@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI157_0@toc@l +; PWR9-NEXT: ld 3, .LC57@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -19693,18 +19411,18 @@ ; ; PWR8-LABEL: ugt_30_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI158_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC58@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI158_0@toc@l +; PWR8-NEXT: ld 3, .LC58@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_30_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI158_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC58@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI158_0@toc@l +; PWR9-NEXT: ld 3, .LC58@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -19827,18 +19545,18 @@ ; ; PWR8-LABEL: ult_31_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI159_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC59@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI159_0@toc@l +; PWR8-NEXT: ld 3, .LC59@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_31_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI159_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC59@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI159_0@toc@l +; PWR9-NEXT: ld 3, .LC59@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -19961,18 +19679,18 @@ ; ; PWR8-LABEL: ugt_31_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI160_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC60@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI160_0@toc@l +; PWR8-NEXT: ld 3, .LC60@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_31_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI160_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC60@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI160_0@toc@l +; PWR9-NEXT: ld 3, .LC60@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -20095,18 +19813,18 @@ ; ; PWR8-LABEL: ult_32_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI161_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC61@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI161_0@toc@l +; PWR8-NEXT: ld 3, .LC61@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_32_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI161_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC61@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI161_0@toc@l +; PWR9-NEXT: ld 3, .LC61@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -20229,18 +19947,18 @@ ; ; PWR8-LABEL: ugt_32_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI162_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC62@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI162_0@toc@l +; PWR8-NEXT: ld 3, .LC62@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_32_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI162_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC62@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI162_0@toc@l +; PWR9-NEXT: ld 3, .LC62@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -20363,18 +20081,18 @@ ; ; PWR8-LABEL: ult_33_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI163_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC63@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI163_0@toc@l +; PWR8-NEXT: ld 3, .LC63@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_33_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI163_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC63@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI163_0@toc@l +; PWR9-NEXT: ld 3, .LC63@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -20497,18 +20215,18 @@ ; ; PWR8-LABEL: ugt_33_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI164_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC64@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI164_0@toc@l +; PWR8-NEXT: ld 3, .LC64@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_33_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI164_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC64@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI164_0@toc@l +; PWR9-NEXT: ld 3, .LC64@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -20631,18 +20349,18 @@ ; ; PWR8-LABEL: ult_34_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI165_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC65@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI165_0@toc@l +; PWR8-NEXT: ld 3, .LC65@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_34_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI165_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC65@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI165_0@toc@l +; PWR9-NEXT: ld 3, .LC65@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -20765,18 +20483,18 @@ ; ; PWR8-LABEL: ugt_34_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI166_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC66@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI166_0@toc@l +; PWR8-NEXT: ld 3, .LC66@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_34_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI166_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC66@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI166_0@toc@l +; PWR9-NEXT: ld 3, .LC66@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -20899,18 +20617,18 @@ ; ; PWR8-LABEL: ult_35_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI167_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC67@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI167_0@toc@l +; PWR8-NEXT: ld 3, .LC67@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_35_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI167_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC67@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI167_0@toc@l +; PWR9-NEXT: ld 3, .LC67@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -21033,18 +20751,18 @@ ; ; PWR8-LABEL: ugt_35_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI168_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC68@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI168_0@toc@l +; PWR8-NEXT: ld 3, .LC68@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_35_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI168_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC68@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI168_0@toc@l +; PWR9-NEXT: ld 3, .LC68@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -21167,18 +20885,18 @@ ; ; PWR8-LABEL: ult_36_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI169_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC69@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI169_0@toc@l +; PWR8-NEXT: ld 3, .LC69@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_36_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI169_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC69@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI169_0@toc@l +; PWR9-NEXT: ld 3, .LC69@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -21301,18 +21019,18 @@ ; ; PWR8-LABEL: ugt_36_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI170_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC70@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI170_0@toc@l +; PWR8-NEXT: ld 3, .LC70@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_36_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI170_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC70@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI170_0@toc@l +; PWR9-NEXT: ld 3, .LC70@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -21435,18 +21153,18 @@ ; ; PWR8-LABEL: ult_37_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI171_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC71@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI171_0@toc@l +; PWR8-NEXT: ld 3, .LC71@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_37_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI171_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC71@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI171_0@toc@l +; PWR9-NEXT: ld 3, .LC71@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -21569,18 +21287,18 @@ ; ; PWR8-LABEL: ugt_37_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI172_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC72@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI172_0@toc@l +; PWR8-NEXT: ld 3, .LC72@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_37_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI172_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC72@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI172_0@toc@l +; PWR9-NEXT: ld 3, .LC72@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -21703,18 +21421,18 @@ ; ; PWR8-LABEL: ult_38_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI173_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC73@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI173_0@toc@l +; PWR8-NEXT: ld 3, .LC73@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_38_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI173_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC73@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI173_0@toc@l +; PWR9-NEXT: ld 3, .LC73@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -21837,18 +21555,18 @@ ; ; PWR8-LABEL: ugt_38_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI174_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC74@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI174_0@toc@l +; PWR8-NEXT: ld 3, .LC74@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_38_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI174_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC74@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI174_0@toc@l +; PWR9-NEXT: ld 3, .LC74@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -21971,18 +21689,18 @@ ; ; PWR8-LABEL: ult_39_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI175_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC75@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI175_0@toc@l +; PWR8-NEXT: ld 3, .LC75@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_39_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI175_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC75@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI175_0@toc@l +; PWR9-NEXT: ld 3, .LC75@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -22105,18 +21823,18 @@ ; ; PWR8-LABEL: ugt_39_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI176_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC76@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI176_0@toc@l +; PWR8-NEXT: ld 3, .LC76@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_39_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI176_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC76@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI176_0@toc@l +; PWR9-NEXT: ld 3, .LC76@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -22239,18 +21957,18 @@ ; ; PWR8-LABEL: ult_40_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI177_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC77@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI177_0@toc@l +; PWR8-NEXT: ld 3, .LC77@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_40_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI177_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC77@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI177_0@toc@l +; PWR9-NEXT: ld 3, .LC77@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -22373,18 +22091,18 @@ ; ; PWR8-LABEL: ugt_40_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI178_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC78@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI178_0@toc@l +; PWR8-NEXT: ld 3, .LC78@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_40_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI178_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC78@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI178_0@toc@l +; PWR9-NEXT: ld 3, .LC78@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -22507,18 +22225,18 @@ ; ; PWR8-LABEL: ult_41_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI179_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC79@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI179_0@toc@l +; PWR8-NEXT: ld 3, .LC79@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_41_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI179_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC79@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI179_0@toc@l +; PWR9-NEXT: ld 3, .LC79@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -22641,18 +22359,18 @@ ; ; PWR8-LABEL: ugt_41_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI180_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC80@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI180_0@toc@l +; PWR8-NEXT: ld 3, .LC80@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_41_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI180_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC80@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI180_0@toc@l +; PWR9-NEXT: ld 3, .LC80@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -22775,18 +22493,18 @@ ; ; PWR8-LABEL: ult_42_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI181_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC81@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI181_0@toc@l +; PWR8-NEXT: ld 3, .LC81@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_42_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI181_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC81@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI181_0@toc@l +; PWR9-NEXT: ld 3, .LC81@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -22909,18 +22627,18 @@ ; ; PWR8-LABEL: ugt_42_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI182_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC82@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI182_0@toc@l +; PWR8-NEXT: ld 3, .LC82@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_42_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI182_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC82@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI182_0@toc@l +; PWR9-NEXT: ld 3, .LC82@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -23043,18 +22761,18 @@ ; ; PWR8-LABEL: ult_43_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI183_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC83@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI183_0@toc@l +; PWR8-NEXT: ld 3, .LC83@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_43_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI183_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC83@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI183_0@toc@l +; PWR9-NEXT: ld 3, .LC83@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -23177,18 +22895,18 @@ ; ; PWR8-LABEL: ugt_43_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI184_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC84@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI184_0@toc@l +; PWR8-NEXT: ld 3, .LC84@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_43_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI184_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC84@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI184_0@toc@l +; PWR9-NEXT: ld 3, .LC84@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -23311,18 +23029,18 @@ ; ; PWR8-LABEL: ult_44_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI185_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC85@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI185_0@toc@l +; PWR8-NEXT: ld 3, .LC85@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_44_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI185_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC85@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI185_0@toc@l +; PWR9-NEXT: ld 3, .LC85@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -23445,18 +23163,18 @@ ; ; PWR8-LABEL: ugt_44_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI186_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC86@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI186_0@toc@l +; PWR8-NEXT: ld 3, .LC86@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_44_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI186_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC86@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI186_0@toc@l +; PWR9-NEXT: ld 3, .LC86@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -23579,18 +23297,18 @@ ; ; PWR8-LABEL: ult_45_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI187_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC87@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI187_0@toc@l +; PWR8-NEXT: ld 3, .LC87@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_45_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI187_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC87@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI187_0@toc@l +; PWR9-NEXT: ld 3, .LC87@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -23713,18 +23431,18 @@ ; ; PWR8-LABEL: ugt_45_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI188_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC88@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI188_0@toc@l +; PWR8-NEXT: ld 3, .LC88@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_45_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI188_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC88@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI188_0@toc@l +; PWR9-NEXT: ld 3, .LC88@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -23847,18 +23565,18 @@ ; ; PWR8-LABEL: ult_46_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI189_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC89@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI189_0@toc@l +; PWR8-NEXT: ld 3, .LC89@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_46_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI189_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC89@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI189_0@toc@l +; PWR9-NEXT: ld 3, .LC89@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -23981,18 +23699,18 @@ ; ; PWR8-LABEL: ugt_46_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI190_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC90@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI190_0@toc@l +; PWR8-NEXT: ld 3, .LC90@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_46_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI190_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC90@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI190_0@toc@l +; PWR9-NEXT: ld 3, .LC90@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -24115,18 +23833,18 @@ ; ; PWR8-LABEL: ult_47_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI191_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC91@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI191_0@toc@l +; PWR8-NEXT: ld 3, .LC91@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_47_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI191_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC91@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI191_0@toc@l +; PWR9-NEXT: ld 3, .LC91@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -24249,18 +23967,18 @@ ; ; PWR8-LABEL: ugt_47_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI192_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC92@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI192_0@toc@l +; PWR8-NEXT: ld 3, .LC92@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_47_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI192_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC92@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI192_0@toc@l +; PWR9-NEXT: ld 3, .LC92@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -24383,18 +24101,18 @@ ; ; PWR8-LABEL: ult_48_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI193_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC93@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI193_0@toc@l +; PWR8-NEXT: ld 3, .LC93@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_48_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI193_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC93@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI193_0@toc@l +; PWR9-NEXT: ld 3, .LC93@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -24517,18 +24235,18 @@ ; ; PWR8-LABEL: ugt_48_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI194_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC94@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI194_0@toc@l +; PWR8-NEXT: ld 3, .LC94@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_48_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI194_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC94@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI194_0@toc@l +; PWR9-NEXT: ld 3, .LC94@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -24651,18 +24369,18 @@ ; ; PWR8-LABEL: ult_49_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI195_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC95@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI195_0@toc@l +; PWR8-NEXT: ld 3, .LC95@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_49_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI195_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC95@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI195_0@toc@l +; PWR9-NEXT: ld 3, .LC95@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -24785,18 +24503,18 @@ ; ; PWR8-LABEL: ugt_49_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI196_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC96@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI196_0@toc@l +; PWR8-NEXT: ld 3, .LC96@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_49_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI196_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC96@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI196_0@toc@l +; PWR9-NEXT: ld 3, .LC96@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -24919,18 +24637,18 @@ ; ; PWR8-LABEL: ult_50_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI197_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC97@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI197_0@toc@l +; PWR8-NEXT: ld 3, .LC97@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_50_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI197_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC97@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI197_0@toc@l +; PWR9-NEXT: ld 3, .LC97@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -25053,18 +24771,18 @@ ; ; PWR8-LABEL: ugt_50_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI198_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC98@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI198_0@toc@l +; PWR8-NEXT: ld 3, .LC98@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_50_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI198_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC98@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI198_0@toc@l +; PWR9-NEXT: ld 3, .LC98@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -25187,18 +24905,18 @@ ; ; PWR8-LABEL: ult_51_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI199_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC99@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI199_0@toc@l +; PWR8-NEXT: ld 3, .LC99@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_51_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI199_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC99@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI199_0@toc@l +; PWR9-NEXT: ld 3, .LC99@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -25321,18 +25039,18 @@ ; ; PWR8-LABEL: ugt_51_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI200_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC100@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI200_0@toc@l +; PWR8-NEXT: ld 3, .LC100@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_51_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI200_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC100@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI200_0@toc@l +; PWR9-NEXT: ld 3, .LC100@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -25455,18 +25173,18 @@ ; ; PWR8-LABEL: ult_52_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI201_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC101@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI201_0@toc@l +; PWR8-NEXT: ld 3, .LC101@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_52_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI201_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC101@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI201_0@toc@l +; PWR9-NEXT: ld 3, .LC101@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -25589,18 +25307,18 @@ ; ; PWR8-LABEL: ugt_52_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI202_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC102@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI202_0@toc@l +; PWR8-NEXT: ld 3, .LC102@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_52_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI202_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC102@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI202_0@toc@l +; PWR9-NEXT: ld 3, .LC102@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -25723,18 +25441,18 @@ ; ; PWR8-LABEL: ult_53_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI203_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC103@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI203_0@toc@l +; PWR8-NEXT: ld 3, .LC103@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_53_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI203_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC103@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI203_0@toc@l +; PWR9-NEXT: ld 3, .LC103@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -25857,18 +25575,18 @@ ; ; PWR8-LABEL: ugt_53_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI204_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC104@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI204_0@toc@l +; PWR8-NEXT: ld 3, .LC104@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_53_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI204_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC104@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI204_0@toc@l +; PWR9-NEXT: ld 3, .LC104@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -25991,18 +25709,18 @@ ; ; PWR8-LABEL: ult_54_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI205_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC105@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI205_0@toc@l +; PWR8-NEXT: ld 3, .LC105@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_54_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI205_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC105@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI205_0@toc@l +; PWR9-NEXT: ld 3, .LC105@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -26125,18 +25843,18 @@ ; ; PWR8-LABEL: ugt_54_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI206_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC106@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI206_0@toc@l +; PWR8-NEXT: ld 3, .LC106@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_54_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI206_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC106@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI206_0@toc@l +; PWR9-NEXT: ld 3, .LC106@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -26259,18 +25977,18 @@ ; ; PWR8-LABEL: ult_55_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI207_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC107@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI207_0@toc@l +; PWR8-NEXT: ld 3, .LC107@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_55_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI207_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC107@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI207_0@toc@l +; PWR9-NEXT: ld 3, .LC107@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -26393,18 +26111,18 @@ ; ; PWR8-LABEL: ugt_55_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI208_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC108@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI208_0@toc@l +; PWR8-NEXT: ld 3, .LC108@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_55_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI208_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC108@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI208_0@toc@l +; PWR9-NEXT: ld 3, .LC108@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -26527,18 +26245,18 @@ ; ; PWR8-LABEL: ult_56_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI209_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC109@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI209_0@toc@l +; PWR8-NEXT: ld 3, .LC109@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_56_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI209_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC109@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI209_0@toc@l +; PWR9-NEXT: ld 3, .LC109@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -26661,18 +26379,18 @@ ; ; PWR8-LABEL: ugt_56_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI210_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC110@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI210_0@toc@l +; PWR8-NEXT: ld 3, .LC110@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_56_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI210_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC110@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI210_0@toc@l +; PWR9-NEXT: ld 3, .LC110@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -26795,18 +26513,18 @@ ; ; PWR8-LABEL: ult_57_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI211_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC111@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI211_0@toc@l +; PWR8-NEXT: ld 3, .LC111@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_57_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI211_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC111@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI211_0@toc@l +; PWR9-NEXT: ld 3, .LC111@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -26929,18 +26647,18 @@ ; ; PWR8-LABEL: ugt_57_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI212_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC112@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI212_0@toc@l +; PWR8-NEXT: ld 3, .LC112@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_57_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI212_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC112@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI212_0@toc@l +; PWR9-NEXT: ld 3, .LC112@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -27063,18 +26781,18 @@ ; ; PWR8-LABEL: ult_58_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI213_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC113@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI213_0@toc@l +; PWR8-NEXT: ld 3, .LC113@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_58_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI213_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC113@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI213_0@toc@l +; PWR9-NEXT: ld 3, .LC113@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -27197,18 +26915,18 @@ ; ; PWR8-LABEL: ugt_58_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI214_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC114@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI214_0@toc@l +; PWR8-NEXT: ld 3, .LC114@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_58_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI214_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC114@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI214_0@toc@l +; PWR9-NEXT: ld 3, .LC114@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -27331,18 +27049,18 @@ ; ; PWR8-LABEL: ult_59_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI215_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC115@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI215_0@toc@l +; PWR8-NEXT: ld 3, .LC115@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_59_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI215_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC115@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI215_0@toc@l +; PWR9-NEXT: ld 3, .LC115@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -27465,18 +27183,18 @@ ; ; PWR8-LABEL: ugt_59_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI216_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC116@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI216_0@toc@l +; PWR8-NEXT: ld 3, .LC116@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_59_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI216_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC116@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI216_0@toc@l +; PWR9-NEXT: ld 3, .LC116@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -27599,18 +27317,18 @@ ; ; PWR8-LABEL: ult_60_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI217_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC117@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI217_0@toc@l +; PWR8-NEXT: ld 3, .LC117@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_60_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI217_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC117@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI217_0@toc@l +; PWR9-NEXT: ld 3, .LC117@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -27733,18 +27451,18 @@ ; ; PWR8-LABEL: ugt_60_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI218_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC118@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI218_0@toc@l +; PWR8-NEXT: ld 3, .LC118@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_60_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI218_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC118@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI218_0@toc@l +; PWR9-NEXT: ld 3, .LC118@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -27867,18 +27585,18 @@ ; ; PWR8-LABEL: ult_61_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI219_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC119@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI219_0@toc@l +; PWR8-NEXT: ld 3, .LC119@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_61_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI219_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC119@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI219_0@toc@l +; PWR9-NEXT: ld 3, .LC119@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -28001,18 +27719,18 @@ ; ; PWR8-LABEL: ugt_61_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI220_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC120@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI220_0@toc@l +; PWR8-NEXT: ld 3, .LC120@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_61_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI220_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC120@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI220_0@toc@l +; PWR9-NEXT: ld 3, .LC120@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -28135,18 +27853,18 @@ ; ; PWR8-LABEL: ult_62_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI221_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC121@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI221_0@toc@l +; PWR8-NEXT: ld 3, .LC121@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_62_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI221_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC121@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI221_0@toc@l +; PWR9-NEXT: ld 3, .LC121@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr @@ -28269,18 +27987,18 @@ ; ; PWR8-LABEL: ugt_62_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI222_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC122@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI222_0@toc@l +; PWR8-NEXT: ld 3, .LC122@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_62_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI222_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC122@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI222_0@toc@l +; PWR9-NEXT: ld 3, .LC122@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr @@ -28403,18 +28121,18 @@ ; ; PWR8-LABEL: ult_63_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI223_0@toc@ha +; PWR8-NEXT: addis 3, 2, .LC123@toc@ha ; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI223_0@toc@l +; PWR8-NEXT: ld 3, .LC123@toc@l(3) ; PWR8-NEXT: lxvd2x 35, 0, 3 ; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_63_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: addis 3, 2, .LCPI223_0@toc@ha +; PWR9-NEXT: addis 3, 2, .LC123@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: addi 3, 3, .LCPI223_0@toc@l +; PWR9-NEXT: ld 3, .LC123@toc@l(3) ; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vector-rotates.ll b/llvm/test/CodeGen/PowerPC/vector-rotates.ll --- a/llvm/test/CodeGen/PowerPC/vector-rotates.ll +++ b/llvm/test/CodeGen/PowerPC/vector-rotates.ll @@ -9,16 +9,16 @@ define <16 x i8> @rotl_v16i8(<16 x i8> %a) { ; CHECK-P8-LABEL: rotl_v16i8: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vrlb v2, v2, v3 ; CHECK-P8-NEXT: blr ; ; CHECK-P7-LABEL: rotl_v16i8: ; CHECK-P7: # %bb.0: # %entry -; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-P7-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-P7-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: vrlb v2, v2, v3 ; CHECK-P7-NEXT: blr @@ -32,16 +32,16 @@ define <8 x i16> @rotl_v8i16(<8 x i16> %a) { ; CHECK-P8-LABEL: rotl_v8i16: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-P8-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vrlh v2, v2, v3 ; CHECK-P8-NEXT: blr ; ; CHECK-P7-LABEL: rotl_v8i16: ; CHECK-P7: # %bb.0: # %entry -; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-P7-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-P7-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: vrlh v2, v2, v3 ; CHECK-P7-NEXT: blr @@ -55,16 +55,16 @@ define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) { ; CHECK-P8-LABEL: rotl_v4i32_0: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-P8-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: vrlw v2, v2, v3 ; CHECK-P8-NEXT: blr ; ; CHECK-P7-LABEL: rotl_v4i32_0: ; CHECK-P7: # %bb.0: # %entry -; CHECK-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-P7-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-P7-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: vrlw v2, v2, v3 ; CHECK-P7-NEXT: blr @@ -101,8 +101,8 @@ define <2 x i64> @rotl_v2i64(<2 x i64> %a) { ; CHECK-P8-LABEL: rotl_v2i64: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-P8-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-P8-NEXT: addis r3, r2, .LC3@toc@ha +; CHECK-P8-NEXT: ld r3, .LC3@toc@l(r3) ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: xxswapd vs35, vs0 ; CHECK-P8-NEXT: vrld v2, v2, v3 diff --git a/llvm/test/CodeGen/PowerPC/vperm-lowering.ll b/llvm/test/CodeGen/PowerPC/vperm-lowering.ll --- a/llvm/test/CodeGen/PowerPC/vperm-lowering.ll +++ b/llvm/test/CodeGen/PowerPC/vperm-lowering.ll @@ -26,6 +26,8 @@ ; CHECK: .byte 6 ; CHECK: .byte 11 ; CHECK: foo: -; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_0@toc@ha -; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_0@toc@l +; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha +; CHECK: ld [[REG2:[0-9]+]], .LC0@toc@l([[REG1]]) ; CHECK: lvx [[REG3:[0-9]+]], 0, [[REG2]] +; CHECK: .LC0: +; CHECK: .tc .LCPI0_0[TC],.LCPI0_0 diff --git a/llvm/test/CodeGen/PowerPC/vselect-constants.ll b/llvm/test/CodeGen/PowerPC/vselect-constants.ll --- a/llvm/test/CodeGen/PowerPC/vselect-constants.ll +++ b/llvm/test/CodeGen/PowerPC/vselect-constants.ll @@ -12,15 +12,14 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 -; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l -; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: vsubuwm 3, 4, 3 -; CHECK-NEXT: lvx 4, 0, 4 +; CHECK-NEXT: lvx 4, 0, 3 ; CHECK-NEXT: vslw 2, 2, 3 ; CHECK-NEXT: vsraw 2, 2, 3 -; CHECK-NEXT: lvx 3, 0, 3 +; CHECK-NEXT: lvx 3, 3, 4 ; CHECK-NEXT: xxsel 34, 36, 35, 34 ; CHECK-NEXT: blr %add = select <4 x i1> %cond, <4 x i32> , <4 x i32> @@ -30,13 +29,12 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_C1_or_C2_vec: ; CHECK: # %bb.0: +; CHECK-NEXT: addis 3, 2, .LC1@toc@ha ; CHECK-NEXT: vcmpequw 2, 2, 3 -; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l -; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l -; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: lvx 4, 0, 4 +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: ld 3, .LC1@toc@l(3) +; CHECK-NEXT: lvx 3, 3, 4 +; CHECK-NEXT: lvx 4, 0, 3 ; CHECK-NEXT: xxsel 34, 36, 35, 34 ; CHECK-NEXT: blr %cond = icmp eq <4 x i32> %x, %y @@ -47,9 +45,9 @@ define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_Cplus1_or_C_vec: ; CHECK: # %bb.0: +; CHECK-NEXT: addis 3, 2, .LC2@toc@ha ; CHECK-NEXT: vspltisw 3, 1 -; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l +; CHECK-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduwm 2, 2, 3 @@ -61,9 +59,9 @@ define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec: ; CHECK: # %bb.0: +; CHECK-NEXT: addis 3, 2, .LC3@toc@ha ; CHECK-NEXT: vcmpequw 2, 2, 3 -; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l +; CHECK-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vsubuwm 2, 3, 2 ; CHECK-NEXT: blr @@ -77,8 +75,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 -; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l +; CHECK-NEXT: addis 3, 2, .LC4@toc@ha +; CHECK-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vslw 2, 2, 3 ; CHECK-NEXT: vsraw 2, 2, 3 @@ -92,9 +90,9 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec: ; CHECK: # %bb.0: +; CHECK-NEXT: addis 3, 2, .LC5@toc@ha ; CHECK-NEXT: vcmpequw 2, 2, 3 -; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l +; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -2220,8 +2220,8 @@ define <2 x double> @test69(<2 x i16> %a) { ; CHECK-LABEL: test69: ; CHECK: # %bb.0: -; CHECK-NEXT: addis r3, r2, .LCPI63_0@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI63_0@toc@l +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NEXT: lxvw4x v3, 0, r3 ; CHECK-NEXT: addi r3, r1, -32 ; CHECK-NEXT: vperm v2, v2, v2, v3 @@ -2237,8 +2237,8 @@ ; ; CHECK-REG-LABEL: test69: ; CHECK-REG: # %bb.0: -; CHECK-REG-NEXT: addis r3, r2, .LCPI63_0@toc@ha -; CHECK-REG-NEXT: addi r3, r3, .LCPI63_0@toc@l +; CHECK-REG-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-REG-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-REG-NEXT: lxvw4x v3, 0, r3 ; CHECK-REG-NEXT: addi r3, r1, -32 ; CHECK-REG-NEXT: vperm v2, v2, v2, v3 @@ -2254,8 +2254,8 @@ ; ; CHECK-FISL-LABEL: test69: ; CHECK-FISL: # %bb.0: -; CHECK-FISL-NEXT: addis r3, r2, .LCPI63_0@toc@ha -; CHECK-FISL-NEXT: addi r3, r3, .LCPI63_0@toc@l +; CHECK-FISL-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-FISL-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3 ; CHECK-FISL-NEXT: vperm v2, v2, v2, v3 ; CHECK-FISL-NEXT: xxlor vs0, v2, v2 @@ -2272,13 +2272,13 @@ ; ; CHECK-LE-LABEL: test69: ; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: addis r3, r2, .LCPI63_0@toc@ha -; CHECK-LE-NEXT: addi r3, r3, .LCPI63_0@toc@l +; CHECK-LE-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-LE-NEXT: addis r4, r2, .LC1@toc@ha +; CHECK-LE-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-LE-NEXT: lvx v3, 0, r3 -; CHECK-LE-NEXT: addis r3, r2, .LCPI63_1@toc@ha -; CHECK-LE-NEXT: addi r3, r3, .LCPI63_1@toc@l -; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 +; CHECK-LE-NEXT: ld r3, .LC1@toc@l(r4) ; CHECK-LE-NEXT: vperm v2, v2, v2, v3 +; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 ; CHECK-LE-NEXT: xxswapd v3, vs0 ; CHECK-LE-NEXT: vsld v2, v2, v3 ; CHECK-LE-NEXT: vsrad v2, v2, v3 @@ -2294,8 +2294,8 @@ define <2 x double> @test70(<2 x i8> %a) { ; CHECK-LABEL: test70: ; CHECK: # %bb.0: -; CHECK-NEXT: addis r3, r2, .LCPI64_0@toc@ha -; CHECK-NEXT: addi r3, r3, .LCPI64_0@toc@l +; CHECK-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-NEXT: lxvw4x v3, 0, r3 ; CHECK-NEXT: addi r3, r1, -32 ; CHECK-NEXT: vperm v2, v2, v2, v3 @@ -2313,8 +2313,8 @@ ; ; CHECK-REG-LABEL: test70: ; CHECK-REG: # %bb.0: -; CHECK-REG-NEXT: addis r3, r2, .LCPI64_0@toc@ha -; CHECK-REG-NEXT: addi r3, r3, .LCPI64_0@toc@l +; CHECK-REG-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-REG-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-REG-NEXT: lxvw4x v3, 0, r3 ; CHECK-REG-NEXT: addi r3, r1, -32 ; CHECK-REG-NEXT: vperm v2, v2, v2, v3 @@ -2332,8 +2332,8 @@ ; ; CHECK-FISL-LABEL: test70: ; CHECK-FISL: # %bb.0: -; CHECK-FISL-NEXT: addis r3, r2, .LCPI64_0@toc@ha -; CHECK-FISL-NEXT: addi r3, r3, .LCPI64_0@toc@l +; CHECK-FISL-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-FISL-NEXT: ld r3, .LC1@toc@l(r3) ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3 ; CHECK-FISL-NEXT: vperm v2, v2, v2, v3 ; CHECK-FISL-NEXT: xxlor vs0, v2, v2 @@ -2352,13 +2352,13 @@ ; ; CHECK-LE-LABEL: test70: ; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: addis r3, r2, .LCPI64_0@toc@ha -; CHECK-LE-NEXT: addi r3, r3, .LCPI64_0@toc@l +; CHECK-LE-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-LE-NEXT: addis r4, r2, .LC3@toc@ha +; CHECK-LE-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-LE-NEXT: lvx v3, 0, r3 -; CHECK-LE-NEXT: addis r3, r2, .LCPI64_1@toc@ha -; CHECK-LE-NEXT: addi r3, r3, .LCPI64_1@toc@l -; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 +; CHECK-LE-NEXT: ld r3, .LC3@toc@l(r4) ; CHECK-LE-NEXT: vperm v2, v2, v2, v3 +; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 ; CHECK-LE-NEXT: xxswapd v3, vs0 ; CHECK-LE-NEXT: vsld v2, v2, v3 ; CHECK-LE-NEXT: vsrad v2, v2, v3 @@ -2376,11 +2376,11 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi r4, r1, -16 ; CHECK-NEXT: stw r3, -16(r1) -; CHECK-NEXT: addis r3, r2, .LCPI65_0@toc@ha +; CHECK-NEXT: addis r3, r2, .LC2@toc@ha ; CHECK-NEXT: lxvw4x vs0, 0, r4 -; CHECK-NEXT: addi r3, r3, .LCPI65_0@toc@l -; CHECK-NEXT: lxvw4x v3, 0, r3 +; CHECK-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-NEXT: xxspltw v2, vs0, 0 +; CHECK-NEXT: lxvw4x v3, 0, r3 ; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: blr ; @@ -2388,11 +2388,11 @@ ; CHECK-REG: # %bb.0: ; CHECK-REG-NEXT: addi r4, r1, -16 ; CHECK-REG-NEXT: stw r3, -16(r1) -; CHECK-REG-NEXT: addis r3, r2, .LCPI65_0@toc@ha +; CHECK-REG-NEXT: addis r3, r2, .LC2@toc@ha ; CHECK-REG-NEXT: lxvw4x vs0, 0, r4 -; CHECK-REG-NEXT: addi r3, r3, .LCPI65_0@toc@l -; CHECK-REG-NEXT: lxvw4x v3, 0, r3 +; CHECK-REG-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-REG-NEXT: xxspltw v2, vs0, 0 +; CHECK-REG-NEXT: lxvw4x v3, 0, r3 ; CHECK-REG-NEXT: vadduwm v2, v2, v3 ; CHECK-REG-NEXT: blr ; @@ -2403,17 +2403,17 @@ ; CHECK-FISL-NEXT: addi r3, r1, -16 ; CHECK-FISL-NEXT: lxvw4x vs0, 0, r3 ; CHECK-FISL-NEXT: xxspltw v2, vs0, 0 -; CHECK-FISL-NEXT: addis r3, r2, .LCPI65_0@toc@ha -; CHECK-FISL-NEXT: addi r3, r3, .LCPI65_0@toc@l +; CHECK-FISL-NEXT: addis r3, r2, .LC2@toc@ha +; CHECK-FISL-NEXT: ld r3, .LC2@toc@l(r3) ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3 ; CHECK-FISL-NEXT: vadduwm v2, v2, v3 ; CHECK-FISL-NEXT: blr ; ; CHECK-LE-LABEL: test80: ; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: addis r4, r2, .LC4@toc@ha ; CHECK-LE-NEXT: mtfprwz f0, r3 -; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha -; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l +; CHECK-LE-NEXT: ld r3, .LC4@toc@l(r4) ; CHECK-LE-NEXT: xxspltw v2, vs0, 1 ; CHECK-LE-NEXT: lvx v3, 0, r3 ; CHECK-LE-NEXT: vadduwm v2, v2, v3