diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td --- a/llvm/test/TableGen/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter.td @@ -70,7 +70,7 @@ // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL // CHECK-NEXT: mutable MatcherState State; // CHECK-NEXT: typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; -// CHECK-NEXT: typedef void(MyTargetInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const; +// CHECK-NEXT: typedef void(MyTargetInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; // CHECK-NEXT: const ISelInfoTy ISelInfo; // CHECK-NEXT: static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; // CHECK-NEXT: static MyTargetInstructionSelector::CustomRendererFn CustomRenderers[]; diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -1980,7 +1980,7 @@ } CvtOS << " unsigned OpIdx;\n"; CvtOS << " Inst.setOpcode(Opcode);\n"; - CvtOS << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"; + CvtOS << " for (const uint8_t *p = Converter; *p; p += 2) {\n"; if (HasOptionalOperands) { CvtOS << " OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n"; } else { @@ -1990,14 +1990,14 @@ CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n"; CvtOS << " case CVT_Reg:\n"; CvtOS << " static_cast<" << TargetOperandClass - << "&>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n"; + << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n"; CvtOS << " break;\n"; CvtOS << " case CVT_Tied: {\n"; CvtOS << " assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n"; - CvtOS << " std::begin(TiedAsmOperandTable)) &&\n"; + CvtOS << " std::begin(TiedAsmOperandTable)) &&\n"; CvtOS << " \"Tied operand not found\");\n"; CvtOS << " unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];\n"; - CvtOS << " if (TiedResOpnd != (uint8_t) -1)\n"; + CvtOS << " if (TiedResOpnd != (uint8_t)-1)\n"; CvtOS << " Inst.addOperand(Inst.getOperand(TiedResOpnd));\n"; CvtOS << " break;\n"; CvtOS << " }\n"; @@ -2012,7 +2012,7 @@ << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" << " unsigned NumMCOperands = 0;\n" << " const uint8_t *Converter = ConversionTable[Kind];\n" - << " for (const uint8_t *p = Converter; *p; p+= 2) {\n" + << " for (const uint8_t *p = Converter; *p; p += 2) {\n" << " switch (*p) {\n" << " default: llvm_unreachable(\"invalid conversion entry!\");\n" << " case CVT_Reg:\n" @@ -2129,12 +2129,12 @@ << OpInfo.MINumOperands << ");\n" << " } else {\n" << " static_cast<" << TargetOperandClass - << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod + << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands << ");\n" << " }\n"; } else { CvtOS << " static_cast<" << TargetOperandClass - << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod + << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands << ");\n"; } CvtOS << " break;\n"; @@ -2448,7 +2448,7 @@ OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, " << "MatchClassKind Kind) {\n"; OS << " " << Info.Target.getName() << "Operand &Operand = (" - << Info.Target.getName() << "Operand&)GOp;\n"; + << Info.Target.getName() << "Operand &)GOp;\n"; // The InvalidMatchClass is not to match any operand. OS << " if (Kind == InvalidMatchClass)\n"; @@ -2811,7 +2811,7 @@ Record *AsmVariant = Target.getAsmParserVariant(VC); int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant"); StringRef AsmParserVariantName = AsmVariant->getValueAsString("Name"); - OS << " case " << AsmParserVariantNo << ":\n"; + OS << " case " << AsmParserVariantNo << ":\n"; emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2, AsmParserVariantName); OS << " break;\n"; @@ -2978,7 +2978,7 @@ "FeatureBitsets[it->RequiredFeaturesIdx];\n"; OS << " if (!ParseForAllFeatures && (AvailableFeatures & " "RequiredFeatures) != RequiredFeatures)\n"; - OS << " continue;\n\n"; + OS << " continue;\n\n"; // Emit check to ensure the operand number matches. OS << " // check if the operand in question has a custom parser.\n"; @@ -3011,10 +3011,10 @@ OS << " uint64_t &ErrorInfo) {\n"; OS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"; OS << " const uint8_t *Converter = ConversionTable[Kind];\n"; - OS << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"; + OS << " for (const uint8_t *p = Converter; *p; p += 2) {\n"; OS << " switch (*p) {\n"; OS << " case CVT_Tied: {\n"; - OS << " unsigned OpIdx = *(p+1);\n"; + OS << " unsigned OpIdx = *(p + 1);\n"; OS << " assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n"; OS << " std::begin(TiedAsmOperandTable)) &&\n"; OS << " \"Tied operand not found\");\n"; @@ -3086,7 +3086,7 @@ OS << "\n"; OS << " std::string Res = \", did you mean: \";\n"; OS << " unsigned i = 0;\n"; - OS << " for( ; i < Candidates.size() - 1; i++)\n"; + OS << " for (; i < Candidates.size() - 1; i++)\n"; OS << " Res += Candidates[i].str() + \", \";\n"; OS << " return Res + Candidates[i].str() + \"?\";\n"; } @@ -3255,7 +3255,7 @@ OS << "#undef GET_ASSEMBLER_HEADER\n"; OS << " // This should be included into the middle of the declaration of\n"; OS << " // your subclasses implementation of MCTargetAsmParser.\n"; - OS << " FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;\n"; + OS << " FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;\n"; if (HasOptionalOperands) { OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, " << "unsigned Opcode,\n" @@ -3559,12 +3559,12 @@ OS << " // Get the instruction mnemonic, which is the first token.\n"; if (HasMnemonicFirst) { OS << " StringRef Mnemonic = ((" << Target.getName() - << "Operand&)*Operands[0]).getToken();\n\n"; + << "Operand &)*Operands[0]).getToken();\n\n"; } else { OS << " StringRef Mnemonic;\n"; OS << " if (Operands[0]->isToken())\n"; OS << " Mnemonic = ((" << Target.getName() - << "Operand&)*Operands[0]).getToken();\n\n"; + << "Operand &)*Operands[0]).getToken();\n\n"; } if (HasMnemonicAliases) { @@ -3614,7 +3614,7 @@ } OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" <<\n" - << " std::distance(MnemonicRange.first, MnemonicRange.second) << \n" + << " std::distance(MnemonicRange.first, MnemonicRange.second) <<\n" << " \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n"; OS << " // Return a more specific error code if no mnemonics match.\n"; @@ -3789,10 +3789,10 @@ OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & " "~AvailableFeatures;\n"; OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target features:\";\n"; - OS << " for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)\n"; - OS << " if (NewMissingFeatures[I])\n"; - OS << " dbgs() << ' ' << I;\n"; - OS << " dbgs() << \"\\n\");\n"; + OS << " for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)\n"; + OS << " if (NewMissingFeatures[I])\n"; + OS << " dbgs() << ' ' << I;\n"; + OS << " dbgs() << \"\\n\");\n"; if (ReportMultipleNearMisses) { OS << " FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);\n"; } else { @@ -3927,7 +3927,7 @@ OS << " getTargetOptions().MCNoDeprecatedWarn &&\n"; OS << " MII.getDeprecatedInfo(Inst, getSTI(), Info)) {\n"; OS << " SMLoc Loc = ((" << Target.getName() - << "Operand&)*Operands[0]).getStartLoc();\n"; + << "Operand &)*Operands[0]).getStartLoc();\n"; OS << " getParser().Warning(Loc, Info, None);\n"; OS << " }\n"; } diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -443,7 +443,7 @@ // Emit the starting string. O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" - << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; + << " O << AsmStrs + (Bits & " << (1 << AsmStrBits)-1 << ") - 1;\n\n"; // Output the table driven operand information. BitsLeft = OpcodeInfoBits-AsmStrBits; diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp --- a/llvm/utils/TableGen/CallingConvEmitter.cpp +++ b/llvm/utils/TableGen/CallingConvEmitter.cpp @@ -85,7 +85,7 @@ EmitAction(CCActions->getElementAsRecord(i), 2, O); } - O << "\n return true; // CC didn't match.\n"; + O << "\n return true; // CC didn't match.\n"; O << "}\n"; } @@ -238,11 +238,11 @@ O << IndentStr << "LocInfo = CCValAssign::FPExt;\n"; } else { O << IndentStr << "if (ArgFlags.isSExt())\n" - << IndentStr << IndentStr << "LocInfo = CCValAssign::SExt;\n" + << IndentStr << " LocInfo = CCValAssign::SExt;\n" << IndentStr << "else if (ArgFlags.isZExt())\n" - << IndentStr << IndentStr << "LocInfo = CCValAssign::ZExt;\n" + << IndentStr << " LocInfo = CCValAssign::ZExt;\n" << IndentStr << "else\n" - << IndentStr << IndentStr << "LocInfo = CCValAssign::AExt;\n"; + << IndentStr << " LocInfo = CCValAssign::AExt;\n"; } } else if (Action->isSubClassOf("CCPromoteToUpperBitsInType")) { Record *DestTy = Action->getValueAsDef("DestTy"); @@ -254,11 +254,11 @@ "point"); } else { O << IndentStr << "if (ArgFlags.isSExt())\n" - << IndentStr << IndentStr << "LocInfo = CCValAssign::SExtUpper;\n" + << IndentStr << " LocInfo = CCValAssign::SExtUpper;\n" << IndentStr << "else if (ArgFlags.isZExt())\n" - << IndentStr << IndentStr << "LocInfo = CCValAssign::ZExtUpper;\n" + << IndentStr << " LocInfo = CCValAssign::ZExtUpper;\n" << IndentStr << "else\n" - << IndentStr << IndentStr << "LocInfo = CCValAssign::AExtUpper;\n"; + << IndentStr << " LocInfo = CCValAssign::AExtUpper;\n"; } } else if (Action->isSubClassOf("CCBitConvertToType")) { Record *DestTy = Action->getValueAsDef("DestTy"); @@ -282,7 +282,7 @@ O << IndentStr << "if (" << Action->getValueAsString("FuncName") << "(ValNo, ValVT, " << "LocVT, LocInfo, ArgFlags, State))\n"; - O << IndentStr << IndentStr << "return false;\n"; + O << IndentStr << " return false;\n"; } else { errs() << *Action; PrintFatalError(Action->getLoc(), "Unknown CCAction!"); diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp --- a/llvm/utils/TableGen/CodeEmitterGen.cpp +++ b/llvm/utils/TableGen/CodeEmitterGen.cpp @@ -483,7 +483,7 @@ << " Inst = Inst.zext(" << BitWidth << ");\n" << " if (Scratch.getBitWidth() != " << BitWidth << ")\n" << " Scratch = Scratch.zext(" << BitWidth << ");\n" - << " LoadIntFromMemory(Inst, (uint8_t*)&InstBits[opcode * " << NumWords + << " LoadIntFromMemory(Inst, (uint8_t *)&InstBits[opcode * " << NumWords << "], " << NumBytes << ");\n" << " APInt &Value = Inst;\n" << " APInt &op = Scratch;\n" @@ -643,9 +643,9 @@ << " report_fatal_error(Msg.str());\n" << " }\n" << "#else\n" - << "// Silence unused variable warning on targets that don't use MCII for " + << " // Silence unused variable warning on targets that don't use MCII for " "other purposes (e.g. BPF).\n" - << "(void)MCII;\n" + << " (void)MCII;\n" << "#endif // NDEBUG\n"; o << "}\n"; o << "#endif\n"; diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp --- a/llvm/utils/TableGen/CodeGenMapTable.cpp +++ b/llvm/utils/TableGen/CodeGenMapTable.cpp @@ -422,7 +422,7 @@ OS << " unsigned start = 0;\n"; OS << " unsigned end = " << TableSize << ";\n"; OS << " while (start < end) {\n"; - OS << " mid = start + (end - start)/2;\n"; + OS << " mid = start + (end - start) / 2;\n"; OS << " if (Opcode == " << InstrMapDesc.getName() << "Table[mid][0]) {\n"; OS << " break;\n"; OS << " }\n"; diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp --- a/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -2011,7 +2011,7 @@ if (RCRegUnits.empty()) continue; - LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units: \n"; + LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n"; for (auto U : RCRegUnits) printRegUnitName(U); dbgs() << "\n UnitSetIDs:"); diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -250,7 +250,7 @@ BeginEmitFunction(OS, "StringRef", "getPatternForIndex(unsigned Index)", true/*AddOverride*/); OS << "{\n"; - OS << "static const char * PATTERN_MATCH_TABLE[] = {\n"; + OS << "static const char *PATTERN_MATCH_TABLE[] = {\n"; for (const auto &It : VecPatterns) { OS << "\"" << It.first << "\",\n"; @@ -264,7 +264,7 @@ BeginEmitFunction(OS, "StringRef", "getIncludePathForIndex(unsigned Index)", true/*AddOverride*/); OS << "{\n"; - OS << "static const char * INCLUDE_PATH_TABLE[] = {\n"; + OS << "static const char *INCLUDE_PATH_TABLE[] = {\n"; for (const auto &It : VecIncludeStrings) { OS << "\"" << It << "\",\n"; @@ -844,7 +844,7 @@ TreePredicateFn PredFn = Preds[i]; assert(!PredFn.isAlwaysTrue() && "No code in this predicate"); - OS << " case " << i << ": { \n"; + OS << " case " << i << ": {\n"; for (auto *SimilarPred : NodePredicatesByCodeToRun[PredFn.getCodeToRunOnSDNode()]) OS << " // " << TreePredicateFn(SimilarPred).getFnName() <<'\n'; @@ -887,7 +887,7 @@ BeginEmitFunction(OS, "bool", "CheckComplexPattern(SDNode *Root, SDNode *Parent,\n" " SDValue N, unsigned PatternNo,\n" - " SmallVectorImpl> &Result)", + " SmallVectorImpl> &Result)", true/*AddOverride*/); OS << "{\n"; OS << " unsigned NextRes = Result.size();\n"; diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp --- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp @@ -744,7 +744,7 @@ } } - errs() << "unhandled leaf node: \n"; + errs() << "unhandled leaf node:\n"; N->dump(); } diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp --- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp +++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp @@ -263,7 +263,7 @@ OS << " " << ProcModelStartIdx[Model] << ", // " << Model->ModelName << "\n"; } - OS << ScheduleClasses.size() << "\n};\n\n"; + OS << " " << ScheduleClasses.size() << "\n};\n\n"; // The type of a state in the nondeterministic automaton we're defining. using NfaStateTy = uint64_t; diff --git a/llvm/utils/TableGen/ExegesisEmitter.cpp b/llvm/utils/TableGen/ExegesisEmitter.cpp --- a/llvm/utils/TableGen/ExegesisEmitter.cpp +++ b/llvm/utils/TableGen/ExegesisEmitter.cpp @@ -144,7 +144,7 @@ void ExegesisEmitter::emitPfmCounters(raw_ostream &OS) const { // Emit the counter name table. - OS << "\nstatic const char* " << Target << "PfmCounterNames[] = {\n"; + OS << "\nstatic const char *" << Target << "PfmCounterNames[] = {\n"; for (const auto &NameAndIndex : PfmCounterNameTable) OS << " \"" << NameAndIndex.first << "\", // " << NameAndIndex.second << "\n"; diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp --- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -941,7 +941,7 @@ // The predicate function is just a big switch statement based on the // input predicate index. OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, " - << "const FeatureBitset& Bits) {\n"; + << "const FeatureBitset &Bits) {\n"; Indentation += 2; if (!Predicates.empty()) { OS.indent(Indentation) << "switch (Idx) {\n"; @@ -965,7 +965,7 @@ unsigned Indentation) const { // The decoder function is just a big switch statement based on the // input decoder index. - OS.indent(Indentation) << "template\n"; + OS.indent(Indentation) << "template \n"; OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S," << " unsigned Idx, InsnType insn, MCInst &MI,\n"; OS.indent(Indentation) << " uint64_t " @@ -2162,7 +2162,7 @@ << "// * Support shift (<<, >>) with signed and unsigned integers on the " "RHS\n" << "// * Support put (<<) to raw_ostream&\n" - << "template\n" + << "template \n" << "#if defined(_MSC_VER) && !defined(__clang__)\n" << "__declspec(noinline)\n" << "#endif\n" @@ -2182,7 +2182,7 @@ << " return (insn & fieldMask) >> startBit;\n" << "}\n" << "\n" - << "template\n" + << "template \n" << "static InsnType fieldFromInstruction(InsnType insn, unsigned " "startBit,\n" << " unsigned numBits, " @@ -2193,7 +2193,7 @@ << " return (insn >> startBit) & fieldMask;\n" << "}\n" << "\n" - << "template\n" + << "template \n" << "static InsnType fieldFromInstruction(InsnType insn, unsigned " "startBit,\n" << " unsigned numBits) {\n" @@ -2205,14 +2205,14 @@ // emitDecodeInstruction - Emit the templated helper function // decodeInstruction(). static void emitDecodeInstruction(formatted_raw_ostream &OS) { - OS << "template\n" + OS << "template \n" << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], " "MCInst &MI,\n" << " InsnType insn, uint64_t " "Address,\n" << " const void *DisAsm,\n" << " const MCSubtargetInfo &STI) {\n" - << " const FeatureBitset& Bits = STI.getFeatureBits();\n" + << " const FeatureBitset &Bits = STI.getFeatureBits();\n" << "\n" << " const uint8_t *Ptr = DecodeTable;\n" << " InsnType CurFieldValue = 0;\n" @@ -2374,7 +2374,7 @@ << " if (Fail)\n" << " S = MCDisassembler::SoftFail;\n" << " LLVM_DEBUG(dbgs() << Loc << \": OPC_SoftFail: \" << (Fail ? " - "\"FAIL\\n\":\"PASS\\n\"));\n" + "\"FAIL\\n\" : \"PASS\\n\"));\n" << " break;\n" << " }\n" << " case MCD::OPC_Fail: {\n" @@ -2392,8 +2392,8 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { formatted_raw_ostream OS(o); OS << "#include \"llvm/MC/MCInst.h\"\n"; - OS << "#include \"llvm/Support/Debug.h\"\n"; OS << "#include \"llvm/Support/DataTypes.h\"\n"; + OS << "#include \"llvm/Support/Debug.h\"\n"; OS << "#include \"llvm/Support/LEB128.h\"\n"; OS << "#include \"llvm/Support/raw_ostream.h\"\n"; OS << "#include \n"; diff --git a/llvm/utils/TableGen/GICombinerEmitter.cpp b/llvm/utils/TableGen/GICombinerEmitter.cpp --- a/llvm/utils/TableGen/GICombinerEmitter.cpp +++ b/llvm/utils/TableGen/GICombinerEmitter.cpp @@ -906,7 +906,6 @@ << " bool isRuleDisabled(unsigned ID) const;\n" << " bool setRuleEnabled(StringRef RuleIdentifier);\n" << " bool setRuleDisabled(StringRef RuleIdentifier);\n" - << "\n" << "};\n" << "\n" << "class " << getClassName(); @@ -914,10 +913,10 @@ if (!StateClass.empty()) OS << " : public " << StateClass; OS << " {\n" - << " const " << getClassName() << "RuleConfig *RuleConfig;\n" + << " const " << getClassName() << "RuleConfig *RuleConfig;\n" << "\n" << "public:\n" - << " template" << getClassName() << "(const " + << " template " << getClassName() << "(const " << getClassName() << "RuleConfig &RuleConfig, Args &&... args) : "; if (!StateClass.empty()) OS << StateClass << "(std::forward(args)...), "; @@ -947,9 +946,9 @@ << " if (First >= Last)\n" << " report_fatal_error(\"Beginning of range should be before " "end of range\");\n" - << " return {{ *First, *Last + 1 }};\n" + << " return {{*First, *Last + 1}};\n" << " } else if (RangePair.first == \"*\") {\n" - << " return {{ 0, " << Rules.size() << " }};\n" + << " return {{0, " << Rules.size() << "}};\n" << " } else {\n" << " const auto I = getRuleIdxForIdentifier(RangePair.first);\n" << " if (!I.hasValue())\n" @@ -963,7 +962,7 @@ OS << "bool " << getClassName() << "RuleConfig::setRule" << (Enabled ? "Enabled" : "Disabled") << "(StringRef RuleIdentifier) {\n" << " auto MaybeRange = getRuleRangeForIdentifier(RuleIdentifier);\n" - << " if(!MaybeRange.hasValue())\n" + << " if (!MaybeRange.hasValue())\n" << " return false;\n" << " for (auto I = MaybeRange->first; I < MaybeRange->second; ++I)\n" << " DisabledRules." << (Enabled ? "reset" : "set") << "(I);\n" @@ -1026,7 +1025,7 @@ << " MachineBasicBlock *MBB = MI.getParent();\n" << " MachineFunction *MF = MBB->getParent();\n" << " MachineRegisterInfo &MRI = MF->getRegInfo();\n" - << " SmallVector MIs = { &MI };\n\n" + << " SmallVector MIs = {&MI};\n\n" << " (void)MBB; (void)MF; (void)MRI; (void)RuleConfig;\n\n"; OS << " // Match data\n"; diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -5619,7 +5619,7 @@ << " typedef void(" << Target.getName() << "InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const " - "MachineInstr&, int) " + "MachineInstr &, int) " "const;\n" << " const ISelInfoTy " @@ -5672,7 +5672,7 @@ OS << "void " << Target.getName() << "InstructionSelector" "::setupGeneratedPerFunctionState(MachineFunction &MF) {\n" " AvailableFunctionFeatures = computeAvailableFunctionFeatures(" - "(const " << Target.getName() << "Subtarget*)&MF.getSubtarget(), &MF);\n" + "(const " << Target.getName() << "Subtarget *)&MF.getSubtarget(), &MF);\n" "}\n"; if (Target.getName() == "X86" || Target.getName() == "AArch64") { @@ -5793,7 +5793,7 @@ << "enum {\n" << " GICR_Invalid,\n"; for (const auto &Record : CustomRendererFns) - OS << " GICR_" << Record->getValueAsString("RendererFn") << ", \n"; + OS << " GICR_" << Record->getValueAsString("RendererFn") << ",\n"; OS << "};\n"; OS << Target.getName() << "InstructionSelector::CustomRendererFn\n" diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -280,7 +280,7 @@ for (const auto &Op : Operands) OS << " " << Op.first << " = " << Op.second << ",\n"; - OS << "OPERAND_LAST"; + OS << " OPERAND_LAST"; OS << "\n};\n"; OS << "} // end namespace OpName\n"; OS << "} // end namespace " << Namespace << "\n"; @@ -316,7 +316,7 @@ OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n"; } - OS << " default: return -1;\n"; + OS << " default: return -1;\n"; OS << " }\n"; } else { // There are no operands, so no need to emit anything diff --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp --- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp +++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp @@ -226,15 +226,15 @@ if (!Expansions.empty()) { o << " switch (MI->getOpcode()) {\n" - << " default: return false;\n"; + << " default: return false;\n"; for (auto &Expansion : Expansions) { CodeGenInstruction &Source = Expansion.Source; CodeGenInstruction &Dest = Expansion.Dest; - o << " case " << Source.Namespace << "::" + o << " case " << Source.Namespace << "::" << Source.TheDef->getName() << ": {\n" - << " MCInst TmpInst;\n" - << " MCOperand MCOp;\n" - << " TmpInst.setOpcode(" << Dest.Namespace << "::" + << " MCInst TmpInst;\n" + << " MCOperand MCOp;\n" + << " TmpInst.setOpcode(" << Dest.Namespace << "::" << Dest.TheDef->getName() << ");\n"; // Copy the operands from the source instruction. @@ -243,23 +243,23 @@ // expansion DAG. unsigned MIOpNo = 0; for (const auto &DestOperand : Dest.Operands) { - o << " // Operand: " << DestOperand.Name << "\n"; + o << " // Operand: " << DestOperand.Name << "\n"; for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) { switch (Expansion.OperandMap[MIOpNo + i].Kind) { case OpData::Operand: - o << " lowerOperand(MI->getOperand(" + o << " lowerOperand(MI->getOperand(" << Source.Operands[Expansion.OperandMap[MIOpNo].Data .Operand].MIOperandNo + i << "), MCOp);\n" - << " TmpInst.addOperand(MCOp);\n"; + << " TmpInst.addOperand(MCOp);\n"; break; case OpData::Imm: - o << " TmpInst.addOperand(MCOperand::createImm(" + o << " TmpInst.addOperand(MCOperand::createImm(" << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; break; case OpData::Reg: { Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; - o << " TmpInst.addOperand(MCOperand::createReg("; + o << " TmpInst.addOperand(MCOperand::createReg("; // "zero_reg" is special. if (Reg->getName() == "zero_reg") o << "0"; @@ -275,15 +275,15 @@ } if (Dest.Operands.isVariadic) { MIOpNo = Source.Operands.size() + 1; - o << " // variable_ops\n"; - o << " for (unsigned i = " << MIOpNo + o << " // variable_ops\n"; + o << " for (unsigned i = " << MIOpNo << ", e = MI->getNumOperands(); i != e; ++i)\n" - << " if (lowerOperand(MI->getOperand(i), MCOp))\n" - << " TmpInst.addOperand(MCOp);\n"; + << " if (lowerOperand(MI->getOperand(i), MCOp))\n" + << " TmpInst.addOperand(MCOp);\n"; } - o << " EmitToStreamer(OutStreamer, TmpInst);\n" - << " break;\n" - << " }\n"; + o << " EmitToStreamer(OutStreamer, TmpInst);\n" + << " break;\n" + << " }\n"; } o << " }\n return true;"; } else diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp --- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp +++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp @@ -37,11 +37,11 @@ // compressing/uncompressing MCInst instructions, plus // some helper functions: // -// bool compressInst(MCInst& OutInst, const MCInst &MI, +// bool compressInst(MCInst &OutInst, const MCInst &MI, // const MCSubtargetInfo &STI, // MCContext &Context); // -// bool uncompressInst(MCInst& OutInst, const MCInst &MI, +// bool uncompressInst(MCInst &OutInst, const MCInst &MI, // const MCRegisterInfo &MRI, // const MCSubtargetInfo &STI); // @@ -610,17 +610,17 @@ << "#undef GEN_CHECK_COMPRESS_INSTR\n\n"; if (EType == EmitterType::Compress) { - FuncH << "static bool compressInst(MCInst& OutInst,\n"; + FuncH << "static bool compressInst(MCInst &OutInst,\n"; FuncH.indent(25) << "const MCInst &MI,\n"; FuncH.indent(25) << "const MCSubtargetInfo &STI,\n"; FuncH.indent(25) << "MCContext &Context) {\n"; } else if (EType == EmitterType::Uncompress){ - FuncH << "static bool uncompressInst(MCInst& OutInst,\n"; + FuncH << "static bool uncompressInst(MCInst &OutInst,\n"; FuncH.indent(27) << "const MCInst &MI,\n"; FuncH.indent(27) << "const MCRegisterInfo &MRI,\n"; FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n"; } else if (EType == EmitterType::CheckCompress) { - FuncH << "static bool isCompressibleInst(const MachineInstr& MI,\n"; + FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n"; FuncH.indent(27) << "const RISCVSubtarget *Subtarget,\n"; FuncH.indent(27) << "const MCRegisterInfo &MRI,\n"; FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n"; @@ -781,7 +781,7 @@ unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates, DestOperand.Rec, StringRef("ImmediateCode")); CondStream.indent(6) << "MI.getOperand(" + std::to_string(OpIdx) + - ").isImm() && \n"; + ").isImm() &&\n"; CondStream.indent(6) << Namespace + "ValidateMachineOperand(" + "MI.getOperand(" + std::to_string(OpIdx) + "), Subtarget, " + std::to_string(Entry) + @@ -858,7 +858,7 @@ << "ValidateMachineOperand(const MachineOperand &MO,\n" << " const RISCVSubtarget *Subtarget,\n" << " unsigned PredicateIndex) {\n" - << " int64_t Imm = MO.getImm(); \n" + << " int64_t Imm = MO.getImm();\n" << " switch (PredicateIndex) {\n" << " default:\n" << " llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n" diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp --- a/llvm/utils/TableGen/RegisterBankEmitter.cpp +++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp @@ -133,7 +133,7 @@ << "namespace " << TargetName << " {\n" << "enum : unsigned {\n"; - OS << "InvalidRegBankID = ~0u,\n"; + OS << " InvalidRegBankID = ~0u,\n"; unsigned ID = 0; for (const auto &Bank : Banks) OS << " " << Bank.getEnumeratorName() << " = " << ID++ << ",\n"; diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -127,7 +127,7 @@ OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; assert(Registers.size() == Registers.back().EnumValue && "Register enum value mismatch!"); - OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; + OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; OS << "};\n"; if (!Namespace.empty()) OS << "} // end namespace " << Namespace << "\n"; @@ -146,7 +146,7 @@ for (const auto &RC : RegisterClasses) OS << " " << RC.getName() << "RegClassID" << " = " << RC.EnumValue << ",\n"; - OS << "\n };\n"; + OS << "\n};\n"; if (!Namespace.empty()) OS << "} // end namespace " << Namespace << "\n\n"; } @@ -323,7 +323,7 @@ OS << "/// Get the dimensions of register pressure impacted by this " << "register class.\n" << "/// Returns a -1 terminated array of pressure set IDs\n" - << "const int* " << ClassName << "::\n" + << "const int *" << ClassName << "::\n" << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) << " RCSetStartTable[] = {\n "; @@ -337,7 +337,7 @@ OS << "/// Get the dimensions of register pressure impacted by this " << "register unit.\n" << "/// Returns a -1 terminated array of pressure set IDs\n" - << "const int* " << ClassName << "::\n" + << "const int *" << ClassName << "::\n" << "getRegUnitPressureSets(unsigned RegUnit) const {\n" << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n"; @@ -1167,7 +1167,7 @@ << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" << "(unsigned, LaneBitmask) const override;\n" << " const TargetRegisterClass *getSubClassWithSubReg" - << "(const TargetRegisterClass*, unsigned) const override;\n"; + << "(const TargetRegisterClass *, unsigned) const override;\n"; } OS << " const RegClassWeight &getRegClassWeight(" << "const TargetRegisterClass *RC) const override;\n" @@ -1436,7 +1436,7 @@ } OS << "\nnamespace {\n"; - OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; + OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; for (const auto &RC : RegisterClasses) OS << " &" << RC.getQualifiedName() << "RegClass,\n"; OS << " };\n"; diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp --- a/llvm/utils/TableGen/SearchableTableEmitter.cpp +++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp @@ -416,7 +416,7 @@ << " " << Field.Name << ";\n"; } OS << " };\n"; - OS << " KeyType Key = { "; + OS << " KeyType Key = {"; bool NeedComma = false; for (const auto &Field : Index.Fields) { if (NeedComma) @@ -434,7 +434,7 @@ Field.Name + "'"); } } - OS << " };\n"; + OS << "};\n"; OS << " auto Table = makeArrayRef(" << IndexName << ");\n"; OS << " auto Idx = std::lower_bound(Table.begin(), Table.end(), Key,\n"; diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -1709,7 +1709,7 @@ } OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n" - << " const FeatureBitset& Bits = getFeatureBits();\n"; + << " const FeatureBitset &Bits = getFeatureBits();\n"; for (Record *R : Features) { // Next record @@ -1755,7 +1755,7 @@ << " const MCInst *MI, const MCInstrInfo *MCII,\n" << " unsigned CPUID) const override {\n" << " return " << Target << "_MC" - << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID); \n"; + << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"; OS << " }\n"; if (TGT.getHwModes().getNumModeIds() > 1) OS << " unsigned getHwMode() const override;\n"; diff --git a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp b/llvm/utils/TableGen/SubtargetFeatureInfo.cpp --- a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp +++ b/llvm/utils/TableGen/SubtargetFeatureInfo.cpp @@ -112,7 +112,7 @@ StringRef TargetName, StringRef ClassName, StringRef FuncName, SubtargetFeatureInfoMap &SubtargetFeatures, raw_ostream &OS) { OS << "FeatureBitset " << TargetName << ClassName << "::\n" - << FuncName << "(const FeatureBitset& FB) const {\n"; + << FuncName << "(const FeatureBitset &FB) const {\n"; OS << " FeatureBitset Features;\n"; for (const auto &SF : SubtargetFeatures) { const SubtargetFeatureInfo &SFI = SF.second;