diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -938,10 +938,11 @@
 }
 
 // Section 8.2.1 - LEA
-let cx = 0, DecoderMethod = "DecodeLoadI64" in
-defm LEA : RMm<"lea", 0x06, I64>;
-let cx = 1, DecoderMethod = "DecodeLoadI64" in
-defm LEASL : RMm<"lea.sl", 0x06, I64>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1,
+    DecoderMethod = "DecodeLoadI64" in {
+  let cx = 0 in defm LEA : RMm<"lea", 0x06, I64>;
+  let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64>;
+}
 
 def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
 def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
@@ -1140,6 +1141,8 @@
 // Section 8.4 - Fixed-point Operation Instructions
 //-----------------------------------------------------------------------------
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.4.1 - ADD (Add)
 defm ADDUL : RRm<"addu.l", 0x48, I64, i64>;
 let cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>;
@@ -1162,6 +1165,8 @@
 // Section 8.4.6 - SBX (Subtract)
 defm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 // Section 8.4.7 - MPY (Multiply)
 defm MULUL : RRm<"mulu.l", 0x49, I64, i64>;
 let cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>;
@@ -1187,6 +1192,8 @@
 // Section 8.4.13 - DVX (Divide)
 defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.4.14 - CMP (Compare)
 defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>;
 let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>;
@@ -1209,10 +1216,14 @@
 defm MAXSL : RRm<"maxs.l", 0x68, I64, i64>;
 let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 //-----------------------------------------------------------------------------
 // Section 8.5 - Logical Operation Instructions
 //-----------------------------------------------------------------------------
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.5.1 - AND (AND)
 defm AND : RRm<"and", 0x44, I64, i64, and>;
 
@@ -1225,9 +1236,12 @@
 // Section 8.5.4 - EQV (Equivalence)
 defm EQV : RRm<"eqv", 0x47, I64, i64>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 // Section 8.5.5 - NND (Negate AND)
 def and_not : PatFrags<(ops node:$x, node:$y),
                        [(and (not node:$x), node:$y)]>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>;
 
 // Section 8.5.6 - MRG (Merge)
@@ -1237,16 +1251,20 @@
 def ctlz_pat : PatFrags<(ops node:$src),
                         [(ctlz node:$src),
                          (ctlz_zero_undef node:$src)]>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>;
 
 // Section 8.5.8 - PCNT (Population Count)
 defm PCNT : RRI1m<"pcnt", 0x38, I64, i64, ctpop>;
 
 // Section 8.5.9 - BRV (Bit Reverse)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm BRV : RRI1m<"brv", 0x39, I64, i64, bitreverse>;
 
 // Section 8.5.10 - BSWP (Byte Swap)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm BSWP : RRSWPm<"bswp", 0x2B, I64, i64>;
+
 def : Pat<(i64 (bswap i64:$src)),
           (BSWPri $src, 0)>;
 def : Pat<(i64 (bswap (i64 mimm:$src))),
@@ -1273,17 +1291,21 @@
 //-----------------------------------------------------------------------------
 
 // Section 8.6.1 - SLL (Shift Left Logical)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
 
 // Section 8.6.2 - SLD (Shift Left Double)
 defm SLD : RRILDm<"sld", 0x64, I64, i64>;
 
 // Section 8.6.3 - SRL (Shift Right Logical)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
 
 // Section 8.6.4 - SRD (Shift Right Double)
 defm SRD : RRIRDm<"srd", 0x74, I64, i64>;
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.6.5 - SLA (Shift Left Arithmetic)
 defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
 let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
@@ -1298,6 +1320,8 @@
 // Section 8.6.8 - SRAX (Shift Right Arithmetic)
 defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),
           (EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
             $src, sub_i32), !add(32, 64)), imm:$val), sub_i32)>;
diff --git a/llvm/test/CodeGen/VE/Scalar/br_cc.ll b/llvm/test/CodeGen/VE/Scalar/br_cc.ll
--- a/llvm/test/CodeGen/VE/Scalar/br_cc.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_cc.ll
@@ -523,7 +523,7 @@
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s3, 0, %s2
+; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, 63, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
@@ -553,7 +553,7 @@
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s3, 0, %s2
+; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, 63, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
@@ -856,15 +856,15 @@
 ; CHECK-LABEL: br_cc_imm_i128:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, -1, (0)1
-; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s2, 0, %s3
-; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s1
+; CHECK-NEXT:    or %s2, 0, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, -64, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
-; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s2, %s3, %s1
-; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
@@ -887,15 +887,15 @@
 ; CHECK-LABEL: br_cc_imm_u128:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, -1, (0)1
-; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s2, 0, %s3
-; CHECK-NEXT:    cmov.l.ne %s2, (63)0, %s1
+; CHECK-NEXT:    or %s2, 0, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, -64, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
-; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s2, %s3, %s1
-; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
diff --git a/llvm/test/CodeGen/VE/Scalar/call.ll b/llvm/test/CodeGen/VE/Scalar/call.ll
--- a/llvm/test/CodeGen/VE/Scalar/call.ll
+++ b/llvm/test/CodeGen/VE/Scalar/call.ll
@@ -50,9 +50,10 @@
 ; CHECK-NEXT:    or %s0, -1, (0)1
 ; CHECK-NEXT:    st %s0, 248(, %s11)
 ; CHECK-NEXT:    lea %s34, 65535
-; CHECK-NEXT:    lea %s1, stack_callee_int_szext@lo
-; CHECK-NEXT:    and %s1, %s1, (32)0
-; CHECK-NEXT:    lea.sl %s12, stack_callee_int_szext@hi(, %s1)
+; CHECK-NEXT:    lea %s0, stack_callee_int_szext@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, stack_callee_int_szext@hi(, %s0)
+; CHECK-NEXT:    or %s0, -1, (0)1
 ; CHECK-NEXT:    lea %s1, 255
 ; CHECK-NEXT:    or %s2, 3, (0)1
 ; CHECK-NEXT:    or %s3, 4, (0)1
@@ -73,6 +74,9 @@
 ; CHECK-NEXT:    lea.sl %s0, 1092616192
 ; CHECK-NEXT:    st %s0, 248(, %s11)
 ; CHECK-NEXT:    lea.sl %s34, 1091567616
+; CHECK-NEXT:    lea %s0, stack_callee_float@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, stack_callee_float@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, 1065353216
 ; CHECK-NEXT:    lea.sl %s1, 1073741824
 ; CHECK-NEXT:    lea.sl %s2, 1077936128
@@ -81,9 +85,6 @@
 ; CHECK-NEXT:    lea.sl %s5, 1086324736
 ; CHECK-NEXT:    lea.sl %s6, 1088421888
 ; CHECK-NEXT:    lea.sl %s7, 1090519040
-; CHECK-NEXT:    lea %s35, stack_callee_float@lo
-; CHECK-NEXT:    and %s35, %s35, (32)0
-; CHECK-NEXT:    lea.sl %s12, stack_callee_float@hi(, %s35)
 ; CHECK-NEXT:    st %s34, 240(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -111,4 +112,3 @@
   %r = tail call float @stack_callee_float(float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0)
   ret float %r
 }
-
diff --git a/llvm/test/CodeGen/VE/Scalar/ctlz.ll b/llvm/test/CodeGen/VE/Scalar/ctlz.ll
--- a/llvm/test/CodeGen/VE/Scalar/ctlz.ll
+++ b/llvm/test/CodeGen/VE/Scalar/ctlz.ll
@@ -10,12 +10,12 @@
 ; CHECK-LABEL: func128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s1, %s2
+; CHECK-NEXT:    cmps.l %s2, %s1, %s2
 ; CHECK-NEXT:    ldz %s1, %s1
 ; CHECK-NEXT:    ldz %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
-; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s3
-; CHECK-NEXT:    or %s1, 0, %s2
+; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s2
+; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
   ret i128 %r
@@ -180,12 +180,12 @@
 ; CHECK-LABEL: func128x:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s1, %s2
+; CHECK-NEXT:    cmps.l %s2, %s1, %s2
 ; CHECK-NEXT:    ldz %s1, %s1
 ; CHECK-NEXT:    ldz %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
-; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s3
-; CHECK-NEXT:    or %s1, 0, %s2
+; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s2
+; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
   ret i128 %r
diff --git a/llvm/test/CodeGen/VE/Scalar/cttz.ll b/llvm/test/CodeGen/VE/Scalar/cttz.ll
--- a/llvm/test/CodeGen/VE/Scalar/cttz.ll
+++ b/llvm/test/CodeGen/VE/Scalar/cttz.ll
@@ -10,16 +10,16 @@
 ; CHECK-LABEL: func128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s0, %s2
-; CHECK-NEXT:    lea %s4, -1(, %s0)
-; CHECK-NEXT:    nnd %s0, %s0, %s4
-; CHECK-NEXT:    pcnt %s4, %s0
+; CHECK-NEXT:    cmps.l %s2, %s0, %s2
+; CHECK-NEXT:    lea %s3, -1(, %s0)
+; CHECK-NEXT:    nnd %s0, %s0, %s3
+; CHECK-NEXT:    pcnt %s3, %s0
 ; CHECK-NEXT:    lea %s0, -1(, %s1)
 ; CHECK-NEXT:    nnd %s0, %s1, %s0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
-; CHECK-NEXT:    cmov.l.ne %s0, %s4, %s3
-; CHECK-NEXT:    or %s1, 0, %s2
+; CHECK-NEXT:    cmov.l.ne %s0, %s3, %s2
+; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
   ret i128 %r
diff --git a/llvm/test/CodeGen/VE/Scalar/fp_frem.ll b/llvm/test/CodeGen/VE/Scalar/fp_frem.ll
--- a/llvm/test/CodeGen/VE/Scalar/fp_frem.ll
+++ b/llvm/test/CodeGen/VE/Scalar/fp_frem.ll
@@ -75,10 +75,10 @@
 ; CHECK-LABEL: frem_float_zero:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea %s0, fmodf@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, 0
-; CHECK-NEXT:    lea %s2, fmodf@lo
-; CHECK-NEXT:    and %s2, %s2, (32)0
-; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = frem float 0.000000e+00, %0
@@ -125,10 +125,10 @@
 ; CHECK-LABEL: frem_float_cont:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea %s0, fmodf@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, -1073741824
-; CHECK-NEXT:    lea %s2, fmodf@lo
-; CHECK-NEXT:    and %s2, %s2, (32)0
-; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = frem float -2.000000e+00, %0
diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll b/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll
--- a/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll
+++ b/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll
@@ -59,15 +59,15 @@
 define float @selectccsgti128(i128, i128, float, float) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -99,4 +99,3 @@
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }
-
diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll b/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll
--- a/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll
+++ b/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll
@@ -59,15 +59,15 @@
 define double @selectccsgti128(i128, i128, double, double) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -99,4 +99,3 @@
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }
-
diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll
--- a/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll
+++ b/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll
@@ -59,15 +59,15 @@
 define i32 @selectccsgti128(i128, i128, i32, i32) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -99,4 +99,3 @@
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
-
diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll
--- a/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll
+++ b/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll
@@ -59,15 +59,15 @@
 define i64 @selectccsgti128(i128, i128, i64, i64) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -99,4 +99,3 @@
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
-
diff --git a/llvm/test/CodeGen/VE/Scalar/va_caller.ll b/llvm/test/CodeGen/VE/Scalar/va_caller.ll
--- a/llvm/test/CodeGen/VE/Scalar/va_caller.ll
+++ b/llvm/test/CodeGen/VE/Scalar/va_caller.ll
@@ -5,44 +5,48 @@
 define i32 @caller() {
 ; CHECK-LABEL: caller:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s18, 48(, %s9) # 8-byte Folded Spill
-; CHECK-NEXT:    or %s18, 0, (0)1
-; CHECK-NEXT:    st %s18, 264(, %s11)
-; CHECK-NEXT:    or %s0, 10, (0)1
-; CHECK-NEXT:    st %s0, 256(, %s11)
-; CHECK-NEXT:    lea.sl %s0, 1075970048
-; CHECK-NEXT:    st %s0, 248(, %s11)
-; CHECK-NEXT:    or %s0, 8, (0)1
-; CHECK-NEXT:    st %s0, 240(, %s11)
-; CHECK-NEXT:    st %s18, 232(, %s11)
-; CHECK-NEXT:    or %s5, 5, (0)1
-; CHECK-NEXT:    st %s5, 216(, %s11)
-; CHECK-NEXT:    or %s4, 4, (0)1
-; CHECK-NEXT:    st %s4, 208(, %s11)
-; CHECK-NEXT:    or %s3, 3, (0)1
-; CHECK-NEXT:    st %s3, 200(, %s11)
-; CHECK-NEXT:    or %s2, 2, (0)1
-; CHECK-NEXT:    st %s2, 192(, %s11)
+; CHECK-NEXT:    or %s0, 0, (0)1
+; CHECK-NEXT:    st %s0, 264(, %s11)
+; CHECK-NEXT:    or %s1, 10, (0)1
+; CHECK-NEXT:    st %s1, 256(, %s11)
+; CHECK-NEXT:    lea.sl %s1, 1075970048
+; CHECK-NEXT:    st %s1, 248(, %s11)
+; CHECK-NEXT:    or %s1, 8, (0)1
+; CHECK-NEXT:    st %s1, 240(, %s11)
+; CHECK-NEXT:    st %s0, 232(, %s11)
+; CHECK-NEXT:    or %s1, 5, (0)1
+; CHECK-NEXT:    st %s1, 216(, %s11)
+; CHECK-NEXT:    or %s1, 4, (0)1
+; CHECK-NEXT:    st %s1, 208(, %s11)
+; CHECK-NEXT:    or %s1, 3, (0)1
+; CHECK-NEXT:    st %s1, 200(, %s11)
+; CHECK-NEXT:    or %s1, 2, (0)1
+; CHECK-NEXT:    st %s1, 192(, %s11)
 ; CHECK-NEXT:    or %s1, 1, (0)1
 ; CHECK-NEXT:    st %s1, 184(, %s11)
-; CHECK-NEXT:    lea %s0, .LCPI{{[0-9]+}}_0@lo
-; CHECK-NEXT:    and %s0, %s0, (32)0
-; CHECK-NEXT:    lea.sl %s0, .LCPI{{[0-9]+}}_0@hi(, %s0)
-; CHECK-NEXT:    ld %s34, 8(, %s0)
-; CHECK-NEXT:    ld %s35, (, %s0)
-; CHECK-NEXT:    st %s18, 176(, %s11)
-; CHECK-NEXT:    lea.sl %s6, 1086324736
-; CHECK-NEXT:    st %s6, 224(, %s11)
+; CHECK-NEXT:    lea %s1, .LCPI{{[0-9]+}}_0@lo
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
+; CHECK-NEXT:    ld %s34, 8(, %s1)
+; CHECK-NEXT:    ld %s35, (, %s1)
+; CHECK-NEXT:    st %s0, 176(, %s11)
+; CHECK-NEXT:    lea.sl %s0, 1086324736
+; CHECK-NEXT:    st %s0, 224(, %s11)
 ; CHECK-NEXT:    st %s34, 280(, %s11)
 ; CHECK-NEXT:    lea %s0, func@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, func@hi(, %s0)
+; CHECK-NEXT:    or %s0, 0, (0)1
+; CHECK-NEXT:    or %s1, 1, (0)1
+; CHECK-NEXT:    or %s2, 2, (0)1
+; CHECK-NEXT:    or %s3, 3, (0)1
+; CHECK-NEXT:    or %s4, 4, (0)1
+; CHECK-NEXT:    or %s5, 5, (0)1
+; CHECK-NEXT:    lea.sl %s6, 1086324736
+; CHECK-NEXT:    or %s7, 0, (0)1
 ; CHECK-NEXT:    st %s35, 272(, %s11)
-; CHECK-NEXT:    or %s0, 0, %s18
-; CHECK-NEXT:    or %s7, 0, %s18
 ; CHECK-NEXT:    bsic %s10, (, %s12)
-; CHECK-NEXT:    or %s0, 0, %s18
-; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
+; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   call i32 (i32, ...) @func(i32 0, i16 1, i8 2, i32 3, i16 4, i8 5, float 6.0, i8* null, i64 8, double 9.0, i128 10, fp128 0xLA000000000000000)
   ret i32 0