Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -212,8 +212,7 @@ setTruncStoreAction(MVT::f64, MVT::f16, Expand); } - if (Subtarget.is64Bit() && - !(Subtarget.hasStdExtD() || Subtarget.hasStdExtF())) { + if (Subtarget.is64Bit()) { setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); @@ -941,6 +940,9 @@ assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0); + if (getTypeAction(*DAG.getContext(), Op0.getValueType()) != + TargetLowering::TypeSoftenFloat) + return; RTLIB::Libcall LC; if (N->getOpcode() == ISD::FP_TO_SINT || N->getOpcode() == ISD::STRICT_FP_TO_SINT) Index: llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll +++ llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll @@ -21,7 +21,7 @@ ; RV64IF: # %bb.0: # %entry ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) -; RV64IF-NEXT: call __fixunsdfdi +; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -44,7 +44,7 @@ ; RV64IF: # %bb.0: # %entry ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) -; RV64IF-NEXT: call __fixdfdi +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -72,7 +72,7 @@ ; RV64IF: # %bb.0: # %entry ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) -; RV64IF-NEXT: call __fixunsdfdi +; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -95,7 +95,7 @@ ; RV64IF: # %bb.0: # %entry ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) -; RV64IF-NEXT: call __fixdfdi +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret