diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5889,9 +5889,17 @@
         // Don't combine AND since emitComparison converts the AND to an ANDS
         // (a.k.a. TST) and the test in the test bit and branch instruction
         // becomes redundant.  This would also increase register pressure.
-        uint64_t Mask = LHS.getValueSizeInBits() - 1;
+        uint64_t SignBitPos = LHS.getValueSizeInBits() - 1;
+        // If LHS is a sext_inreg, we can check the sign bit of the
+        // original unextended data.
+        if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+          SignBitPos =
+              cast<VTSDNode>(LHS.getOperand(1))->getVT().getFixedSizeInBits() -
+              1;
+          LHS = LHS.getOperand(0);
+        }
         return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
-                           DAG.getConstant(Mask, dl, MVT::i64), Dest);
+                           DAG.getConstant(SignBitPos, dl, MVT::i64), Dest);
       }
     }
     if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
@@ -5899,9 +5907,16 @@
       // Don't combine AND since emitComparison converts the AND to an ANDS
       // (a.k.a. TST) and the test in the test bit and branch instruction
       // becomes redundant.  This would also increase register pressure.
-      uint64_t Mask = LHS.getValueSizeInBits() - 1;
+      uint64_t SignBitPos = LHS.getValueSizeInBits() - 1;
+      // If LHS is a sext_inreg, we can check the sign bit of the
+      // original unextended data.
+      if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+        SignBitPos =
+            cast<VTSDNode>(LHS.getOperand(1))->getVT().getFixedSizeInBits() - 1;
+        LHS = LHS.getOperand(0);
+      }
       return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
-                         DAG.getConstant(Mask, dl, MVT::i64), Dest);
+                         DAG.getConstant(SignBitPos, dl, MVT::i64), Dest);
     }
 
     SDValue CCVal;
diff --git a/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll b/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
@@ -0,0 +1,108 @@
+; RUN: llc -mtriple aarch64-gnu-linux -o -  -asm-verbose=0 %s | FileCheck %s
+
+; These tests make sure that the `cmp` instruction is rendered with an
+; instruction that checks the sign bit of the original unextended data
+; (%in) instead of the sign bit of the sign extended one that is
+; created by the type legalization process.
+
+; CHECK-LABEL: f_i8:
+; CHECK: tbnz w0, #7, .LBB
+define i32 @f_i8(i8 %in, i32 %a, i32 %b) nounwind {
+entry:
+  %cmp = icmp sgt i8 %in, -1
+  %ext = zext i8 %in to i32
+  br i1 %cmp, label %A, label %B
+
+A:
+  %retA = add i32 %ext, %a
+  ret i32 %retA
+
+B: 
+  %retB = add i32 %ext, %b
+  ret i32 %retB
+}
+
+; CHECK-LABEL: f_i16:
+; CHECK: tbnz w0, #15, .LBB
+define i32 @f_i16(i16 %in, i32 %a, i32 %b) nounwind {
+entry:
+  %cmp = icmp sgt i16 %in, -1
+  %ext = zext i16 %in to i32
+  br i1 %cmp, label %A, label %B
+
+A:
+  %retA = add i32 %ext, %a
+  ret i32 %retA
+
+B: 
+  %retB = add i32 %ext, %b
+  ret i32 %retB
+}
+
+; CHECK-LABEL: f_i32:
+; CHECK: tbnz w0, #31, .LBB
+define i64 @f_i32(i32 %in, i64 %a, i64 %b) nounwind {
+entry:
+  %cmp = icmp sgt i32 %in, -1
+  %ext = zext i32 %in to i64
+  br i1 %cmp, label %A, label %B
+
+A:
+  %retA = add i64 %ext, %a
+  ret i64 %retA
+
+B: 
+  %retB = add i64 %ext, %b
+  ret i64 %retB
+}
+
+; CHECK-LABEL: g_i8:
+; CHECK: tbnz w0, #7, .LBB
+define i32 @g_i8(i8 %in, i32 %a, i32 %b) nounwind {
+entry:
+  %cmp = icmp slt i8 %in, 0
+  %ext = zext i8 %in to i32
+  br i1 %cmp, label %A, label %B
+
+A:
+  %retA = add i32 %ext, %a
+  ret i32 %retA
+
+B:
+  %retB = add i32 %ext, %b
+  ret i32 %retB
+}
+
+; CHECK-LABEL: g_i16:
+; CHECK: tbnz w0, #15, .LBB
+define i32 @g_i16(i16 %in, i32 %a, i32 %b) nounwind {
+entry:
+  %cmp = icmp slt i16 %in, 0
+  %ext = zext i16 %in to i32
+  br i1 %cmp, label %A, label %B
+
+A:
+  %retA = add i32 %ext, %a
+  ret i32 %retA
+
+B:
+  %retB = add i32 %ext, %b
+  ret i32 %retB
+}
+
+; CHECK-LABEL: g_i32:
+; CHECK: tbnz w0, #31, .LBB
+define i64 @g_i32(i32 %in, i64 %a, i64 %b) nounwind {
+entry:
+  %cmp = icmp slt i32 %in, 0
+  %ext = zext i32 %in to i64
+  br i1 %cmp, label %A, label %B
+
+A:
+  %retA = add i64 %ext, %a
+  ret i64 %retA
+
+B:
+  %retB = add i64 %ext, %b
+  ret i64 %retB
+}