Index: llvm/lib/Target/AMDGPU/FLATInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -238,6 +238,10 @@
 class FlatScratchInst <string sv_op, string mode> {
   string SVOp = sv_op;
   string Mode = mode;
+  string Op = sv_op#!if(!eq(mode, "SS"), "_SADDR",
+                    !if(!eq(mode, "SV"), "",
+                        "_"#mode));
+  bit IsFlatScratch = 1;
 }
 
 class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -43,6 +43,69 @@
 class GCNSubtarget;
 class TargetRegisterClass;
 
+namespace AMDGPU {
+
+  LLVM_READONLY
+  int getVOPe64(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getVOPe32(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getSDWAOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getDPPOp32(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getBasicFromSDWAOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getCommuteRev(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getCommuteOrig(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getAddr64Inst(uint16_t Opcode);
+
+  /// Check if \p Opcode is an Addr64 opcode.
+  ///
+  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
+  LLVM_READONLY
+  int getIfAddr64Inst(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getMUBUFNoLdsInst(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getAtomicRetOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getAtomicNoRetOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getSOPKOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getGlobalSaddrOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getVCMPXNoSDstOp(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getFlatScratchInstSTfromSS(uint16_t Opcode);
+
+  LLVM_READONLY
+  int getFlatScratchInst(uint16_t Opcode);
+
+  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
+  const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
+  const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
+  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
+
+} // end namespace AMDGPU
+
 class SIInstrInfo final : public AMDGPUGenInstrInfo {
 private:
   const SIRegisterInfo RI;
@@ -512,13 +575,12 @@
     return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
   }
 
-  // FIXME: Make this more precise
   static bool isFLATScratch(const MachineInstr &MI) {
-    return isSegmentSpecificFLAT(MI);
+    return AMDGPU::getFlatScratchInst(MI.getOpcode()) >= 0;
   }
 
-  bool isFLATScratch(uint16_t Opcode) const {
-    return isSegmentSpecificFLAT(Opcode);
+  static bool isFLATScratch(uint16_t Opcode) {
+    return AMDGPU::getFlatScratchInst(Opcode) >= 0;
   }
 
   // Any FLAT encoded instruction, including global_* and scratch_*.
@@ -1106,66 +1168,6 @@
                                    Register VReg,
                                    const MachineInstr &DefMI);
 
-namespace AMDGPU {
-
-  LLVM_READONLY
-  int getVOPe64(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getVOPe32(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getSDWAOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getDPPOp32(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getBasicFromSDWAOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getCommuteRev(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getCommuteOrig(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getAddr64Inst(uint16_t Opcode);
-
-  /// Check if \p Opcode is an Addr64 opcode.
-  ///
-  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
-  LLVM_READONLY
-  int getIfAddr64Inst(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getMUBUFNoLdsInst(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getAtomicRetOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getAtomicNoRetOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getSOPKOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getGlobalSaddrOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getVCMPXNoSDstOp(uint16_t Opcode);
-
-  LLVM_READONLY
-  int getFlatScratchInstSTfromSS(uint16_t Opcode);
-
-  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
-  const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
-  const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
-  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
-
-} // end namespace AMDGPU
-
 namespace SI {
 namespace KernelInputOffsets {
 
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2573,6 +2573,15 @@
   let ValueCols = [["ST"]];
 }
 
+// Maps a flat scratch instruction to itself.
+// Used to check if an instruction is a flat scratch.
+def getFlatScratchInst : InstrMapping {
+  let FilterClass = "FlatScratchInst";
+  let RowFields = ["Op"];
+  let ColFields = ["IsFlatScratch"];
+  let KeyCol = ["1"];
+  let ValueCols = [["1"]];
+}
 
 include "SIInstructions.td"