diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -978,7 +978,8 @@
/// Compute known bits from a shift operator, including those with a
/// non-constant shift amount. Known is the output of this function. Known2 is a
-/// pre-allocated temporary with the same bit width as Known. KZF and KOF are
+/// pre-allocated temporary with the same bit width as Known and on return
+/// contains the known bit of the shift value source. KZF and KOF are
/// operator-specific functions that, given the known-zero or known-one bits
/// respectively, and a shift amount, compute the implied known-zero or
/// known-one bits of the shift operator's result respectively for that shift
@@ -991,13 +992,13 @@
function_ref<APInt(const APInt &, unsigned)> KOF) {
unsigned BitWidth = Known.getBitWidth();
+ computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
computeKnownBits(I->getOperand(1), DemandedElts, Known, Depth + 1, Q);
+
if (Known.isConstant()) {
unsigned ShiftAmt = Known.getConstant().getLimitedValue(BitWidth - 1);
-
- computeKnownBits(I->getOperand(0), DemandedElts, Known, Depth + 1, Q);
- Known.Zero = KZF(Known.Zero, ShiftAmt);
- Known.One = KOF(Known.One, ShiftAmt);
+ Known.Zero = KZF(Known2.Zero, ShiftAmt);
+ Known.One = KOF(Known2.One, ShiftAmt);
// If the known bits conflict, this must be an overflowing left shift, so
// the shift result is poison. We can return anything we want. Choose 0 for
// the best folding opportunity.
@@ -1040,8 +1041,6 @@
return;
}
- computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
-
Known.Zero.setAllBits();
Known.One.setAllBits();
for (unsigned ShiftAmt = 0; ShiftAmt < BitWidth; ++ShiftAmt) {
@@ -1258,6 +1257,12 @@
computeKnownBitsFromShiftOperator(I, DemandedElts, Known, Known2, Depth, Q,
KZF, KOF);
+
+ if (!Known.isConstant()) {
+ // No matter the shift amount, the trailing zeros will stay zero.
+ Known.Zero.setLowBits(Known2.countMinTrailingZeros());
+ assert(!Known.hasConflict() && "Known bits conflict from Shl");
+ }
break;
}
case Instruction::LShr: {
@@ -1275,6 +1280,12 @@
computeKnownBitsFromShiftOperator(I, DemandedElts, Known, Known2, Depth, Q,
KZF, KOF);
+
+ if (!Known.isConstant()) {
+ // No matter the shift amount, the leading zeros will stay zero.
+ Known.Zero.setHighBits(Known2.countMinLeadingZeros());
+ assert(!Known.hasConflict() && "Known bits conflict from LShr");
+ }
break;
}
case Instruction::AShr: {
diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll
--- a/llvm/test/Transforms/InstCombine/and2.ll
+++ b/llvm/test/Transforms/InstCombine/and2.ll
@@ -150,9 +150,8 @@
define i8 @and1_lshr1_is_cmp_eq_0(i8 %x) {
; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
-; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP1]] to i8
-; CHECK-NEXT: ret i8 [[AND]]
+; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]]
+; CHECK-NEXT: ret i8 [[SH]]
;
%sh = lshr i8 1, %x
%and = and i8 %sh, 1
@@ -164,8 +163,7 @@
define i8 @and1_lshr1_is_cmp_eq_0_multiuse(i8 %x) {
; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_multiuse(
; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1
-; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i8 [[SH]], [[AND]]
+; CHECK-NEXT: [[ADD:%.*]] = shl nuw nsw i8 [[SH]], 1
; CHECK-NEXT: ret i8 [[ADD]]
;
%sh = lshr i8 1, %x
@@ -178,9 +176,8 @@
define <2 x i8> @and1_lshr1_is_cmp_eq_0_vec(<2 x i8> %x) {
; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
-; CHECK-NEXT: ret <2 x i8> [[AND]]
+; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> <i8 1, i8 1>, [[X:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[SH]]
;
%sh = lshr <2 x i8> <i8 1, i8 1>, %x
%and = and <2 x i8> %sh, <i8 1, i8 1>
diff --git a/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
--- a/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
@@ -184,7 +184,8 @@
define i1 @scalar_i32_lshr_and_negC_eq_X_is_constant1(i32 %y) {
; CHECK-LABEL: @scalar_i32_lshr_and_negC_eq_X_is_constant1(
; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 12345, [[Y:%.*]]
-; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[LSHR]], 8
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[LSHR]], 16376
+; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%lshr = lshr i32 12345, %y
@@ -196,7 +197,8 @@
define i1 @scalar_i32_lshr_and_negC_eq_X_is_constant2(i32 %y) {
; CHECK-LABEL: @scalar_i32_lshr_and_negC_eq_X_is_constant2(
; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 268435456, [[Y:%.*]]
-; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[LSHR]], 8
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[LSHR]], 536870904
+; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%lshr = lshr i32 268435456, %y
diff --git a/llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll
--- a/llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll
@@ -187,10 +187,7 @@
define i1 @scalar_i32_signbit_shl_and_eq_X_is_constant1(i32 %y) {
; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_X_is_constant1(
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], 12345
-; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: ret i1 true
;
%shl = shl i32 2147483648, %y
%and = and i32 %shl, 12345
@@ -200,10 +197,7 @@
define i1 @scalar_i32_signbit_shl_and_eq_X_is_constant2(i32 %y) {
; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_X_is_constant2(
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], 1
-; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: ret i1 true
;
%shl = shl i32 2147483648, %y
%and = and i32 %shl, 1
@@ -219,7 +213,7 @@
; CHECK-LABEL: @scalar_i32_signbit_shl_and_slt(
; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]]
-; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[AND]], 0
+; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%shl = shl i32 2147483648, %y
@@ -232,10 +226,7 @@
define i1 @scalar_i32_signbit_shl_and_eq_nonzero(i32 %x, i32 %y) {
; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_nonzero(
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 1
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: ret i1 false
;
%shl = shl i32 2147483648, %y
%and = and i32 %shl, %x
diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
--- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
@@ -32,10 +32,7 @@
; CHECK-NEXT: br label [[BLOCK2]]
; CHECK: block2:
; CHECK-NEXT: [[CMP_I:%.*]] = phi i1 [ false, [[BLOCK1:%.*]] ], [ true, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[M_011:%.*]] = phi i32 [ 0, [[BLOCK1]] ], [ 33, [[ENTRY]] ]
-; CHECK-NEXT: [[M_1_OP:%.*]] = lshr i32 1, [[M_011]]
-; CHECK-NEXT: [[SEXT_MASK:%.*]] = and i32 [[M_1_OP]], 65535
-; CHECK-NEXT: [[CMP115:%.*]] = icmp ne i32 [[SEXT_MASK]], 0
+; CHECK-NEXT: [[CMP115:%.*]] = phi i1 [ true, [[BLOCK1]] ], [ false, [[ENTRY]] ]
; CHECK-NEXT: [[CMP1:%.*]] = or i1 [[CMP_I]], [[CMP115]]
; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP1]] to i32
; CHECK-NEXT: ret i32 [[CONV2]]