diff --git a/llvm/lib/Target/VE/VE.td b/llvm/lib/Target/VE/VE.td
--- a/llvm/lib/Target/VE/VE.td
+++ b/llvm/lib/Target/VE/VE.td
@@ -18,6 +18,9 @@
 //===----------------------------------------------------------------------===//
 // VE Subtarget features.
 //
+def FeatureEnableVPU
+  : SubtargetFeature<"vpu", "EnableVPU", "true",
+                     "Disable the VPU">;
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -45,7 +45,7 @@
 
   void initRegisterClasses();
   void initSPUActions();
-  // TODO void initVPUActions();
+  void initVPUActions();
 
 public:
   VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -57,46 +57,48 @@
   addRegisterClass(MVT::f64, &VE::I64RegClass);
   addRegisterClass(MVT::f128, &VE::F128RegClass);
 
-  addRegisterClass(MVT::v2i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v4i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v8i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v16i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v32i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v64i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v128i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v256i32, &VE::V64RegClass);
-  addRegisterClass(MVT::v512i32, &VE::V64RegClass);
-
-  addRegisterClass(MVT::v2i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v4i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v8i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v16i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v32i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v64i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v128i64, &VE::V64RegClass);
-  addRegisterClass(MVT::v256i64, &VE::V64RegClass);
-
-  addRegisterClass(MVT::v2f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v4f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v8f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v16f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v32f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v64f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v128f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v256f32, &VE::V64RegClass);
-  addRegisterClass(MVT::v512f32, &VE::V64RegClass);
-
-  addRegisterClass(MVT::v2f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v4f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v8f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v16f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v32f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v64f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v128f64, &VE::V64RegClass);
-  addRegisterClass(MVT::v256f64, &VE::V64RegClass);
-
-  addRegisterClass(MVT::v256i1, &VE::VMRegClass);
-  addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
+  if (Subtarget->enableVPU()) {
+    addRegisterClass(MVT::v2i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v4i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v8i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v16i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v32i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v64i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v128i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v256i32, &VE::V64RegClass);
+    addRegisterClass(MVT::v512i32, &VE::V64RegClass);
+
+    addRegisterClass(MVT::v2i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v4i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v8i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v16i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v32i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v64i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v128i64, &VE::V64RegClass);
+    addRegisterClass(MVT::v256i64, &VE::V64RegClass);
+
+    addRegisterClass(MVT::v2f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v4f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v8f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v16f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v32f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v64f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v128f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v256f32, &VE::V64RegClass);
+    addRegisterClass(MVT::v512f32, &VE::V64RegClass);
+
+    addRegisterClass(MVT::v2f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v4f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v8f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v16f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v32f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v64f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v128f64, &VE::V64RegClass);
+    addRegisterClass(MVT::v256f64, &VE::V64RegClass);
+
+    addRegisterClass(MVT::v256i1, &VE::VMRegClass);
+    addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
+  }
 }
 
 void VETargetLowering::initSPUActions() {
@@ -262,6 +264,10 @@
   /// } Atomic isntructions
 }
 
+void VETargetLowering::initVPUActions() {
+  // TODO upstream vector isel
+}
+
 SDValue
 VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                               bool IsVarArg,
@@ -842,7 +848,7 @@
 
   initRegisterClasses();
   initSPUActions();
-  // TODO initVPUActions();
+  initVPUActions();
 
   setStackPointerRegisterToSaveRestore(VE::SX11);
 
diff --git a/llvm/lib/Target/VE/VESubtarget.h b/llvm/lib/Target/VE/VESubtarget.h
--- a/llvm/lib/Target/VE/VESubtarget.h
+++ b/llvm/lib/Target/VE/VESubtarget.h
@@ -32,6 +32,13 @@
   Triple TargetTriple;
   virtual void anchor();
 
+  /// Features {
+
+  // Emit VPU instructions
+  bool EnableVPU;
+
+  /// } Features
+
   VEInstrInfo InstrInfo;
   VETargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
@@ -55,6 +62,8 @@
 
   bool enableMachineScheduler() const override;
 
+  bool enableVPU() const { return EnableVPU; }
+
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
diff --git a/llvm/lib/Target/VE/VESubtarget.cpp b/llvm/lib/Target/VE/VESubtarget.cpp
--- a/llvm/lib/Target/VE/VESubtarget.cpp
+++ b/llvm/lib/Target/VE/VESubtarget.cpp
@@ -27,6 +27,9 @@
 
 VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                           StringRef FS) {
+  // Default feature settings
+  EnableVPU = false;
+
   // Determine default and user specified characteristics
   std::string CPUName = std::string(CPU);
   if (CPUName.empty())
diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h
--- a/llvm/lib/Target/VE/VETargetTransformInfo.h
+++ b/llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -33,16 +33,52 @@
   const VESubtarget *getST() const { return ST; }
   const VETargetLowering *getTLI() const { return TLI; }
 
+  bool enableVPU() const { return getST()->enableVPU(); }
+
 public:
   explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
         TLI(ST->getTargetLowering()) {}
 
-  unsigned getNumberOfRegisters(unsigned ClassID) const { return 64; }
+  unsigned getNumberOfRegisters(unsigned ClassID) const {
+    bool VectorRegs = (ClassID == 1);
+    if (VectorRegs) {
+      // TODO report vregs once vector isel is stable.
+      return 0;
+    }
+
+    return 64;
+  }
+
+  unsigned getRegisterBitWidth(bool Vector) const {
+    if (Vector) {
+      // TODO report vregs once vector isel is stable.
+      return 0;
+    }
+    return 64;
+  }
+
+  unsigned getMinVectorRegisterBitWidth() const {
+    // TODO report vregs once vector isel is stable.
+    return 0;
+  }
 
-  unsigned getRegisterBitWidth(bool Vector) const { return 64; }
+  /// Load & Store {
+  bool isLegalMaskedLoad(Type *DataType, MaybeAlign Alignment) { return false; }
+  bool isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) {
+    return false;
+  }
+  bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) {
+    return false;
+  };
+  bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) {
+    return false;
+  }
+  /// } Load & Store
 
-  unsigned getMinVectorRegisterBitWidth() const { return 64; }
+  /// Reductions {
+  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
+  /// } Reductions
 };
 
 } // namespace llvm