diff --git a/clang/test/CodeGen/X86/ms-inline-asm-prefix.c b/clang/test/CodeGen/X86/ms-inline-asm-prefix.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/X86/ms-inline-asm-prefix.c
@@ -0,0 +1,14 @@
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o -  | FileCheck %s -check-prefix CHECK
+
+void check_inline_prefix(void) {
+  __asm {
+// CHECK: vex     vcvtps2pd       xmm0, xmm1
+// CHECK: vex     vcvtps2pd       xmm0, xmm1
+// CHECK: vex3    vcvtps2pd       xmm0, xmm1
+// CHECK: evex    vcvtps2pd       xmm0, xmm1
+    vex vcvtps2pd xmm0, xmm1
+    vex2 vcvtps2pd xmm0, xmm1
+    vex3 vcvtps2pd xmm0, xmm1
+    evex vcvtps2pd xmm0, xmm1
+  }
+}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2847,7 +2847,30 @@
       }
       continue;
     }
-
+    // Parse MASM style pseudo prefixes.
+    if (isParsingIntelSyntax()) {
+      bool IsPrefix = false;
+      if (Name == "vex" || Name == "vex2") {
+        ForcedVEXEncoding = VEXEncoding_VEX;
+        IsPrefix = true;
+      }
+      else if (Name == "vex3") {
+        ForcedVEXEncoding = VEXEncoding_VEX3;
+        IsPrefix = true;
+      }
+      else if (Name == "evex") {
+        ForcedVEXEncoding = VEXEncoding_EVEX;
+        IsPrefix = true;
+      }
+      if (IsPrefix) {
+        NameLoc = Parser.getTok().getLoc();
+        if (getLexer().isNot(AsmToken::Identifier))
+          return Error(Parser.getTok().getLoc(), "Expected identifier");
+        // FIXME: The mnemonic won't match correctly if its not in lower case.
+        Name = Parser.getTok().getString();
+        Parser.Lex();
+      }
+    }
     break;
   }
 
@@ -4146,10 +4169,16 @@
 
   MCInst Inst;
 
-  // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
-  // encoder.
-  if (ForcedVEXEncoding == VEXEncoding_VEX3)
+  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
+  // encoder and printer.
+  if (ForcedVEXEncoding == VEXEncoding_VEX)
+    Prefixes |= X86::IP_USE_VEX;
+  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
+    Prefixes |= X86::IP_USE_VEX2;
+  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
     Prefixes |= X86::IP_USE_VEX3;
+  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
+    Prefixes |= X86::IP_USE_EVEX;
 
   // Set encoded flags for {disp8} and {disp32}.
   if (ForcedDispEncoding == DispEncoding_Disp8)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -48,6 +48,22 @@
 
   printInstFlags(MI, OS);
 
+  unsigned Flags = MI->getFlags();
+  // These all require a pseudo prefix
+  if (Flags & X86::IP_USE_VEX)
+    OS << "\t{vex}";
+  else if (Flags & X86::IP_USE_VEX2)
+    OS << "\t{vex2}";
+  else if (Flags & X86::IP_USE_VEX3)
+    OS << "\t{vex3}";
+  else if (Flags & X86::IP_USE_EVEX)
+    OS << "\t{evex}";
+
+  if (Flags & X86::IP_USE_DISP8)
+    OS << "\t{disp8}";
+  else if (Flags & X86::IP_USE_DISP32)
+    OS << "\t{disp32}";
+
   // Output CALLpcrel32 as "callq" in 64-bit mode.
   // In Intel annotation it's always emitted as "call".
   //
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
@@ -346,21 +346,6 @@
     O << "\trepne\t";
   else if (Flags & X86::IP_HAS_REPEAT)
     O << "\trep\t";
-
-  // These all require a pseudo prefix
-  if (Flags & X86::IP_USE_VEX)
-    O << "\t{vex}";
-  else if (Flags & X86::IP_USE_VEX2)
-    O << "\t{vex2}";
-  else if (Flags & X86::IP_USE_VEX3)
-    O << "\t{vex3}";
-  else if (Flags & X86::IP_USE_EVEX)
-    O << "\t{evex}";
-
-  if (Flags & X86::IP_USE_DISP8)
-    O << "\t{disp8}";
-  else if (Flags & X86::IP_USE_DISP32)
-    O << "\t{disp32}";
 }
 
 void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
--- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -42,6 +42,17 @@
                                     raw_ostream &OS) {
   printInstFlags(MI, OS);
 
+  unsigned Flags = MI->getFlags();
+  // These all require a pseudo prefix
+  if (Flags & X86::IP_USE_VEX)
+    OS << "\tvex";
+  else if (Flags & X86::IP_USE_VEX2)
+    OS << "\tvex2";
+  else if (Flags & X86::IP_USE_VEX3)
+    OS << "\tvex3";
+  else if (Flags & X86::IP_USE_EVEX)
+    OS << "\tevex";
+
   // In 16-bit mode, print data16 as data32.
   if (MI->getOpcode() == X86::DATA16_PREFIX &&
       STI.getFeatureBits()[X86::Mode16Bit]) {