diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -2507,15 +2507,11 @@
   SDValue Chain = N->getOperand(0);
   SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32);
 
-  // TODO: Can this just be removed from the instruction?
-  SDValue GDS = CurDAG->getTargetConstant(1, SL, MVT::i1);
-
   const unsigned Opc = gwsIntrinToOpcode(IntrID);
   SmallVector<SDValue, 5> Ops;
   if (HasVSrc)
     Ops.push_back(N->getOperand(2));
   Ops.push_back(OffsetField);
-  Ops.push_back(GDS);
   Ops.push_back(Chain);
 
   SDNode *Selected = CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1392,7 +1392,6 @@
   }
 
   MIB.addImm(ImmOffset)
-     .addImm(-1) // $gds
      .cloneMemRefs(MI);
 
   MI.eraseFromParent();
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -330,13 +330,13 @@
 
 class DS_GWS_0D <string opName>
 : DS_GWS<opName,
-  (ins offset:$offset, gds:$gds), "$offset gds"> {
+  (ins offset:$offset), "$offset gds"> {
   let hasSideEffects = 1;
 }
 
 class DS_GWS_1D <string opName>
 : DS_GWS<opName,
-  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
+  (ins VGPR_32:$data0, offset:$offset), "$data0$offset gds"> {
 
   let has_gws_data0 = 1;
   let hasSideEffects = 1;
diff --git a/llvm/test/CodeGen/AMDGPU/gws-hazards.mir b/llvm/test/CodeGen/AMDGPU/gws-hazards.mir
--- a/llvm/test/CodeGen/AMDGPU/gws-hazards.mir
+++ b/llvm/test/CodeGen/AMDGPU/gws-hazards.mir
@@ -15,22 +15,22 @@
     ; GFX9: liveins: $vgpr0
     ; GFX9: $m0 = S_MOV_B32 -1
     ; GFX9: S_NOP 0
-    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; VI-LABEL: name: m0_gws_init0
     ; VI: liveins: $vgpr0
     ; VI: $m0 = S_MOV_B32 -1
     ; VI: S_NOP 0
-    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; CI-LABEL: name: m0_gws_init0
     ; CI: liveins: $vgpr0
     ; CI: $m0 = S_MOV_B32 -1
-    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; SI-LABEL: name: m0_gws_init0
     ; SI: liveins: $vgpr0
     ; SI: $m0 = S_MOV_B32 -1
-    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
 
 ...
 
@@ -44,23 +44,23 @@
     ; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; GFX9: $m0 = S_MOV_B32 -1
     ; GFX9: S_NOP 0
-    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; VI-LABEL: name: m0_gws_init1
     ; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; VI: $m0 = S_MOV_B32 -1
     ; VI: S_NOP 0
-    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; CI-LABEL: name: m0_gws_init1
     ; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; CI: $m0 = S_MOV_B32 -1
-    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; SI-LABEL: name: m0_gws_init1
     ; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; SI: $m0 = S_MOV_B32 -1
-    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
 
 ...
 
@@ -79,25 +79,25 @@
     ; GFX9: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; GFX9: $m0 = S_MOV_B32 $sgpr0
     ; GFX9: S_NOP 0
-    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; VI-LABEL: name: m0_gws_readlane
     ; VI: liveins: $vgpr0, $vgpr1
     ; VI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; VI: $m0 = S_MOV_B32 $sgpr0
     ; VI: S_NOP 0
-    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; CI-LABEL: name: m0_gws_readlane
     ; CI: liveins: $vgpr0, $vgpr1
     ; CI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; CI: $m0 = S_MOV_B32 $sgpr0
-    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; SI-LABEL: name: m0_gws_readlane
     ; SI: liveins: $vgpr0, $vgpr1
     ; SI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; SI: $m0 = S_MOV_B32 $sgpr0
-    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     $m0 = S_MOV_B32 $sgpr0
-    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
 
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir b/llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
--- a/llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
+++ b/llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
@@ -14,7 +14,7 @@
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-  ; CHECK:   DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+  ; CHECK:   DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
@@ -24,7 +24,7 @@
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-    DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
@@ -42,7 +42,7 @@
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-  ; CHECK:   DS_GWS_BARRIER $vgpr0, 0, 1, implicit $m0, implicit $exec
+  ; CHECK:   DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
@@ -52,7 +52,7 @@
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-    DS_GWS_BARRIER $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
@@ -27,7 +27,7 @@
 
 ; MIR-LABEL: name: gws_barrier_offset0{{$}}
 ; MIR: BUNDLE implicit{{( killed)?( renamable)?}} $vgpr0, implicit $m0, implicit $exec {
-; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, -1, implicit $m0, implicit $exec :: (load 4 from custom "GWSResource")
+; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load 4 from custom "GWSResource")
 ; MIR-NEXT: S_WAITCNT 0
 ; MIR-NEXT: }
 define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/merge-m0.mir b/llvm/test/CodeGen/AMDGPU/merge-m0.mir
--- a/llvm/test/CodeGen/AMDGPU/merge-m0.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-m0.mir
@@ -231,21 +231,21 @@
 # GCN-LABEL: name: move-m0-avoid-hazard
 # GCN: $m0 = S_MOV_B32 -1
 # GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ---
 name: move-m0-avoid-hazard
 body:             |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ...
 
 # GCN-LABEL: name: move-m0-with-prologue
 # GCN: $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
 # GCN: $m0 = S_MOV_B32 -1
 # GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ---
 name: move-m0-with-prologue
 body:             |
@@ -255,7 +255,7 @@
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ...
 
 # GCN-LABEL: name: move-m0-different-initializer
diff --git a/llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir b/llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
--- a/llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
+++ b/llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
@@ -20,22 +20,22 @@
     ; CHECK: $m0 = S_MOV_B32 -1
     ; CHECK: $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     ; CHECK: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
-    ; CHECK:   DS_GWS_INIT $vgpr0, 8, -1, implicit $m0, implicit $exec
+    ; CHECK:   DS_GWS_INIT $vgpr0, 8, implicit $m0, implicit $exec
     ; CHECK:   S_WAITCNT 0
     ; CHECK: }
     ; CHECK: BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
-    ; CHECK:   DS_GWS_BARRIER killed $vgpr0, 8, -1, implicit $m0, implicit $exec
+    ; CHECK:   DS_GWS_BARRIER killed $vgpr0, 8, implicit $m0, implicit $exec
     ; CHECK:   S_WAITCNT 0
     ; CHECK: }
     renamable $sgpr0 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 0, 0, 0
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
     BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
-      DS_GWS_INIT $vgpr0, 8, -1, implicit $m0, implicit $exec
+      DS_GWS_INIT $vgpr0, 8, implicit $m0, implicit $exec
       S_WAITCNT 0
     }
     BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
-      DS_GWS_BARRIER $vgpr0, 8, -1, implicit $m0, implicit $exec
+      DS_GWS_BARRIER $vgpr0, 8, implicit $m0, implicit $exec
       S_WAITCNT 0
     }
 
diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir b/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
--- a/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
+++ b/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
@@ -28,7 +28,7 @@
     ; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
     ; GCN: $m0 = S_MOV_B32 0
     ; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
-    ; GCN:   DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
+    ; GCN:   DS_GWS_INIT $vgpr0, 11, implicit $m0, implicit $exec :: (store 4)
     ; GCN:   S_WAITCNT 0
     ; GCN: }
     ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3)
@@ -42,7 +42,7 @@
     $m0 = S_MOV_B32 0
     $vgpr0 = COPY %5
     BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
-      DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
+      DS_GWS_INIT $vgpr0, 11, implicit $m0, implicit $exec :: (store 4)
       S_WAITCNT 0
     }
     %8:vgpr_32 = V_MOV_B32_e32 2, implicit $exec