[AMDGPU] Remove gds operand from ds_gws_* MachineInstrs

[foad]

Summary

The operand value was always 1 (except in some bad MIR tests) so it was
redundant.

[arsenm]

I wonder if the instruction completely ignores it or not

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

SDNode *M0Base
                                SDValue(SGPROffset, 0),
                                CurDAG->getTargetConstant(16, SL, MVT::i32));
     glueCopyToM0(N, SDValue(M0Base, 0));
   }
 
   SDValue Chain = N->getOperand(0);
   SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32);
 
-  // TODO: Can this just be removed from the instruction?
-  SDValue GDS = CurDAG->getTargetConstant(1, SL, MVT::i1);
-
   const unsigned Opc = gwsIntrinToOpcode(IntrID);
   SmallVector<SDValue, 5> Ops;
   if (HasVSrc)
     Ops.push_back(N->getOperand(2));
   Ops.push_back(OffsetField);
-  Ops.push_back(GDS);
   Ops.push_back(Chain);
 
   SDNode *Selected = CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
   CurDAG->setNodeMemRefs(cast<MachineSDNode>(Selected), {MMO});
 }
 
 void AMDGPUDAGToDAGISel::SelectInterpP1F16(SDNode *N) {
   if (Subtarget->getLDSBankCount() != 16) {

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::selectDSGWSIntrinsic(MachineInstr &MI,
   if (HasVSrc) {
     Register VSrc = MI.getOperand(1).getReg();
     MIB.addReg(VSrc);
     if (!RBI.constrainGenericRegister(VSrc, AMDGPU::VGPR_32RegClass, *MRI))
       return false;
   }
 
   MIB.addImm(ImmOffset)
-     .addImm(-1) // $gds
      .cloneMemRefs(MI);
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI,
                                                       bool IsAppend) const {

llvm/lib/Target/AMDGPU/DSInstructions.td

: DS_Pseudo<opName, (outs), ins, asmOps> {
 
   let has_gds   = 0;
   let gdsValue  = 1;
   let AsmMatchConverter = "cvtDSGds";
 }
 
 class DS_GWS_0D <string opName>
 : DS_GWS<opName,
-  (ins offset:$offset, gds:$gds), "$offset gds"> {
+  (ins offset:$offset), "$offset gds"> {
   let hasSideEffects = 1;
 }
 
 class DS_GWS_1D <string opName>
 : DS_GWS<opName,
-  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
+  (ins VGPR_32:$data0, offset:$offset), "$data0$offset gds"> {
 
   let has_gws_data0 = 1;
   let hasSideEffects = 1;
 }
 
 class DS_VOID <string opName> : DS_Pseudo<opName,
   (outs), (ins), ""> {
   let mayLoad = 0;

llvm/test/CodeGen/AMDGPU/gws-hazards.mir

 body: |
 
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: m0_gws_init0
     ; GFX9: liveins: $vgpr0
     ; GFX9: $m0 = S_MOV_B32 -1
     ; GFX9: S_NOP 0
-    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; VI-LABEL: name: m0_gws_init0
     ; VI: liveins: $vgpr0
     ; VI: $m0 = S_MOV_B32 -1
     ; VI: S_NOP 0
-    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; CI-LABEL: name: m0_gws_init0
     ; CI: liveins: $vgpr0
     ; CI: $m0 = S_MOV_B32 -1
-    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; SI-LABEL: name: m0_gws_init0
     ; SI: liveins: $vgpr0
     ; SI: $m0 = S_MOV_B32 -1
-    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
 
 ...
 
 ---
 name: m0_gws_init1
 tracksRegLiveness: true
 body: |
 
   bb.0:
     ; GFX9-LABEL: name: m0_gws_init1
     ; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; GFX9: $m0 = S_MOV_B32 -1
     ; GFX9: S_NOP 0
-    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; VI-LABEL: name: m0_gws_init1
     ; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; VI: $m0 = S_MOV_B32 -1
     ; VI: S_NOP 0
-    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; CI-LABEL: name: m0_gws_init1
     ; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; CI: $m0 = S_MOV_B32 -1
-    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; SI-LABEL: name: m0_gws_init1
     ; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     ; SI: $m0 = S_MOV_B32 -1
-    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
 
 ...
 
 # Test a typical situation where m0 needs to be set from a VGPR
 # through readfirstlane
 ---
 name: m0_gws_readlane
 tracksRegLiveness: true
 body: |
 
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX9-LABEL: name: m0_gws_readlane
     ; GFX9: liveins: $vgpr0, $vgpr1
     ; GFX9: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; GFX9: $m0 = S_MOV_B32 $sgpr0
     ; GFX9: S_NOP 0
-    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; VI-LABEL: name: m0_gws_readlane
     ; VI: liveins: $vgpr0, $vgpr1
     ; VI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; VI: $m0 = S_MOV_B32 $sgpr0
     ; VI: S_NOP 0
-    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; CI-LABEL: name: m0_gws_readlane
     ; CI: liveins: $vgpr0, $vgpr1
     ; CI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; CI: $m0 = S_MOV_B32 $sgpr0
-    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     ; SI-LABEL: name: m0_gws_readlane
     ; SI: liveins: $vgpr0, $vgpr1
     ; SI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     ; SI: $m0 = S_MOV_B32 $sgpr0
-    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
     $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
     $m0 = S_MOV_B32 $sgpr0
-    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
 
 ...

llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 -verify-machineinstrs  %s -o - | FileCheck %s
 # Make sure mandatory skips are inserted to ensure GWS ops aren't run with exec = 0
 
 ---
 
 name: skip_gws_init
 body: |
   ; CHECK-LABEL: name: skip_gws_init
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-  ; CHECK:   DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+  ; CHECK:   DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
     SI_MASK_BRANCH %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-    DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
 ...
 
 ---
 
 name: skip_gws_barrier
 body: |
   ; CHECK-LABEL: name: skip_gws_barrier
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-  ; CHECK:   DS_GWS_BARRIER $vgpr0, 0, 1, implicit $m0, implicit $exec
+  ; CHECK:   DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
     SI_MASK_BRANCH %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-    DS_GWS_BARRIER $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
 ...

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll

 ; LOOP-NEXT: ds_gws_barrier v0 gds
 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
 
 ; MIR-LABEL: name: gws_barrier_offset0{{$}}
 ; MIR: BUNDLE implicit{{( killed)?( renamable)?}} $vgpr0, implicit $m0, implicit $exec {
-; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, -1, implicit $m0, implicit $exec :: (load 4 from custom "GWSResource")
+; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load 4 from custom "GWSResource")
 ; MIR-NEXT: S_WAITCNT 0
 ; MIR-NEXT: }
 define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
   call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
   ret void
 }
 
 ; MIR-LABEL: name: gws_barrier_offset63{{$}}

llvm/test/CodeGen/AMDGPU/merge-m0.mir

body:             |
 
   bb.3:
     S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: move-m0-avoid-hazard
 # GCN: $m0 = S_MOV_B32 -1
 # GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ---
 name: move-m0-avoid-hazard
 body:             |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ...
 
 # GCN-LABEL: name: move-m0-with-prologue
 # GCN: $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
 # GCN: $m0 = S_MOV_B32 -1
 # GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ---
 name: move-m0-with-prologue
 body:             |
   bb.0:
     liveins: $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
-    DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
+    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 ...
 
 # GCN-LABEL: name: move-m0-different-initializer
 # GCN: SI_INIT_M0 -1
 # GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
 # GCN: SI_INIT_M0 65536
 # GCN-NEXT: S_NOP
 ---

llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir

bb.0:
     liveins: $sgpr4_sgpr5, $sgpr7
 
     ; CHECK-LABEL: name: kill_flag_use_first_bundle_inst
     ; CHECK: liveins: $sgpr4_sgpr5, $sgpr7
     ; CHECK: renamable $sgpr0 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 0, 0, 0
     ; CHECK: $m0 = S_MOV_B32 -1
     ; CHECK: $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
     ; CHECK: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
-    ; CHECK:   DS_GWS_INIT $vgpr0, 8, -1, implicit $m0, implicit $exec
+    ; CHECK:   DS_GWS_INIT $vgpr0, 8, implicit $m0, implicit $exec
     ; CHECK:   S_WAITCNT 0
     ; CHECK: }
     ; CHECK: BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
-    ; CHECK:   DS_GWS_BARRIER killed $vgpr0, 8, -1, implicit $m0, implicit $exec
+    ; CHECK:   DS_GWS_BARRIER killed $vgpr0, 8, implicit $m0, implicit $exec
     ; CHECK:   S_WAITCNT 0
     ; CHECK: }
     renamable $sgpr0 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 0, 0, 0
     $m0 = S_MOV_B32 -1
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
     BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
-      DS_GWS_INIT $vgpr0, 8, -1, implicit $m0, implicit $exec
+      DS_GWS_INIT $vgpr0, 8, implicit $m0, implicit $exec
       S_WAITCNT 0
     }
     BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
-      DS_GWS_BARRIER $vgpr0, 8, -1, implicit $m0, implicit $exec
+      DS_GWS_BARRIER $vgpr0, 8, implicit $m0, implicit $exec
       S_WAITCNT 0
     }
 
 ...

llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir

bb.0:
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; GCN: $vcc_hi = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
     ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3)
     ; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
     ; GCN: $m0 = S_MOV_B32 0
     ; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
-    ; GCN:   DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
+    ; GCN:   DS_GWS_INIT $vgpr0, 11, implicit $m0, implicit $exec :: (store 4)
     ; GCN:   S_WAITCNT 0
     ; GCN: }
     ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3)
     ; GCN: S_ENDPGM 0
     $vcc_hi = IMPLICIT_DEF
     %2:sgpr_64 = COPY $sgpr4_sgpr5
     %5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %2, 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
     %6:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     %7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     DS_WRITE_B32_gfx9 %7, %6, 0, 0, implicit $exec :: (store 4, addrspace 3)
     $m0 = S_MOV_B32 0
     $vgpr0 = COPY %5
     BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
-      DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
+      DS_GWS_INIT $vgpr0, 11, implicit $m0, implicit $exec :: (store 4)
       S_WAITCNT 0
     }
     %8:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
     DS_WRITE_B32_gfx9 %7, %8, 0, 0, implicit $exec :: (store 4, addrspace 3)
     S_ENDPGM 0
 
 ...