diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1168,9 +1168,9 @@
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   if ((Val & ~ENABLE_MASK) != 0) {
-    O << " " << formatHex(static_cast<uint64_t>(Val));
+    O << formatHex(static_cast<uint64_t>(Val));
   } else {
-    O << " gpr_idx(";
+    O << "gpr_idx(";
     bool NeedComma = false;
     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
       if (Val & (1 << ModeId)) {
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1036,7 +1036,7 @@
   "s_set_gpr_idx_on" ,
   (outs),
   (ins SSrc_b32:$src0, GPRIdxMode:$src1),
-  "$src0,$src1"> {
+  "$src0, $src1"> {
   let Defs = [M0, MODE]; // No scc def
   let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified.
   let hasSideEffects = 1; // Sets mode.gpr_idx_en
@@ -1289,7 +1289,6 @@
 let SubtargetPredicate = HasVGPRIndexMode in {
 def S_SET_GPR_IDX_MODE : SOPP_Pseudo<"s_set_gpr_idx_mode", (ins GPRIdxMode:$simm16),
   "$simm16"> {
-  /*"s_set_gpr_idx_mode$simm16"> {*/
   let Defs = [M0, MODE];
   let Uses = [MODE];
 }
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
@@ -23703,13 +23703,13 @@
 # CHECK: s_set_gpr_idx_off                       ; encoding: [0x00,0x00,0x9c,0xbf]
 0x00,0x00,0x9c,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx()           ; encoding: [0x00,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx()            ; encoding: [0x00,0x00,0x9d,0xbf]
 0x00,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0)       ; encoding: [0x01,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0)        ; encoding: [0x01,0x00,0x9d,0xbf]
 0x01,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
 0x0f,0x00,0x9d,0xbf
 
 # CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x     ; encoding: [0x01,0x00,0x14,0xd4]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -20577,13 +20577,13 @@
 # CHECK: s_set_gpr_idx_off                       ; encoding: [0x00,0x00,0x9c,0xbf]
 0x00,0x00,0x9c,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx()           ; encoding: [0x00,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx()            ; encoding: [0x00,0x00,0x9d,0xbf]
 0x00,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0)       ; encoding: [0x01,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0)        ; encoding: [0x01,0x00,0x9d,0xbf]
 0x01,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
 0x0f,0x00,0x9d,0xbf
 
 # CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x     ; encoding: [0x01,0x00,0x14,0xd4]