This is an archive of the discontinued LLVM Phabricator instance.

Differential D90374

[AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode
ClosedPublic

Authored by foad on Oct 29 2020, 2:48 AM.

Details

Reviewers
dp
rampitec
arsenm
Commits
rGa442fad911b3: [AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode

Diff Detail

Event Timeline

foad created this revision.Oct 29 2020, 2:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 29 2020, 2:48 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 7 others. · View Herald Transcript
foad requested review of this revision.Oct 29 2020, 2:48 AM
Herald added a subscriber: wdng. · View Herald TranscriptOct 29 2020, 2:48 AM
Harbormaster completed remote builds in B76876: Diff 301545.Oct 29 2020, 3:27 AM
arsenm accepted this revision.Oct 29 2020, 6:47 AM
This revision is now accepted and ready to land.Oct 29 2020, 6:47 AM
This revision was landed with ongoing or failed builds.Oct 29 2020, 8:03 AM
Closed by commit rGa442fad911b3: [AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGa442fad911b3: [AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
MCTargetDesc/
4 lines
3 lines
test/
MC/
Disassembler/
AMDGPU/
6 lines
6 lines

Diff 301622

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Show First 20 Lines • Show All 1,162 Lines • ▼ Show 20 Lines
void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
using namespace llvm::AMDGPU::VGPRIndexMode; using namespace llvm::AMDGPU::VGPRIndexMode;
unsigned Val = MI->getOperand(OpNo).getImm(); unsigned Val = MI->getOperand(OpNo).getImm();
if ((Val & ~ENABLE_MASK) != 0) { if ((Val & ~ENABLE_MASK) != 0) {
O << " " << formatHex(static_cast<uint64_t>(Val)); O << formatHex(static_cast<uint64_t>(Val));
} else { } else {
O << " gpr_idx("; O << "gpr_idx(";
bool NeedComma = false; bool NeedComma = false;
for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
if (Val & (1 << ModeId)) { if (Val & (1 << ModeId)) {
if (NeedComma) if (NeedComma)
O << ','; O << ',';
O << IdSymbolic[ModeId]; O << IdSymbolic[ModeId];
NeedComma = true; NeedComma = true;
} }
▲ Show 20 Lines • Show All 463 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SOPInstructions.td

Show First 20 Lines • Show All 1,030 Lines • ▼ Show 20 Lines
// Setting the GPR index mode is really writing the fields in the mode // Setting the GPR index mode is really writing the fields in the mode
// register. We don't want to add mode register uses to every // register. We don't want to add mode register uses to every
// instruction, and it's too complicated to deal with anyway. This is // instruction, and it's too complicated to deal with anyway. This is
// modeled just as a side effect. // modeled just as a side effect.
def S_SET_GPR_IDX_ON : SOPC_Pseudo < def S_SET_GPR_IDX_ON : SOPC_Pseudo <
"s_set_gpr_idx_on" , "s_set_gpr_idx_on" ,
(outs), (outs),
(ins SSrc_b32:$src0, GPRIdxMode:$src1), (ins SSrc_b32:$src0, GPRIdxMode:$src1),
"$src0,$src1"> { "$src0, $src1"> {
let Defs = [M0, MODE]; // No scc def let Defs = [M0, MODE]; // No scc def
let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified. let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified.
let hasSideEffects = 1; // Sets mode.gpr_idx_en let hasSideEffects = 1; // Sets mode.gpr_idx_en
let FixedSize = 1; let FixedSize = 1;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 236 Lines • ▼ Show 20 Linesdef S_SET_GPR_IDX_OFF : SOPP_Pseudo<"s_set_gpr_idx_off", (ins) > {
let Uses = [MODE]; let Uses = [MODE];
} }
} }
} // End hasSideEffects } // End hasSideEffects
let SubtargetPredicate = HasVGPRIndexMode in { let SubtargetPredicate = HasVGPRIndexMode in {
def S_SET_GPR_IDX_MODE : SOPP_Pseudo<"s_set_gpr_idx_mode", (ins GPRIdxMode:$simm16), def S_SET_GPR_IDX_MODE : SOPP_Pseudo<"s_set_gpr_idx_mode", (ins GPRIdxMode:$simm16),
"$simm16"> { "$simm16"> {
/*"s_set_gpr_idx_mode$simm16"> {*/
let Defs = [M0, MODE]; let Defs = [M0, MODE];
let Uses = [MODE]; let Uses = [MODE];
} }
} }
let SubtargetPredicate = isGFX10Plus in { let SubtargetPredicate = isGFX10Plus in {
def S_INST_PREFETCH : def S_INST_PREFETCH :
SOPP_Pseudo<"s_inst_prefetch", (ins s16imm:$simm16), "$simm16">; SOPP_Pseudo<"s_inst_prefetch", (ins s16imm:$simm16), "$simm16">;
▲ Show 20 Lines • Show All 671 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt

Show First 20 Lines • Show All 23,697 Lines • ▼ Show 20 Lines
0xd1,0xc1,0x9a,0xbf 0xd1,0xc1,0x9a,0xbf
# CHECK: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf] # CHECK: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf]
0x00,0x00,0x9b,0xbf 0x00,0x00,0x9b,0xbf
# CHECK: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf] # CHECK: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf]
0x00,0x00,0x9c,0xbf 0x00,0x00,0x9c,0xbf
# CHECK: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf] # CHECK: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
0x00,0x00,0x9d,0xbf 0x00,0x00,0x9d,0xbf
# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0) ; encoding: [0x01,0x00,0x9d,0xbf] # CHECK: s_set_gpr_idx_mode gpr_idx(SRC0) ; encoding: [0x01,0x00,0x9d,0xbf]
0x01,0x00,0x9d,0xbf 0x01,0x00,0x9d,0xbf
# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf] # CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
0x0f,0x00,0x9d,0xbf 0x0f,0x00,0x9d,0xbf
# CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x ; encoding: [0x01,0x00,0x14,0xd4] # CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x ; encoding: [0x01,0x00,0x14,0xd4]
0x01,0x00,0x14,0xd4 0x01,0x00,0x14,0xd4
# CHECK: v_interp_p1_f32_e32 v255, v1, attr0.x ; encoding: [0x01,0x00,0xfc,0xd7] # CHECK: v_interp_p1_f32_e32 v255, v1, attr0.x ; encoding: [0x01,0x00,0xfc,0xd7]
0x01,0x00,0xfc,0xd7 0x01,0x00,0xfc,0xd7
▲ Show 20 Lines • Show All 65,527 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

Show First 20 Lines • Show All 20,571 Lines • ▼ Show 20 Lines
0xd1,0xc1,0x9a,0xbf 0xd1,0xc1,0x9a,0xbf
# CHECK: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf] # CHECK: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf]
0x00,0x00,0x9b,0xbf 0x00,0x00,0x9b,0xbf
# CHECK: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf] # CHECK: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf]
0x00,0x00,0x9c,0xbf 0x00,0x00,0x9c,0xbf
# CHECK: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf] # CHECK: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
0x00,0x00,0x9d,0xbf 0x00,0x00,0x9d,0xbf
# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0) ; encoding: [0x01,0x00,0x9d,0xbf] # CHECK: s_set_gpr_idx_mode gpr_idx(SRC0) ; encoding: [0x01,0x00,0x9d,0xbf]
0x01,0x00,0x9d,0xbf 0x01,0x00,0x9d,0xbf
# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf] # CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
0x0f,0x00,0x9d,0xbf 0x0f,0x00,0x9d,0xbf
# CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x ; encoding: [0x01,0x00,0x14,0xd4] # CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x ; encoding: [0x01,0x00,0x14,0xd4]
0x01,0x00,0x14,0xd4 0x01,0x00,0x14,0xd4
# CHECK: v_interp_p1_f32_e32 v255, v1, attr0.x ; encoding: [0x01,0x00,0xfc,0xd7] # CHECK: v_interp_p1_f32_e32 v255, v1, attr0.x ; encoding: [0x01,0x00,0xfc,0xd7]
0x01,0x00,0xfc,0xd7 0x01,0x00,0xfc,0xd7
▲ Show 20 Lines • Show All 65,527 Lines • Show Last 20 Lines