diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -35,6 +35,7 @@ #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/InitializePasses.h" #include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCRegister.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Pass.h" #include "llvm/Support/Allocator.h" @@ -115,18 +116,18 @@ bool PerformTrivialCopyPropagation(MachineInstr *MI, MachineBasicBlock *MBB); - bool isPhysDefTriviallyDead(unsigned Reg, + bool isPhysDefTriviallyDead(MCRegister Reg, MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator E) const; bool hasLivePhysRegDefUses(const MachineInstr *MI, const MachineBasicBlock *MBB, - SmallSet &PhysRefs, + SmallSet &PhysRefs, PhysDefVector &PhysDefs, bool &PhysUseDef) const; bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, - SmallSet &PhysRefs, + SmallSet &PhysRefs, PhysDefVector &PhysDefs, bool &NonLocal) const; bool isCSECandidate(MachineInstr *MI); - bool isProfitableToCSE(unsigned CSReg, unsigned Reg, + bool isProfitableToCSE(Register CSReg, Register Reg, MachineBasicBlock *CSBB, MachineInstr *MI); void EnterScope(MachineBasicBlock *MBB); void ExitScope(MachineBasicBlock *MBB); @@ -218,10 +219,9 @@ return Changed; } -bool -MachineCSE::isPhysDefTriviallyDead(unsigned Reg, - MachineBasicBlock::const_iterator I, - MachineBasicBlock::const_iterator E) const { +bool MachineCSE::isPhysDefTriviallyDead( + MCRegister Reg, MachineBasicBlock::const_iterator I, + MachineBasicBlock::const_iterator E) const { unsigned LookAheadLeft = LookAheadLimit; while (LookAheadLeft) { // Skip over dbg_value's. @@ -255,7 +255,7 @@ return false; } -static bool isCallerPreservedOrConstPhysReg(unsigned Reg, +static bool isCallerPreservedOrConstPhysReg(MCRegister Reg, const MachineFunction &MF, const TargetRegisterInfo &TRI) { // MachineRegisterInfo::isConstantPhysReg directly called by @@ -276,7 +276,7 @@ /// instruction does not uses a physical register. bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI, const MachineBasicBlock *MBB, - SmallSet &PhysRefs, + SmallSet &PhysRefs, PhysDefVector &PhysDefs, bool &PhysUseDef) const { // First, add all uses to PhysRefs. @@ -289,7 +289,7 @@ if (Register::isVirtualRegister(Reg)) continue; // Reading either caller preserved or constant physregs is ok. - if (!isCallerPreservedOrConstPhysReg(Reg, *MI->getMF(), *TRI)) + if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), *MI->getMF(), *TRI)) for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) PhysRefs.insert(*AI); } @@ -308,12 +308,12 @@ if (Register::isVirtualRegister(Reg)) continue; // Check against PhysRefs even if the def is "dead". - if (PhysRefs.count(Reg)) + if (PhysRefs.count(Reg.asMCReg())) PhysUseDef = true; // If the def is dead, it's ok. But the def may not marked "dead". That's // common since this pass is run before livevariables. We can scan // forward a few instructions and check if it is obviously dead. - if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end())) + if (!MO.isDead() && !isPhysDefTriviallyDead(Reg.asMCReg(), I, MBB->end())) PhysDefs.push_back(std::make_pair(MOP.index(), Reg)); } @@ -327,7 +327,7 @@ } bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, - SmallSet &PhysRefs, + SmallSet &PhysRefs, PhysDefVector &PhysDefs, bool &NonLocal) const { // For now conservatively returns false if the common subexpression is @@ -382,7 +382,7 @@ Register MOReg = MO.getReg(); if (Register::isVirtualRegister(MOReg)) continue; - if (PhysRefs.count(MOReg)) + if (PhysRefs.count(MOReg.asMCReg())) return false; } @@ -429,7 +429,7 @@ /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a /// common expression that defines Reg. CSBB is basic block where CSReg is /// defined. -bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, +bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg, MachineBasicBlock *CSBB, MachineInstr *MI) { // FIXME: Heuristics that works around the lack the live range splitting. @@ -556,7 +556,7 @@ // used, then it's not safe to replace it with a common subexpression. // It's also not safe if the instruction uses physical registers. bool CrossMBBPhysDef = false; - SmallSet PhysRefs; + SmallSet PhysRefs; PhysDefVector PhysDefs; bool PhysUseDef = false; if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -42,6 +42,7 @@ #include "llvm/IR/DebugLoc.h" #include "llvm/InitializePasses.h" #include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCRegister.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Pass.h" #include "llvm/Support/Casting.h" @@ -145,7 +146,7 @@ } // Track 'estimated' register pressure. - SmallSet RegSeen; + SmallSet RegSeen; SmallVector RegPressure; // Register pressure "limit" per register pressure set. If the pressure @@ -212,7 +213,7 @@ BitVector &PhysRegClobbers, SmallSet &StoredFIs, SmallVectorImpl &Candidates); - void AddToLiveIns(unsigned Reg); + void AddToLiveIns(MCRegister Reg); bool IsLICMCandidate(MachineInstr &I); @@ -221,7 +222,7 @@ bool HasLoopPHIUse(const MachineInstr *MI) const; bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, - unsigned Reg) const; + Register Reg) const; bool IsCheapInstruction(MachineInstr &MI) const; @@ -606,7 +607,7 @@ /// Add register 'Reg' to the livein sets of BBs in the current loop, and make /// sure it is not killed by any instructions in the loop. -void MachineLICMBase::AddToLiveIns(unsigned Reg) { +void MachineLICMBase::AddToLiveIns(MCRegister Reg) { for (MachineBasicBlock *BB : CurLoop->getBlocks()) { if (!BB->isLiveIn(Reg)) BB->addLiveIn(Reg); @@ -978,7 +979,7 @@ Reg = TRI->lookThruCopyLike(MO.getReg(), MRI); if (Register::isVirtualRegister(Reg)) return false; - if (!TRI->isCallerPreservedPhysReg(Reg, *MI.getMF())) + if (!TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *MI.getMF())) return false; else FoundCallerPresReg = true; @@ -1008,7 +1009,7 @@ if (Register::isVirtualRegister(CopySrcReg)) return false; - if (!TRI->isCallerPreservedPhysReg(CopySrcReg, *MF)) + if (!TRI->isCallerPreservedPhysReg(CopySrcReg.asMCReg(), *MF)) return false; Register CopyDstReg = MI.getOperand(0).getReg(); @@ -1071,7 +1072,7 @@ // However, if the physreg is known to always be caller saved/restored // then this use is safe to hoist. if (!MRI->isConstantPhysReg(Reg) && - !(TRI->isCallerPreservedPhysReg(Reg, *I.getMF()))) + !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF()))) return false; // Otherwise it's safe to move. continue; @@ -1138,9 +1139,8 @@ /// Compute operand latency between a def of 'Reg' and an use in the current /// loop, return true if the target considered it high. -bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, - unsigned DefIdx, - unsigned Reg) const { +bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, + Register Reg) const { if (MRI->use_nodbg_empty(Reg)) return false; diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -660,7 +660,7 @@ bool IsRootReserved = true; for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); Super.isValid(); ++Super) { - unsigned Reg = *Super; + MCRegister Reg = *Super; if (!isReserved(Reg)) { IsRootReserved = false; break;