diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -53,7 +53,7 @@
 }
 
 class DS_Real <DS_Pseudo ds> :
-  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
+  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # ds.AsmOperands, []>,
   Enc64 {
 
   let isPseudo = 0;
@@ -87,7 +87,7 @@
 : DS_Pseudo<opName,
   (outs),
   (ins rc:$data0, offset:$offset, gds:$gds),
-  "$data0$offset$gds"> {
+  " $data0$offset$gds"> {
 
   let has_addr = 0;
   let has_data1 = 0;
@@ -98,7 +98,7 @@
 : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
-  "$addr, $data0$offset$gds"> {
+  " $addr, $data0$offset$gds"> {
 
   let has_data1 = 0;
   let has_vdst = 0;
@@ -118,7 +118,7 @@
 : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
-  "$addr, $data0, $data1$offset$gds"> {
+  " $addr, $data0, $data1$offset$gds"> {
 
   let has_vdst = 0;
 }
@@ -138,7 +138,7 @@
   (outs),
   (ins VGPR_32:$addr, rc:$data0, rc:$data1,
        offset0:$offset0, offset1:$offset1, gds:$gds),
-  "$addr, $data0, $data1$offset0$offset1$gds"> {
+  " $addr, $data0, $data1$offset0$offset1$gds"> {
 
   let has_vdst = 0;
   let has_offset = 0;
@@ -157,7 +157,7 @@
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
-  "$vdst, $addr, $data0$offset$gds"> {
+  " $vdst, $addr, $data0$offset$gds"> {
 
   let hasPostISelHook = 1;
   let has_data1 = 0;
@@ -181,7 +181,7 @@
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
-  "$vdst, $addr, $data0, $data1$offset$gds"> {
+  " $vdst, $addr, $data0, $data1$offset$gds"> {
 
   let hasPostISelHook = 1;
 }
@@ -205,7 +205,7 @@
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
-  "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
+  " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
 
   let has_offset = 0;
   let AsmMatchConverter = "cvtDSOffset01";
@@ -230,7 +230,7 @@
   !if(HasTiedOutput,
     (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
     (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
-  "$vdst, $addr$offset$gds"> {
+  " $vdst, $addr$offset$gds"> {
   let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
   let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
   let has_data0 = 0;
@@ -252,7 +252,7 @@
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
-  "$vdst, $addr$offset0$offset1$gds"> {
+  " $vdst, $addr$offset0$offset1$gds"> {
 
   let has_offset = 0;
   let has_data0 = 0;
@@ -271,7 +271,7 @@
 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins VGPR_32:$addr, offset:$offset),
-  "$vdst, $addr$offset gds"> {
+  " $vdst, $addr$offset gds"> {
 
   let has_data0 = 0;
   let has_data1 = 0;
@@ -283,7 +283,7 @@
 class DS_0A_RET <string opName> : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins offset:$offset, gds:$gds),
-  "$vdst$offset$gds"> {
+  " $vdst$offset$gds"> {
 
   let mayLoad = 1;
   let mayStore = 1;
@@ -296,7 +296,7 @@
 class DS_1A <string opName> : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, offset:$offset, gds:$gds),
-  "$addr$offset$gds"> {
+  " $addr$offset$gds"> {
 
   let mayLoad = 1;
   let mayStore = 1;
@@ -336,7 +336,7 @@
 
 class DS_GWS_1D <string opName>
 : DS_GWS<opName,
-  (ins VGPR_32:$data0, offset:$offset), "$data0$offset gds"> {
+  (ins VGPR_32:$data0, offset:$offset), " $data0$offset gds"> {
 
   let has_gws_data0 = 1;
   let hasSideEffects = 1;
@@ -364,7 +364,7 @@
 : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
-  "$vdst, $addr, $data0$offset",
+  " $vdst, $addr, $data0$offset",
   [(set i32:$vdst,
    (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
 
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -136,7 +136,7 @@
                                     raw_ostream &O) {
   uint16_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm != 0) {
-    O << ((OpNo == 0)? "offset:" : " offset:");
+    O << " offset:";
     printU16ImmDecOperand(MI, OpNo, O);
   }
 }
@@ -146,7 +146,7 @@
                                         raw_ostream &O) {
   uint16_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm != 0) {
-    O << ((OpNo == 0)? "offset:" : " offset:");
+    O << " offset:";
 
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     bool IsFlatSeg = !(Desc.TSFlags & SIInstrFlags::IsNonFlatSeg);
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -3623,7 +3623,7 @@
 # GFX10: ds_gws_sema_br v255 offset:65535 gds    ; encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
 0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00
 
-# GFX10: ds_gws_sema_p  gds                      ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_p gds                       ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
 0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_p offset:4660 gds           ; encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00]
@@ -3632,7 +3632,7 @@
 # GFX10: ds_gws_sema_p offset:65535 gds          ; encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
 0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00
 
-# GFX10: ds_gws_sema_release_all  gds            ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_release_all gds             ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
 0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_release_all offset:4660 gds ; encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00]
@@ -3641,7 +3641,7 @@
 # GFX10: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
 0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00
 
-# GFX10: ds_gws_sema_v  gds                      ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_v gds                       ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
 0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_v offset:4660 gds           ; encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
@@ -2277,7 +2277,7 @@
 # CHECK: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_release_all  gds            ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_release_all gds             ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_release_all offset:4 gds    ; encoding: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
@@ -2298,7 +2298,7 @@
 # CHECK: ds_gws_sema_v offset:65535 gds          ; encoding: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_v  gds                      ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_v gds                       ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_v offset:4 gds              ; encoding: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
@@ -2319,7 +2319,7 @@
 # CHECK: ds_gws_sema_p offset:65535 gds          ; encoding: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_p  gds                      ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_p gds                       ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_p offset:4 gds              ; encoding: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -2421,7 +2421,7 @@
 # CHECK: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_release_all  gds            ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_release_all gds             ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_release_all offset:4 gds    ; encoding: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
@@ -2442,7 +2442,7 @@
 # CHECK: ds_gws_sema_v offset:65535 gds          ; encoding: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_v  gds                      ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_v gds                       ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_v offset:4 gds              ; encoding: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
@@ -2463,7 +2463,7 @@
 # CHECK: ds_gws_sema_p offset:65535 gds          ; encoding: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_p  gds                      ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_p gds                       ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_p offset:4 gds              ; encoding: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]