diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -330,7 +330,7 @@ class DS_GWS_0D : DS_GWS { + (ins offset:$offset, gds:$gds), "${offset}gds"> { let hasSideEffects = 1; } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -138,6 +138,8 @@ if (Imm != 0) { O << ((OpNo == 0)? "offset:" : " offset:"); printU16ImmDecOperand(MI, OpNo, O); + if (OpNo == 0) + O << " "; } } diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt --- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt @@ -3623,7 +3623,7 @@ # GFX10: ds_gws_sema_br v255 offset:65535 gds ; encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00] 0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00 -# GFX10: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00] +# GFX10: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00] 0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00 # GFX10: ds_gws_sema_p offset:4660 gds ; encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00] @@ -3632,7 +3632,7 @@ # GFX10: ds_gws_sema_p offset:65535 gds ; encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00] 0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00 -# GFX10: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00] +# GFX10: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00] 0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00 # GFX10: ds_gws_sema_release_all offset:4660 gds ; encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00] @@ -3641,7 +3641,7 @@ # GFX10: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00] 0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00 -# GFX10: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00] +# GFX10: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00] 0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00 # GFX10: ds_gws_sema_v offset:4660 gds ; encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]