diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -632,7 +632,7 @@ /// Get an iterator over the pressure sets affected by the given physical or /// virtual register. If RegUnit is physical, it must be a register unit (from /// MCRegUnitIterator). - PSetIterator getPressureSets(unsigned RegUnit) const; + PSetIterator getPressureSets(Register RegUnit) const; //===--------------------------------------------------------------------===// // Virtual Register Info @@ -1187,14 +1187,13 @@ public: PSetIterator() = default; - PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { + PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); - if (Register::isVirtualRegister(RegUnit)) { + if (RegUnit.isVirtual()) { const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); PSet = TRI->getRegClassPressureSets(RC); Weight = TRI->getRegClassWeight(RC).RegWeight; - } - else { + } else { PSet = TRI->getRegUnitPressureSets(RegUnit); Weight = TRI->getRegUnitWeight(RegUnit); } @@ -1216,8 +1215,8 @@ } }; -inline PSetIterator MachineRegisterInfo:: -getPressureSets(unsigned RegUnit) const { +inline PSetIterator +MachineRegisterInfo::getPressureSets(Register RegUnit) const { return PSetIterator(RegUnit, this); } diff --git a/llvm/include/llvm/CodeGen/RegisterPressure.h b/llvm/include/llvm/CodeGen/RegisterPressure.h --- a/llvm/include/llvm/CodeGen/RegisterPressure.h +++ b/llvm/include/llvm/CodeGen/RegisterPressure.h @@ -37,10 +37,10 @@ class RegisterClassInfo; struct RegisterMaskPair { - unsigned RegUnit; ///< Virtual register or register unit. + Register RegUnit; ///< Virtual register or register unit. LaneBitmask LaneMask; - RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) + RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) : RegUnit(RegUnit), LaneMask(LaneMask) {} }; @@ -157,7 +157,7 @@ const_iterator begin() const { return &PressureChanges[0]; } const_iterator end() const { return &PressureChanges[MaxPSets]; } - void addPressureChange(unsigned RegUnit, bool IsDec, + void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI); void dump(const TargetRegisterInfo &TRI) const; @@ -275,24 +275,24 @@ RegSet Regs; unsigned NumRegUnits; - unsigned getSparseIndexFromReg(unsigned Reg) const { - if (Register::isVirtualRegister(Reg)) + unsigned getSparseIndexFromReg(Register Reg) const { + if (Reg.isVirtual()) return Register::virtReg2Index(Reg) + NumRegUnits; assert(Reg < NumRegUnits); return Reg; } - unsigned getRegFromSparseIndex(unsigned SparseIndex) const { + Register getRegFromSparseIndex(unsigned SparseIndex) const { if (SparseIndex >= NumRegUnits) - return Register::index2VirtReg(SparseIndex-NumRegUnits); - return SparseIndex; + return Register::index2VirtReg(SparseIndex - NumRegUnits); + return Register(SparseIndex); } public: void clear(); void init(const MachineRegisterInfo &MRI); - LaneBitmask contains(unsigned Reg) const { + LaneBitmask contains(Register Reg) const { unsigned SparseIndex = getSparseIndexFromReg(Reg); RegSet::const_iterator I = Regs.find(SparseIndex); if (I == Regs.end()) @@ -332,7 +332,7 @@ template void appendTo(ContainerT &To) const { for (const IndexMaskPair &P : Regs) { - unsigned Reg = getRegFromSparseIndex(P.Index); + Register Reg = getRegFromSparseIndex(P.Index); if (P.LaneMask.any()) To.push_back(RegisterMaskPair(Reg, P.LaneMask)); } @@ -390,7 +390,7 @@ LiveRegSet LiveRegs; /// Set of vreg defs that start a live range. - SparseSet UntiedDefs; + SparseSet UntiedDefs; /// Live-through pressure. std::vector LiveThruPressure; @@ -532,7 +532,7 @@ return getDownwardPressure(MI, PressureResult, MaxPressureResult); } - bool hasUntiedDef(unsigned VirtReg) const { + bool hasUntiedDef(Register VirtReg) const { return UntiedDefs.count(VirtReg); } @@ -548,9 +548,9 @@ /// after the current position. SlotIndex getCurrSlot() const; - void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask, + void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask); - void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask, + void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask); void bumpDeadDefs(ArrayRef DeadDefs); @@ -561,9 +561,9 @@ void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl &LiveInOrOut); - LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const; - LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const; - LaneBitmask getLiveThroughAt(unsigned RegUnit, SlotIndex Pos) const; + LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const; + LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const; + LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const; }; void dumpRegSetPressure(ArrayRef SetPressure, diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -87,22 +87,21 @@ /// Return true if the specified register is included in this register class. /// This does not include virtual registers. - bool contains(unsigned Reg) const { + bool contains(Register Reg) const { /// FIXME: Historically this function has returned false when given vregs /// but it should probably only receive physical registers - if (!Register::isPhysicalRegister(Reg)) + if (!Reg.isPhysical()) return false; - return MC->contains(Reg); + return MC->contains(Reg.asMCReg()); } /// Return true if both registers are in this class. - bool contains(unsigned Reg1, unsigned Reg2) const { + bool contains(Register Reg1, Register Reg2) const { /// FIXME: Historically this function has returned false when given a vregs /// but it should probably only receive physical registers - if (!Register::isPhysicalRegister(Reg1) || - !Register::isPhysicalRegister(Reg2)) + if (!Reg1.isPhysical() || !Reg2.isPhysical()) return false; - return MC->contains(Reg1, Reg2); + return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); } /// Return the cost of copying a value between two registers in this class. @@ -401,9 +400,9 @@ } /// Returns true if Reg contains RegUnit. - bool hasRegUnit(MCRegister Reg, unsigned RegUnit) const { + bool hasRegUnit(MCRegister Reg, Register RegUnit) const { for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) - if (*Units == RegUnit) + if (Register(*Units) == RegUnit) return true; return false; } @@ -1183,8 +1182,8 @@ // This is useful when building IndexedMaps keyed on virtual registers struct VirtReg2IndexFunctor { - using argument_type = unsigned; - unsigned operator()(unsigned Reg) const { + using argument_type = Register; + unsigned operator()(Register Reg) const { return Register::virtReg2Index(Reg); } }; diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp --- a/llvm/lib/CodeGen/RegisterPressure.cpp +++ b/llvm/lib/CodeGen/RegisterPressure.cpp @@ -62,7 +62,7 @@ /// Decrease pressure for each pressure set provided by TargetRegisterInfo. static void decreaseSetPressure(std::vector &CurrSetPressure, - const MachineRegisterInfo &MRI, unsigned Reg, + const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask) { //assert((NewMask & !PrevMask) == 0 && "Must not add bits"); if (NewMask.any() || PrevMask.none()) @@ -152,7 +152,7 @@ #endif -void RegPressureTracker::increaseRegPressure(unsigned RegUnit, +void RegPressureTracker::increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask) { if (PreviousMask.any() || NewMask.none()) @@ -167,7 +167,7 @@ } } -void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, +void RegPressureTracker::decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask) { decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); @@ -418,11 +418,12 @@ } } -static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, - const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit, - SlotIndex Pos, LaneBitmask SafeDefault, - bool(*Property)(const LiveRange &LR, SlotIndex Pos)) { - if (Register::isVirtualRegister(RegUnit)) { +static LaneBitmask +getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, + bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, + LaneBitmask SafeDefault, + bool (*Property)(const LiveRange &LR, SlotIndex Pos)) { + if (RegUnit.isVirtual()) { const LiveInterval &LI = LIS.getInterval(RegUnit); LaneBitmask Result; if (TrackLaneMasks && LI.hasSubRanges()) { @@ -517,12 +518,13 @@ } } - void pushReg(unsigned Reg, + void pushReg(Register Reg, SmallVectorImpl &RegUnits) const { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneBitmask::getAll())); } else if (MRI.isAllocatable(Reg)) { - for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) + for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid(); + ++Units) addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll())); } } @@ -549,15 +551,16 @@ } } - void pushRegLanes(unsigned Reg, unsigned SubRegIdx, + void pushRegLanes(Register Reg, unsigned SubRegIdx, SmallVectorImpl &RegUnits) const { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { LaneBitmask LaneMask = SubRegIdx != 0 ? TRI.getSubRegIndexLaneMask(SubRegIdx) : MRI.getMaxLaneMaskForVReg(Reg); addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask)); } else if (MRI.isAllocatable(Reg)) { - for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) + for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid(); + ++Units) addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll())); } } @@ -667,7 +670,7 @@ } /// Add a change in pressure to the pressure diff of a given instruction. -void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec, +void PressureDiff::addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI) { PSetIterator PSetI = MRI->getPressureSets(RegUnit); int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight(); @@ -1240,7 +1243,7 @@ return LastUseMask; } -LaneBitmask RegPressureTracker::getLiveLanesAt(unsigned RegUnit, +LaneBitmask RegPressureTracker::getLiveLanesAt(Register RegUnit, SlotIndex Pos) const { assert(RequireIntervals); return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos, @@ -1250,7 +1253,7 @@ }); } -LaneBitmask RegPressureTracker::getLastUsedLanes(unsigned RegUnit, +LaneBitmask RegPressureTracker::getLastUsedLanes(Register RegUnit, SlotIndex Pos) const { assert(RequireIntervals); return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, @@ -1261,7 +1264,7 @@ }); } -LaneBitmask RegPressureTracker::getLiveThroughAt(unsigned RegUnit, +LaneBitmask RegPressureTracker::getLiveThroughAt(Register RegUnit, SlotIndex Pos) const { assert(RequireIntervals); return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,