diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -9279,9 +9279,9 @@ ((Subtarget.hasVSX() && ElementSize == 64) || (Subtarget.hasP9Vector() && ElementSize == 32))) { SDValue Ops[] = { - LD->getChain(), // Chain - LD->getBasePtr(), // Ptr - DAG.getValueType(Op.getValueType()) // VT + LD->getChain(), // Chain + LD->getBasePtr(), // Ptr + DAG.getValueType(Op.getValueType()) // VT }; SDValue LdSplt = DAG.getMemIntrinsicNode( PPCISD::LD_SPLAT, dl, DAG.getVTList(Op.getValueType(), MVT::Other), @@ -9339,8 +9339,8 @@ dl); // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. - int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> - (32-SplatBitSize)); + int32_t SextVal = + (int32_t(SplatBits << (32 - SplatBitSize)) >> (32 - SplatBitSize)); if (SextVal >= -16 && SextVal <= 15) return getCanonicalConstSplat(SextVal, SplatSize, Op.getValueType(), DAG, dl); @@ -9359,8 +9359,8 @@ // we convert to a pseudo that will be expanded later into one of // the above forms. SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32); - EVT VT = (SplatSize == 1 ? MVT::v16i8 : - (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); + EVT VT = (SplatSize == 1 ? MVT::v16i8 + : (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32); SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); if (VT == Op.getValueType()) @@ -9372,13 +9372,13 @@ // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important // for fneg/fabs. - if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { + if (SplatSize == 4 && SplatBits == (0x7FFFFFFF & ~SplatUndef)) { // Make -1 and vspltisw -1: SDValue OnesV = getCanonicalConstSplat(-1, 4, MVT::v4i32, DAG, dl); // Make the VSLW intrinsic, computing 0x8000_0000. - SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, - OnesV, DAG, dl); + SDValue Res = + BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, OnesV, DAG, dl); // xor by OnesV to invert it. Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); @@ -9387,9 +9387,8 @@ // Check to see if this is a wide variety of vsplti*, binop self cases. static const signed char SplatCsts[] = { - -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, - -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 - }; + -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, -8, 8, + -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16}; for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { // Indirect through the SplatCsts array so that we favor 'vsplti -1' for @@ -9398,50 +9397,50 @@ // Figure out what shift amount will be used by altivec if shifted by i in // this splat size. - unsigned TypeShiftAmt = i & (SplatBitSize-1); + unsigned TypeShiftAmt = i & (SplatBitSize - 1); // vsplti + shl self. if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, - Intrinsic::ppc_altivec_vslw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vslb, + Intrinsic::ppc_altivec_vslh, 0, + Intrinsic::ppc_altivec_vslw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } // vsplti + srl self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, - Intrinsic::ppc_altivec_vsrw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vsrb, + Intrinsic::ppc_altivec_vsrh, 0, + Intrinsic::ppc_altivec_vsrw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } // vsplti + sra self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, - Intrinsic::ppc_altivec_vsraw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vsrab, + Intrinsic::ppc_altivec_vsrah, 0, + Intrinsic::ppc_altivec_vsraw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } // vsplti + rol self. if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | - ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { + ((unsigned)i >> (SplatBitSize - TypeShiftAmt)))) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, - Intrinsic::ppc_altivec_vrlw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vrlb, + Intrinsic::ppc_altivec_vrlh, 0, + Intrinsic::ppc_altivec_vrlw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp --- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp @@ -413,6 +413,19 @@ LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: "); LLVM_DEBUG(MI.dump()); } + + // should prefer D-form if LXVX / STXVX uses a ZERO or ZERO8 + if (MI.getOpcode() == PPC::LXVX || MI.getOpcode() == PPC::STXVX) { + LLVM_DEBUG(dbgs() << "Replacing LXVX/STXVX REG, 0 with LXV/STX\n"); + // if it's Frame index we should not apply the transformation + if (!MI.getOperand(1).isFI() && + (MI.getOperand(1).getReg() == PPC::ZERO || + MI.getOperand(1).getReg() == PPC::ZERO8)) { + MI.setDesc(TII->get(MI.getOpcode() == PPC::STXVX ? PPC::STXV : PPC::LXV)); + + Changed = true; + } + } } // Eliminate conditional branch based on a constant CR bit by diff --git a/llvm/test/CodeGen/PowerPC/PR33671.ll b/llvm/test/CodeGen/PowerPC/PR33671.ll --- a/llvm/test/CodeGen/PowerPC/PR33671.ll +++ b/llvm/test/CodeGen/PowerPC/PR33671.ll @@ -27,6 +27,6 @@ ; CHECK-LABEL: test2 ; CHECK: addi 3, 3, 8 ; CHECK: addi [[REG:[0-9]+]], 4, 4 -; CHECK: lxvx [[LD:[0-9]+]], 0, 3 -; CHECK: stxvx [[LD]], 0, [[REG]] +; CHECK: lxv [[LD:[0-9]+]], 0(3) +; CHECK: stxv [[LD]], 0([[REG]]) } diff --git a/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll b/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll --- a/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll +++ b/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ -; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: | FileCheck %s --check-prefix=CHECK-P8 ; RUN: llc < %s -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ @@ -29,7 +29,7 @@ ; CHECK-P9: addis r4, r2, .LC0@toc@ha ; CHECK-P9: lxvwsx vs0, 0, r3 ; CHECK-P9: ld r4, .LC0@toc@l(r4) -; CHECK-P9: stxvx vs0, 0, r4 +; CHECK-P9: stxv vs0, 0(r4) ; CHECK-P9: lis r4, 1024 ; CHECK-P9: lfiwax f0, 0, r3 ; CHECK-P9: addis r3, r2, .LC1@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll --- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll @@ -858,14 +858,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsi: @@ -927,7 +927,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -1023,10 +1023,10 @@ ; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: addi r3, r3, -12 -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -1035,10 +1035,10 @@ ; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: addi r3, r3, -12 -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: blr ; @@ -1384,14 +1384,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoi: @@ -1449,7 +1449,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: xvcvspsxws v2, v2 ; P9BE-NEXT: blr @@ -1459,7 +1459,7 @@ ; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: xvcvspsxws v2, v2 ; P9LE-NEXT: blr @@ -1836,14 +1836,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoi: @@ -2376,14 +2376,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsui: @@ -2445,7 +2445,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -2541,10 +2541,10 @@ ; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: addi r3, r3, -12 -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -2553,10 +2553,10 @@ ; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: addi r3, r3, -12 -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: blr ; @@ -2902,14 +2902,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoui: @@ -2967,7 +2967,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: xvcvspuxws v2, v2 ; P9BE-NEXT: blr @@ -2977,7 +2977,7 @@ ; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: xvcvspuxws v2, v2 ; P9LE-NEXT: blr @@ -3355,14 +3355,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoui: @@ -3775,14 +3775,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst1ll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst1ll: @@ -3808,14 +3808,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst16kll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst16kll: @@ -3841,14 +3841,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst32kll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst32kll: @@ -3904,14 +3904,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsll: @@ -4238,14 +4238,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvftoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvftoll: @@ -4311,14 +4311,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoll: @@ -4600,14 +4600,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvdtoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvdtoll: @@ -4673,14 +4673,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoll: @@ -4963,14 +4963,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst1ull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst1ull: @@ -4996,14 +4996,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst16kull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst16kull: @@ -5029,14 +5029,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst32kull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst32kull: @@ -5092,14 +5092,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsull: @@ -5426,14 +5426,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvftoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvftoull: @@ -5499,14 +5499,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoull: @@ -5788,14 +5788,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvdtoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvdtoull: @@ -5861,14 +5861,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoull: diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll @@ -112,7 +112,7 @@ ret fp128 %2 ; CHECK-LABEL: insert_exp_qp ; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3 -; CHECK-DAG: lxvx [[VECREG:v[0-9]+]] +; CHECK-DAG: lxv [[VECREG:v[0-9]+]] ; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]] ; CHECK: blr } @@ -127,7 +127,7 @@ %1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0) ret i64 %1 ; CHECK-LABEL: extract_exp -; CHECK: lxvx [[VECIN:v[0-9]+]] +; CHECK: lxv [[VECIN:v[0-9]+]] ; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]] ; CHECK: mfvsrd r3, [[VECOUT]] ; CHECK: blr diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll --- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll +++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll @@ -383,7 +383,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vmrgow v2, v3, v2 ; CHECK-P9-NEXT: blr ; @@ -421,7 +421,7 @@ ; CHECK-P9-NEXT: lxsiwzx v2, r3, r4 ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: blr ; diff --git a/llvm/test/CodeGen/PowerPC/constant-pool.ll b/llvm/test/CodeGen/PowerPC/constant-pool.ll --- a/llvm/test/CodeGen/PowerPC/constant-pool.ll +++ b/llvm/test/CodeGen/PowerPC/constant-pool.ll @@ -64,7 +64,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret fp128 0xL00000000000000003C00FFFFC5D02B3A @@ -80,7 +80,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <16 x i8> @@ -96,7 +96,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <8 x i16> @@ -112,7 +112,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <4 x i32> @@ -128,7 +128,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <2 x i64> @@ -144,7 +144,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI8_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI8_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <1 x i128> @@ -160,7 +160,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <4 x float> @@ -176,7 +176,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <2 x double> @@ -320,15 +320,15 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_1@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_1@toc@l ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_2@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_2@toc@l ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: blr entry: @@ -408,10 +408,10 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI17_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI17_0@toc@l -; CHECK-P9-NEXT: lxvx vs0, 0, r3 +; CHECK-P9-NEXT: lxv vs0, 0(r3) ; CHECK-P9-NEXT: addis r3, r2, .LCPI17_1@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI17_1@toc@l -; CHECK-P9-NEXT: lxvx vs2, 0, r3 +; CHECK-P9-NEXT: lxv vs2, 0(r3) ; CHECK-P9-NEXT: xvadddp vs1, vs34, vs0 ; CHECK-P9-NEXT: xvadddp vs1, vs1, vs2 ; CHECK-P9-NEXT: xvadddp vs34, vs1, vs0 diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll --- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll +++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll @@ -599,7 +599,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1 ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: li r3, 16 ; CHECK-P9-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-NEXT: li r3, 20 diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -536,14 +536,14 @@ ; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r8, 72(r1) -; CHECK-NEXT: lxvx v2, 0, r4 +; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: std r9, 80(r1) ; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: addi r3, r1, 40 ; CHECK-NEXT: addi r4, r1, 72 -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: std r4, -8(r1) ; CHECK-NEXT: xsaddqp v2, v3, v2 ; CHECK-NEXT: lxv v3, 16(r3) @@ -560,14 +560,14 @@ ; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-NEXT: std r8, 88(r1) -; CHECK-BE-NEXT: lxvx v2, 0, r4 +; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-NEXT: bltlr cr0 ; CHECK-BE-NEXT: # %bb.1: # %if.end ; CHECK-BE-NEXT: addi r3, r1, 56 ; CHECK-BE-NEXT: addi r4, r1, 88 -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: std r4, -8(r1) ; CHECK-BE-NEXT: xsaddqp v2, v3, v2 ; CHECK-BE-NEXT: lxv v3, 16(r3) diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll --- a/llvm/test/CodeGen/PowerPC/f128-arith.ll +++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll @@ -166,8 +166,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r3, r3, 4 ; CHECK-NEXT: addi r4, r4, 8 -; CHECK-NEXT: lxvx vs0, 0, r3 -; CHECK-NEXT: stxvx vs0, 0, r4 +; CHECK-NEXT: lxv vs0, 0(r3) +; CHECK-NEXT: stxv vs0, 0(r4) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: testLdNSt: @@ -813,10 +813,10 @@ ; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: addis r3, r2, a@toc@ha ; CHECK-NEXT: addi r3, r3, a@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b@toc@ha ; CHECK-NEXT: addi r3, r3, b@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: bl fmodf128 ; CHECK-NEXT: nop ; CHECK-NEXT: addi r1, r1, 32 diff --git a/llvm/test/CodeGen/PowerPC/f128-compare.ll b/llvm/test/CodeGen/PowerPC/f128-compare.ll --- a/llvm/test/CodeGen/PowerPC/f128-compare.ll +++ b/llvm/test/CodeGen/PowerPC/f128-compare.ll @@ -15,10 +15,10 @@ ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iselgt r3, r4, r3 @@ -63,10 +63,10 @@ ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: isellt r3, r4, r3 @@ -108,10 +108,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: cror 4*cr5+lt, un, lt @@ -155,10 +155,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: cror 4*cr5+lt, un, gt @@ -205,10 +205,10 @@ ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iseleq r3, r4, r3 @@ -251,10 +251,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iselgt r3, 0, r3 @@ -300,10 +300,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: isellt r3, 0, r3 @@ -347,10 +347,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, lt, un @@ -394,10 +394,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, gt, un @@ -443,10 +443,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iseleq r3, 0, r3 @@ -490,10 +490,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: bgtlr cr0 ; CHECK-NEXT: # %bb.1: # %entry @@ -554,10 +554,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: # %bb.1: # %entry @@ -618,10 +618,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, un, lt ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 @@ -683,10 +683,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, un, gt ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 @@ -748,10 +748,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: beqlr cr0 ; CHECK-NEXT: # %bb.1: # %entry diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll --- a/llvm/test/CodeGen/PowerPC/f128-conv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll @@ -989,7 +989,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NEXT: ld r4, .LC6@toc@l(r4) -; CHECK-NEXT: lxvx v2, 0, r4 +; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: stxsd v2, 0(r3) ; CHECK-NEXT: blr @@ -1031,7 +1031,7 @@ ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: ld r5, .LC7@toc@l(r5) -; CHECK-NEXT: lxvx v2, 0, r5 +; CHECK-NEXT: lxv v2, 0(r5) ; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: blr @@ -1159,7 +1159,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NEXT: ld r4, .LC6@toc@l(r4) -; CHECK-NEXT: lxvx v2, 0, r4 +; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: xscvqpdpo v2, v2 ; CHECK-NEXT: xsrsp f0, v2 ; CHECK-NEXT: stfs f0, 0(r3) @@ -1329,7 +1329,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: dpConv2qp_02: @@ -1366,7 +1366,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: dpConv2qp_02b: @@ -1507,7 +1507,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: spConv2qp_02: @@ -1544,7 +1544,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: spConv2qp_02b: diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll --- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll +++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: loadConstant: @@ -32,7 +32,7 @@ ; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: blr ; @@ -608,7 +608,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld r3, 104(r1) ; CHECK-NEXT: stxv v2, 0(r9) -; CHECK-NEXT: stxvx v3, 0, r3 +; CHECK-NEXT: stxv v3, 0(r3) ; CHECK-NEXT: mtvsrwa v3, r10 ; CHECK-NEXT: lxv v2, 0(r9) ; CHECK-NEXT: xscvsdqp v3, v3 diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll --- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll @@ -413,7 +413,7 @@ ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: ld r5, .LC0@toc@l(r5) -; CHECK-NEXT: lxvx v2, 0, r5 +; CHECK-NEXT: lxv v2, 0(r5) ; CHECK-NEXT: xscvqpudz v2, v2 ; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll --- a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll +++ b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll @@ -42,8 +42,8 @@ ; CHECK-NEXT: ld 4, a15@toc@l(4) ; CHECK-NEXT: lfd 2, a2@toc@l(3) ; CHECK-NEXT: addis 3, 2, a3@toc@ha -; CHECK-NEXT: lxvx 34, 0, 6 -; CHECK-NEXT: lxvx 0, 0, 5 +; CHECK-NEXT: lxv 34, 0(6) +; CHECK-NEXT: lxv 0, 0(5) ; CHECK-NEXT: li 5, 152 ; CHECK-NEXT: lfd 3, a3@toc@l(3) ; CHECK-NEXT: addis 3, 2, a4@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll --- a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll +++ b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll @@ -96,7 +96,7 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x i32>, <4 x i32>* %vp1 @@ -134,7 +134,7 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x i32>, <4 x i32>* %vp1 @@ -172,7 +172,7 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <8 x i16>, <8 x i16>* %vp1 @@ -210,7 +210,7 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <8 x i16>, <8 x i16>* %vp1 @@ -346,7 +346,7 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x float>, <4 x float>* %vp1 @@ -384,7 +384,7 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x float>, <4 x float>* %vp1 @@ -475,7 +475,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -512,7 +512,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 +; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -549,7 +549,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -586,7 +586,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 +; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -745,7 +745,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -782,7 +782,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 +; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll --- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll +++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll @@ -55,7 +55,7 @@ ; CHECK-NEXT: stxv vs0, 48(r30) ; CHECK-NEXT: stxv vs1, 32(r30) ; CHECK-NEXT: stxv vs2, 16(r30) -; CHECK-NEXT: stxvx vs3, 0, r30 +; CHECK-NEXT: stxv vs3, 0(r30) ; CHECK-NEXT: addi r1, r1, 176 ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -105,7 +105,7 @@ ; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4 ; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: stxv vs1, 16(r30) -; CHECK-BE-NEXT: stxvx vs0, 0, r30 +; CHECK-BE-NEXT: stxv vs0, 0(r30) ; CHECK-BE-NEXT: stxv vs3, 48(r30) ; CHECK-BE-NEXT: stxv vs2, 32(r30) ; CHECK-BE-NEXT: ld r30, 240(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll --- a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll +++ b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll @@ -31,7 +31,7 @@ ; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs1, 32(r3) ; CHECK-NEXT: stxv vs2, 16(r3) -; CHECK-NEXT: stxvx vs3, 0, r3 +; CHECK-NEXT: stxv vs3, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: intrinsics1: @@ -54,7 +54,7 @@ ; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp4, v0, 0, 0 ; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: stxv vs1, 16(r3) -; CHECK-BE-NEXT: stxvx vs0, 0, r3 +; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/mul-const-vector.ll b/llvm/test/CodeGen/PowerPC/mul-const-vector.ll --- a/llvm/test/CodeGen/PowerPC/mul-const-vector.ll +++ b/llvm/test/CodeGen/PowerPC/mul-const-vector.ll @@ -277,7 +277,7 @@ ; CHECK-LABEL: test1_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]] @@ -289,7 +289,7 @@ ; CHECK-LABEL: test2_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]] @@ -302,7 +302,7 @@ ; CHECK-LABEL: test3_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 @@ -317,7 +317,7 @@ ; CHECK-LABEL: test4_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]], @@ -332,7 +332,7 @@ ; CHECK-LABEL: test5_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]] @@ -348,7 +348,7 @@ ; CHECK-LABEL: test6_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]] @@ -364,7 +364,7 @@ ; CHECK-LABEL: test7_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]] @@ -376,7 +376,7 @@ ; CHECK-LABEL: test8_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 diff --git a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll --- a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll +++ b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll @@ -24,7 +24,7 @@ ; CHECK-NOPCREL: # %bb.0: # %entry ; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NOPCREL-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-NOPCREL-NEXT: lxvx vs34, 0, r3 +; CHECK-NOPCREL-NEXT: lxv vs34, 0(r3) ; CHECK-NOPCREL-NEXT: blr entry: @@ -41,7 +41,7 @@ ; CHECK-NOPCREL: # %bb.0: # %entry ; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NOPCREL-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-NOPCREL-NEXT: lxvx vs34, 0, r3 +; CHECK-NOPCREL-NEXT: lxv vs34, 0(r3) ; CHECK-NOPCREL-NEXT: blr entry: @@ -58,7 +58,7 @@ ; CHECK-NOPCREL: # %bb.0: # %entry ; CHECK-NOPCREL-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NOPCREL-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-NOPCREL-NEXT: lxvx vs34, 0, r3 +; CHECK-NOPCREL-NEXT: lxv vs34, 0(r3) ; CHECK-NOPCREL-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll --- a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll +++ b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll @@ -63,7 +63,7 @@ define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) { ; CHECK-LABEL: test_vrlqnm: ; CHECK: # %bb.0: # %entry -; CHECK-BE: lxvx v5 +; CHECK-BE: lxv v5 ; CHECK-BE-NEXT: vperm v3, v3, v4, v5 ; CHECK-LE-NEXT: plxv v5 ; CHECK-LE-NEXT: vperm v3, v4, v3, v5 diff --git a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll --- a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll +++ b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll @@ -451,7 +451,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -464,7 +464,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -482,7 +482,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -505,7 +505,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -518,7 +518,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -536,7 +536,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -559,7 +559,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -577,7 +577,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1455,7 +1455,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1478,7 +1478,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1496,7 +1496,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1509,7 +1509,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1527,7 +1527,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1550,7 +1550,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1568,7 +1568,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1586,7 +1586,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1599,7 +1599,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1617,7 +1617,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1635,7 +1635,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1658,7 +1658,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1676,7 +1676,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1689,7 +1689,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1707,7 +1707,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1730,7 +1730,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll --- a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll +++ b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll @@ -42,11 +42,11 @@ ; CHECK-NEXT: pld r4, output8@got@pcrel(0), 1 ; CHECK-NEXT: .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8) ; CHECK-NEXT: lbz r3, 0(r3) +; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: blr ; In this test the stb r3, 0(r4) cannot be optimized because it ; uses the register r3 and that register is defined by lbz r3, 0(r3) ; which is defined between the pld and the stb. -; CHECK-NEXT: stb r3, 0(r4) -; CHECK-NEXT: blr entry: %0 = load i8, i8* @input8, align 1 store i8 %0, i8* @output8, align 1 @@ -61,11 +61,11 @@ ; CHECK-NEXT: pld r4, output16@got@pcrel(0), 1 ; CHECK-NEXT: .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8) ; CHECK-NEXT: lhz r3, 0(r3) +; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: blr ; In this test the sth r3, 0(r4) cannot be optimized because it ; uses the register r3 and that register is defined by lhz r3, 0(r3) ; which is defined between the pld and the sth. -; CHECK-NEXT: sth r3, 0(r4) -; CHECK-NEXT: blr entry: %0 = load i16, i16* @input16, align 2 store i16 %0, i16* @output16, align 2 @@ -110,9 +110,9 @@ ; CHECK-LABEL: ReadWrite128: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, input128@got@pcrel(0), 1 -; CHECK-NEXT: lxvx vs0, 0, r3 +; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: pld r3, output128@got@pcrel(0), 1 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %0 = load i128, i128* @input128, align 16 @@ -166,10 +166,10 @@ ; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1 ; CHECK-NEXT: li r4, 45 ; CHECK-NEXT: mtfprwz f1, r4 -; CHECK-NEXT: lxvx vs0, 0, r3 +; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: pld r3, outputVi32@got@pcrel(0), 1 ; CHECK-NEXT: xxinsertw vs0, vs1, 8 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16 @@ -182,9 +182,9 @@ ; CHECK-LABEL: ReadWriteVi64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, inputVi64@got@pcrel(0), 1 -; CHECK-NEXT: lxvx vs0, 0, r3 +; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: pld r3, outputVi64@got@pcrel(0), 1 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <2 x i64>, <2 x i64>* @inputVi64, align 16 diff --git a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll --- a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -63,7 +63,7 @@ ; FIXME: li [[R1:r[0-9]+]], 1 ; FIXME: li [[R2:r[0-9]+]], 0 ; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]] -; CHECK-P9: lxvx [[V1:v[0-9]+]] +; CHECK-P9: lxv [[V1:v[0-9]+]] ; CHECK-P9: vadduqm v2, v2, [[V1]] ; CHECK-P9: blr @@ -237,8 +237,8 @@ ; CHECK-LE: blr ; CHECK-P9-LABEL: @call_v1i128_increment_by_val -; CHECK-P9-DAG: lxvx v2 -; CHECK-P9-DAG: lxvx v3 +; CHECK-P9-DAG: lxv v2 +; CHECK-P9-DAG: lxv v3 ; CHECK-P9: bl v1i128_increment_by_val ; CHECK-P9: blr diff --git a/llvm/test/CodeGen/PowerPC/pr38087.ll b/llvm/test/CodeGen/PowerPC/pr38087.ll --- a/llvm/test/CodeGen/PowerPC/pr38087.ll +++ b/llvm/test/CodeGen/PowerPC/pr38087.ll @@ -17,7 +17,7 @@ ; CHECK-NEXT: xvcvsxwsp vs0, v3 ; CHECK-NEXT: xxspltw vs0, vs0, 2 ; CHECK-NEXT: xvmaddasp vs0, v2, v2 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %.size = load i32, i32* undef diff --git a/llvm/test/CodeGen/PowerPC/pr45628.ll b/llvm/test/CodeGen/PowerPC/pr45628.ll --- a/llvm/test/CodeGen/PowerPC/pr45628.ll +++ b/llvm/test/CodeGen/PowerPC/pr45628.ll @@ -270,13 +270,13 @@ ; P9-VSX: # %bb.0: # %entry ; P9-VSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha ; P9-VSX-NEXT: addi r3, r3, .LCPI8_0@toc@l -; P9-VSX-NEXT: lxvx v3, 0, r3 +; P9-VSX-NEXT: lxv v3, 0(r3) ; P9-VSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha ; P9-VSX-NEXT: addi r3, r3, .LCPI8_1@toc@l ; P9-VSX-NEXT: vslo v4, v2, v3 ; P9-VSX-NEXT: vspltb v3, v3, 15 ; P9-VSX-NEXT: vsl v3, v4, v3 -; P9-VSX-NEXT: lxvx v4, 0, r3 +; P9-VSX-NEXT: lxv v4, 0(r3) ; P9-VSX-NEXT: vsro v2, v2, v4 ; P9-VSX-NEXT: vspltb v4, v4, 15 ; P9-VSX-NEXT: vsr v2, v2, v4 diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll --- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll +++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll @@ -16,10 +16,10 @@ ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: li r6, 0 ; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l -; CHECK-NEXT: lxvx v2, 0, r5 +; CHECK-NEXT: lxv v2, 0(r5) ; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l -; CHECK-NEXT: lxvx v4, 0, r5 +; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: li r5, 4 ; CHECK-NEXT: vperm v0, v3, v5, v2 ; CHECK-NEXT: mtctr r5 @@ -72,11 +72,11 @@ ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: li r6, 0 ; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r5 +; P9BE-NEXT: lxv v2, 0(r5) ; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; P9BE-NEXT: xxlor v5, vs0, vs0 ; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l -; P9BE-NEXT: lxvx v4, 0, r5 +; P9BE-NEXT: lxv v4, 0(r5) ; P9BE-NEXT: li r5, 4 ; P9BE-NEXT: vperm v0, v3, v5, v2 ; P9BE-NEXT: mtctr r5 @@ -183,10 +183,10 @@ ; CHECK-NEXT: lxsd v1, 0(r4) ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l -; CHECK-NEXT: lxvx v0, 0, r3 +; CHECK-NEXT: lxv v0, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v5, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v0 @@ -209,12 +209,12 @@ ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l ; P9BE-NEXT: xxlor v2, vs0, vs0 ; P9BE-NEXT: lfd f0, 0(r4) -; P9BE-NEXT: lxvx v0, 0, r3 +; P9BE-NEXT: lxv v0, 0(r3) ; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vperm v5, v3, v2, v4 @@ -285,7 +285,7 @@ ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: lxsiwzx v5, r5, r3 ; CHECK-NEXT: vperm v2, v2, v3, v4 @@ -296,7 +296,7 @@ ; CHECK-NEXT: vslw v3, v3, v4 ; CHECK-NEXT: vsubuwm v2, v3, v2 ; CHECK-NEXT: xxswapd vs0, v2 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr ; ; P9BE-LABEL: test32: @@ -307,7 +307,7 @@ ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: xxsldwi v2, f0, f0, 1 ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: lfiwzx f0, r5, r3 ; P9BE-NEXT: vperm v2, v3, v2, v4 @@ -319,7 +319,7 @@ ; P9BE-NEXT: vslw v3, v3, v4 ; P9BE-NEXT: vsubuwm v2, v3, v2 ; P9BE-NEXT: xxswapd vs0, v2 -; P9BE-NEXT: stxvx vs0, 0, r3 +; P9BE-NEXT: stxv vs0, 0(r3) ; P9BE-NEXT: blr entry: %idx.ext63 = sext i32 %i_pix2 to i64 @@ -363,7 +363,7 @@ ; CHECK-NEXT: vmrghh v2, v3, v2 ; CHECK-NEXT: vsplth v3, v3, 3 ; CHECK-NEXT: vmrglw v3, v4, v3 -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: xxspltw v3, v2, 2 @@ -391,7 +391,7 @@ ; P9BE-NEXT: vmrghh v2, v3, v2 ; P9BE-NEXT: vsplth v3, v3, 0 ; P9BE-NEXT: vmrghw v3, v3, v4 -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: xxspltw v3, v2, 1 @@ -452,7 +452,7 @@ ; CHECK-NEXT: vmrglw v2, v2, v4 ; CHECK-NEXT: vmrglh v3, v3, v4 ; CHECK-NEXT: vmrglw v3, v4, v3 -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: xxspltw v3, v2, 2 @@ -481,7 +481,7 @@ ; P9BE-NEXT: vmrghh v4, v4, v3 ; P9BE-NEXT: xxspltw v3, v3, 0 ; P9BE-NEXT: vmrghw v2, v4, v2 -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: xxspltw v3, v2, 1 diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -502,12 +502,12 @@ ; CHECK-P9-NEXT: xvrsqrtesp 0, 35 ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 +; CHECK-P9-NEXT: lxv 2, 0(3) ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_1@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_1@toc@l ; CHECK-P9-NEXT: xvmulsp 1, 35, 0 ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lxvx 1, 0, 3 +; CHECK-P9-NEXT: lxv 1, 0(3) ; CHECK-P9-NEXT: xvmulsp 0, 0, 1 ; CHECK-P9-NEXT: xvmulsp 0, 0, 2 ; CHECK-P9-NEXT: xvmulsp 34, 34, 0 @@ -984,12 +984,12 @@ ; CHECK-P9-NEXT: xvrsqrtesp 0, 34 ; CHECK-P9-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI24_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 +; CHECK-P9-NEXT: lxv 2, 0(3) ; CHECK-P9-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI24_1@toc@l ; CHECK-P9-NEXT: xvmulsp 1, 34, 0 ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lxvx 0, 0, 3 +; CHECK-P9-NEXT: lxv 0, 0(3) ; CHECK-P9-NEXT: xvmulsp 0, 1, 0 ; CHECK-P9-NEXT: xxlxor 1, 1, 1 ; CHECK-P9-NEXT: xvmulsp 0, 0, 2 @@ -1108,13 +1108,13 @@ ; CHECK-P9-NEXT: xvrsqrtedp 0, 34 ; CHECK-P9-NEXT: addis 3, 2, .LCPI26_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI26_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 +; CHECK-P9-NEXT: lxv 2, 0(3) ; CHECK-P9-NEXT: addis 3, 2, .LCPI26_1@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI26_1@toc@l ; CHECK-P9-NEXT: xvmuldp 1, 34, 0 ; CHECK-P9-NEXT: xxlor 3, 2, 2 ; CHECK-P9-NEXT: xvmaddadp 3, 1, 0 -; CHECK-P9-NEXT: lxvx 1, 0, 3 +; CHECK-P9-NEXT: lxv 1, 0(3) ; CHECK-P9-NEXT: xvmuldp 0, 0, 1 ; CHECK-P9-NEXT: xvmuldp 0, 0, 3 ; CHECK-P9-NEXT: xvmuldp 3, 34, 0 diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll --- a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll +++ b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll @@ -46,7 +46,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: ld r3, .LC0@toc@l(r3) -; CHECK-P9: lxvx vs0, 0, r3 +; CHECK-P9: lxv vs0, 0(r3) ; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: lfd f1, 0(r3) @@ -54,7 +54,7 @@ ; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: xxswapd vs1, f1 ; CHECK-P9: xxpermdi vs0, vs0, vs1, 1 -; CHECK-P9: stxvx vs0, 0, r3 +; CHECK-P9: stxv vs0, 0(r3) ; CHECK-P9: blr entry: %0 = load <2 x double>, <2 x double>* @x, align 16 @@ -91,7 +91,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: ld r3, .LC0@toc@l(r3) -; CHECK-P9: lxvx vs0, 0, r3 +; CHECK-P9: lxv vs0, 0(r3) ; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: lfd f1, 0(r3) @@ -99,7 +99,7 @@ ; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: xxswapd vs1, f1 ; CHECK-P9: xxmrgld vs0, vs1, vs0 -; CHECK-P9: stxvx vs0, 0, r3 +; CHECK-P9: stxv vs0, 0(r3) ; CHECK-P9: blr entry: %0 = load <2 x double>, <2 x double>* @x, align 16 diff --git a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll --- a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll +++ b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll @@ -57,8 +57,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: addi r4, r4, 4 -; CHECK-NEXT: lxvx vs0, 0, r3 -; CHECK-NEXT: stxvx vs0, 0, r4 +; CHECK-NEXT: lxv vs0, 0(r3) +; CHECK-NEXT: stxv vs0, 0(r4) ; CHECK-NEXT: blr entry: %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1 @@ -80,15 +80,16 @@ ; CHECK-NEXT: li r5, 3 ; CHECK-NEXT: mtctr r3 ; CHECK-NEXT: li r3, 0 -; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4. ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB4_1: # %for.body -; CHECK: ldu r6, 8(r4) +; CHECK-NEXT: # +; CHECK-NEXT: ldu r6, 8(r4) ; CHECK-NEXT: ldx r7, r4, r5 ; CHECK-NEXT: maddld r3, r7, r6, r3 ; CHECK-NEXT: bdnz .LBB4_1 ; CHECK-NEXT: # %bb.2: # %for.end ; CHECK-NEXT: blr +; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4. entry: br label %for.body diff --git a/llvm/test/CodeGen/PowerPC/vavg.ll b/llvm/test/CodeGen/PowerPC/vavg.ll --- a/llvm/test/CodeGen/PowerPC/vavg.ll +++ b/llvm/test/CodeGen/PowerPC/vavg.ll @@ -140,7 +140,7 @@ ; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx 35, 0, 3 +; CHECK-P9-NEXT: lxv 35, 0(3) ; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vspltish 3, 1 ; CHECK-P9-NEXT: vsrah 2, 2, 3 diff --git a/llvm/test/CodeGen/PowerPC/vec-itofp.ll b/llvm/test/CodeGen/PowerPC/vec-itofp.ll --- a/llvm/test/CodeGen/PowerPC/vec-itofp.ll +++ b/llvm/test/CodeGen/PowerPC/vec-itofp.ll @@ -53,24 +53,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -83,24 +83,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -141,12 +141,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -159,12 +159,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -197,7 +197,7 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v2 ; CHECK-P9-NEXT: stxv vs0, 0(r3) @@ -209,7 +209,7 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v2 ; CHECK-BE-NEXT: stxv vs0, 0(r3) @@ -275,27 +275,27 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -309,27 +309,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -377,13 +377,13 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -397,13 +397,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -441,7 +441,7 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp vs0, v2 @@ -453,7 +453,7 @@ ; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs0, v2 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll @@ -100,7 +100,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: blr @@ -139,12 +139,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 @@ -192,12 +192,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v4, 0, r4 +; CHECK-P9-NEXT: lxv v4, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v0 -; CHECK-P9-NEXT: lxvx v0, 0, r4 +; CHECK-P9-NEXT: lxv v0, 0(r4) ; CHECK-P9-NEXT: vperm v3, v5, v3, v0 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 @@ -217,12 +217,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v0 -; CHECK-BE-NEXT: lxvx v0, 0, r4 +; CHECK-BE-NEXT: lxv v0, 0(r4) ; CHECK-BE-NEXT: vperm v3, v5, v3, v0 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 @@ -377,7 +377,7 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vextsh2w v3, v3 @@ -454,7 +454,7 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: vperm v0, v5, v3, v4 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v3 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll @@ -27,7 +27,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: blr @@ -38,7 +38,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: blr @@ -76,12 +76,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -94,12 +94,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -154,24 +154,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -183,24 +183,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -278,24 +278,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v4, 0, r4 +; CHECK-P9-NEXT: lxv v4, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0 -; CHECK-P9-NEXT: lxvx v0, 0, r4 +; CHECK-P9-NEXT: lxv v0, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v1, v5, v3, v0 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v1 -; CHECK-P9-NEXT: lxvx v1, 0, r4 +; CHECK-P9-NEXT: lxv v1, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v6, v5, v3, v1 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v6 -; CHECK-P9-NEXT: lxvx v6, 0, r4 +; CHECK-P9-NEXT: lxv v6, 0(r4) ; CHECK-P9-NEXT: vperm v3, v5, v3, v6 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v3 @@ -321,24 +321,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0 -; CHECK-BE-NEXT: lxvx v0, 0, r4 +; CHECK-BE-NEXT: lxv v0, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v1, v5, v3, v0 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v1 -; CHECK-BE-NEXT: lxvx v1, 0, r4 +; CHECK-BE-NEXT: lxv v1, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v6, v5, v3, v1 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v6 -; CHECK-BE-NEXT: lxvx v6, 0, r4 +; CHECK-BE-NEXT: lxv v6, 0(r4) ; CHECK-BE-NEXT: vperm v3, v5, v3, v6 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v3 @@ -385,7 +385,7 @@ ; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2 @@ -396,7 +396,7 @@ ; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2 @@ -441,13 +441,13 @@ ; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -461,13 +461,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -533,27 +533,27 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -566,27 +566,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -682,20 +682,20 @@ ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r5 +; CHECK-P9-NEXT: lxv v3, 0(r5) ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-P9-NEXT: lxvx v5, 0, r5 +; CHECK-P9-NEXT: lxv v5, 0(r5) ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: vperm v4, v2, v2, v3 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vextsh2d v4, v4 -; CHECK-P9-NEXT: lxvx v0, 0, r5 +; CHECK-P9-NEXT: lxv v0, 0(r5) ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: xvcvsxddp vs0, v4 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l -; CHECK-P9-NEXT: lxvx v1, 0, r5 +; CHECK-P9-NEXT: lxv v1, 0(r5) ; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0 @@ -736,10 +736,10 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l -; CHECK-BE-NEXT: lxvx v2, 0, r5 +; CHECK-BE-NEXT: lxv v2, 0(r5) ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r5 +; CHECK-BE-NEXT: lxv v3, 0(r5) ; CHECK-BE-NEXT: vperm v0, v5, v4, v2 ; CHECK-BE-NEXT: vperm v2, v5, v1, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -751,7 +751,7 @@ ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2 -; CHECK-BE-NEXT: lxvx v2, 0, r4 +; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: xvcvsxddp vs1, v0 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l @@ -764,7 +764,7 @@ ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: xvcvsxddp vs6, v2 ; CHECK-BE-NEXT: vperm v4, v4, v4, v3 ; CHECK-BE-NEXT: vperm v2, v1, v1, v3 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll @@ -95,7 +95,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: blr @@ -106,7 +106,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: blr @@ -142,12 +142,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 @@ -160,12 +160,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 @@ -216,24 +216,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 @@ -245,24 +245,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 @@ -362,7 +362,7 @@ ; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2 @@ -373,7 +373,7 @@ ; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2 @@ -414,13 +414,13 @@ ; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2w v2, v2 @@ -434,13 +434,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2w v2, v2 @@ -500,27 +500,27 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2w v2, v2 @@ -533,27 +533,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsb2w v2, v2 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll @@ -27,7 +27,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: blr @@ -38,7 +38,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: blr @@ -76,12 +76,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -94,12 +94,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -156,24 +156,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -186,24 +186,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -290,48 +290,48 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: xvcvuxddp vs4, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: xvcvuxddp vs5, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: xvcvuxddp vs6, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: xvcvuxddp vs7, v2 @@ -343,48 +343,48 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: xvcvuxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: xvcvuxddp vs5, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: xvcvuxddp vs6, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: xvcvuxddp vs7, v2 @@ -418,7 +418,7 @@ ; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2 @@ -429,7 +429,7 @@ ; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2 @@ -474,13 +474,13 @@ ; CHECK-P9-NEXT: mtvsrws v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -494,13 +494,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -568,27 +568,27 @@ ; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -602,27 +602,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -728,55 +728,55 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs3, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -789,55 +789,55 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs2, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll --- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll @@ -47,10 +47,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI1_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI1_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI1_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -102,7 +102,7 @@ ; PC64LE9-NEXT: lfs 3, .LCPI2_3@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI2_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI2_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsdivsp 2, 2, 0 ; PC64LE9-NEXT: xsdivsp 0, 3, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -154,10 +154,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI3_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI3_2@toc@l ; PC64LE9-NEXT: xsdivdp 3, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI3_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI3_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvdivdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -195,14 +195,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI4_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI4_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI4_2@toc@l ; PC64LE9-NEXT: xvdivdp 35, 1, 0 -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -403,7 +403,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -675,10 +675,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI11_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI11_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -730,7 +730,7 @@ ; PC64LE9-NEXT: lfs 3, .LCPI12_3@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI12_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI12_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsmulsp 2, 1, 2 ; PC64LE9-NEXT: xsmulsp 1, 1, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -783,10 +783,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI13_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI13_2@toc@l ; PC64LE9-NEXT: xsmuldp 3, 0, 1 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI13_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI13_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmuldp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -825,14 +825,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI14_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI14_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI14_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI14_2@toc@l ; PC64LE9-NEXT: xvmuldp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -891,10 +891,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI16_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -944,7 +944,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l ; PC64LE9-NEXT: xsaddsp 1, 0, 1 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsaddsp 2, 0, 2 ; PC64LE9-NEXT: xsaddsp 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -995,10 +995,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l ; PC64LE9-NEXT: xsadddp 3, 0, 1 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvadddp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1037,14 +1037,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI19_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI19_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI19_2@toc@l ; PC64LE9-NEXT: xvadddp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1103,10 +1103,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1156,7 +1156,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l ; PC64LE9-NEXT: xssubsp 1, 0, 1 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xssubsp 2, 0, 2 ; PC64LE9-NEXT: xssubsp 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -1207,10 +1207,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l ; PC64LE9-NEXT: xssubdp 3, 0, 1 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvsubdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1249,14 +1249,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l ; PC64LE9-NEXT: xvsubdp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1306,7 +1306,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI26_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: blr entry: @@ -1362,7 +1362,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: blr entry: @@ -1396,7 +1396,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI28_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI28_1@toc@l ; PC64LE9-NEXT: xssqrtdp 3, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsqrtdp 2, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1429,11 +1429,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI29_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI29_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI29_1@toc@l ; PC64LE9-NEXT: xvsqrtdp 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: blr entry: @@ -1632,7 +1632,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -2032,7 +2032,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -2403,7 +2403,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -2752,7 +2752,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -3101,7 +3101,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -3450,7 +3450,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -3799,7 +3799,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -4148,7 +4148,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -4497,7 +4497,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -4721,7 +4721,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI76_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvrdpic 34, 0 ; PC64LE9-NEXT: blr entry: @@ -4777,7 +4777,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: blr entry: @@ -4811,7 +4811,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI78_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI78_1@toc@l ; PC64LE9-NEXT: xsrdpic 3, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvrdpic 2, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -4844,11 +4844,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI79_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI79_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI79_1@toc@l ; PC64LE9-NEXT: xvrdpic 34, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvrdpic 35, 0 ; PC64LE9-NEXT: blr entry: @@ -5021,7 +5021,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -5266,10 +5266,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI86_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI86_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmaxdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5359,7 +5359,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -5426,10 +5426,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmaxdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -5473,17 +5473,17 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI89_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI89_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI89_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_2@toc@l ; PC64LE9-NEXT: xvmaxdp 34, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI89_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmaxdp 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5553,10 +5553,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI91_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI91_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmindp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5646,7 +5646,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -5713,10 +5713,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmindp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -5760,17 +5760,17 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI94_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI94_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI94_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_2@toc@l ; PC64LE9-NEXT: xvmindp 34, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI94_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmindp 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5883,7 +5883,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI97_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI97_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI97_3@toc@ha ; PC64LE9-NEXT: lfs 0, .LCPI97_3@toc@l(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 @@ -5912,7 +5912,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI98_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvspsxws 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6178,7 +6178,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI105_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI105_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI105_3@toc@ha ; PC64LE9-NEXT: lfd 0, .LCPI105_3@toc@l(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 @@ -6287,7 +6287,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI108_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI108_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6356,11 +6356,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI110_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI110_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI110_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI110_1@toc@l ; PC64LE9-NEXT: xvcvdpsxds 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6471,7 +6471,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI113_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI113_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI113_3@toc@ha ; PC64LE9-NEXT: lfs 0, .LCPI113_3@toc@l(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 @@ -6500,7 +6500,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI114_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI114_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvspuxws 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6765,7 +6765,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI121_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI121_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI121_3@toc@ha ; PC64LE9-NEXT: lfd 0, .LCPI121_3@toc@l(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 @@ -6874,7 +6874,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI124_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI124_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6943,11 +6943,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI126_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI126_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI126_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI126_1@toc@l ; PC64LE9-NEXT: xvcvdpuxds 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -7058,7 +7058,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI129_3@toc@ha ; PC64LE9-NEXT: lfd 0, .LCPI129_3@toc@l(3) ; PC64LE9-NEXT: xsrsp 0, 0 @@ -7268,10 +7268,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI136_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI136_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI136_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpip 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7310,7 +7310,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI137_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI137_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI137_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7343,7 +7343,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI138_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI138_1@toc@l ; PC64LE9-NEXT: xsrdpip 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI138_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI138_2@toc@l(3) ; PC64LE9-NEXT: xvrdpip 0, 0 @@ -7400,10 +7400,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI140_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI140_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI140_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpim 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7442,7 +7442,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI141_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI141_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI141_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7475,7 +7475,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI142_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI142_1@toc@l ; PC64LE9-NEXT: xsrdpim 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI142_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI142_2@toc@l(3) ; PC64LE9-NEXT: xvrdpim 0, 0 @@ -7531,10 +7531,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI144_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI144_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI144_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpi 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7573,7 +7573,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI145_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI145_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI145_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7608,7 +7608,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI146_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI146_1@toc@l ; PC64LE9-NEXT: xsrdpi 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI146_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI146_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI146_3@toc@ha @@ -7665,10 +7665,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI148_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI148_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI148_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpiz 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7707,7 +7707,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI149_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI149_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI149_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7740,7 +7740,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI150_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI150_1@toc@l ; PC64LE9-NEXT: xsrdpiz 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI150_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI150_2@toc@l(3) ; PC64LE9-NEXT: xvrdpiz 0, 0 @@ -7854,7 +7854,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI155_0@toc@l -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 2, 2, 3 ; PC64LE9-NEXT: vextsh2d 2, 2 ; PC64LE9-NEXT: xvcvsxddp 34, 34 @@ -8082,7 +8082,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: mtfprwa 0, 3 ; PC64LE9-NEXT: xscvsxdsp 0, 0 @@ -8163,7 +8163,7 @@ ; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -8438,7 +8438,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PC64LE9-NEXT: xxlxor 36, 36, 36 ; PC64LE9-NEXT: addi 3, 3, .LCPI173_0@toc@l -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: xvcvuxddp 34, 34 ; PC64LE9-NEXT: blr @@ -8665,7 +8665,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: xscvuxdsp 0, 0 @@ -8746,7 +8746,7 @@ ; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 diff --git a/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll b/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll --- a/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll +++ b/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll @@ -149,7 +149,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx 35, 0, 3 +; CHECK-P9-NEXT: lxv 35, 0(3) ; CHECK-P9-NEXT: vsld 2, 2, 3 ; CHECK-P9-NEXT: vsrad 2, 2, 3 ; CHECK-P9-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll --- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll +++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll @@ -12000,7 +12000,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI100_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI100_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12067,7 +12067,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI101_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI101_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12201,7 +12201,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI102_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI102_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12335,7 +12335,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI103_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI103_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12469,7 +12469,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI104_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI104_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12603,7 +12603,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI105_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI105_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12737,7 +12737,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI106_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI106_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12871,7 +12871,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI107_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI107_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13005,7 +13005,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI108_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI108_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13139,7 +13139,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI109_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI109_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13273,7 +13273,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI110_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI110_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13407,7 +13407,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI111_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI111_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13541,7 +13541,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI112_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI112_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13675,7 +13675,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI113_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI113_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13809,7 +13809,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI114_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI114_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13943,7 +13943,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI115_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI115_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14077,7 +14077,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI116_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI116_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14211,7 +14211,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI117_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI117_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14345,7 +14345,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI118_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI118_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14479,7 +14479,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI119_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI119_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14613,7 +14613,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI120_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI120_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14747,7 +14747,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI121_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI121_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14881,7 +14881,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI122_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI122_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15015,7 +15015,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI123_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI123_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15149,7 +15149,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI124_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI124_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15283,7 +15283,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI125_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI125_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15417,7 +15417,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI126_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI126_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15551,7 +15551,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI127_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI127_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15685,7 +15685,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI128_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI128_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15819,7 +15819,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI129_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15953,7 +15953,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI130_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI130_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16087,7 +16087,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI131_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI131_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16221,7 +16221,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI132_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI132_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16355,7 +16355,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI133_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI133_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16489,7 +16489,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI134_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI134_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16623,7 +16623,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI135_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI135_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16757,7 +16757,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI136_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16891,7 +16891,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI137_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI137_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17025,7 +17025,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI138_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI138_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17159,7 +17159,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI139_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI139_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17293,7 +17293,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI140_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17427,7 +17427,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI141_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI141_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17561,7 +17561,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI142_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI142_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17695,7 +17695,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI143_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI143_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17829,7 +17829,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI144_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17963,7 +17963,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI145_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI145_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18097,7 +18097,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI146_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI146_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18231,7 +18231,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI147_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI147_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18365,7 +18365,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI148_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18499,7 +18499,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI149_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI149_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18633,7 +18633,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI150_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI150_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18767,7 +18767,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI151_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI151_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18901,7 +18901,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI152_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI152_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19035,7 +19035,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI153_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI153_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19169,7 +19169,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI154_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI154_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19303,7 +19303,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI155_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19437,7 +19437,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI156_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI156_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19571,7 +19571,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI157_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI157_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19705,7 +19705,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI158_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI158_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19839,7 +19839,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI159_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI159_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19973,7 +19973,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI160_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI160_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20107,7 +20107,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI161_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI161_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20241,7 +20241,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI162_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI162_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20375,7 +20375,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI163_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI163_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20509,7 +20509,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI164_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI164_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20643,7 +20643,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI165_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI165_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20777,7 +20777,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI166_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI166_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20911,7 +20911,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI167_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI167_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21045,7 +21045,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI168_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI168_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21179,7 +21179,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI169_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI169_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21313,7 +21313,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI170_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI170_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21447,7 +21447,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI171_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI171_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21581,7 +21581,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI172_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI172_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21715,7 +21715,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI173_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21849,7 +21849,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI174_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI174_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21983,7 +21983,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI175_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI175_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22117,7 +22117,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI176_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI176_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22251,7 +22251,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI177_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI177_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22385,7 +22385,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI178_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI178_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22519,7 +22519,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI179_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI179_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22653,7 +22653,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI180_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI180_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22787,7 +22787,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI181_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI181_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22921,7 +22921,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI182_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI182_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23055,7 +23055,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI183_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI183_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23189,7 +23189,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI184_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI184_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23323,7 +23323,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI185_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI185_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23457,7 +23457,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI186_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI186_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23591,7 +23591,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI187_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI187_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23725,7 +23725,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI188_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI188_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23859,7 +23859,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI189_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI189_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23993,7 +23993,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI190_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI190_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24127,7 +24127,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI191_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI191_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24261,7 +24261,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI192_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI192_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24395,7 +24395,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI193_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI193_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24529,7 +24529,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI194_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI194_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24663,7 +24663,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI195_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI195_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24797,7 +24797,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI196_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI196_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24931,7 +24931,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI197_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI197_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25065,7 +25065,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI198_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI198_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25199,7 +25199,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI199_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI199_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25333,7 +25333,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI200_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI200_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25467,7 +25467,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI201_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI201_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25601,7 +25601,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI202_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI202_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25735,7 +25735,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI203_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI203_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25869,7 +25869,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI204_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI204_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26003,7 +26003,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI205_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI205_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26137,7 +26137,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI206_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI206_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26271,7 +26271,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI207_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI207_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26405,7 +26405,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI208_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI208_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26539,7 +26539,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI209_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI209_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26673,7 +26673,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI210_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI210_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26807,7 +26807,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI211_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI211_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26941,7 +26941,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI212_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI212_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27075,7 +27075,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI213_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI213_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27209,7 +27209,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI214_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI214_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27343,7 +27343,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI215_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI215_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27477,7 +27477,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI216_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI216_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27611,7 +27611,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI217_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI217_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27745,7 +27745,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI218_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI218_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27879,7 +27879,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI219_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI219_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28013,7 +28013,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI220_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI220_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28147,7 +28147,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI221_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI221_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28281,7 +28281,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI222_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI222_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28415,7 +28415,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI223_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI223_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) diff --git a/llvm/test/CodeGen/PowerPC/vsx-p9.ll b/llvm/test/CodeGen/PowerPC/vsx-p9.ll --- a/llvm/test/CodeGen/PowerPC/vsx-p9.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-p9.ll @@ -36,8 +36,8 @@ %1 = load <16 x i8>, <16 x i8>* @ucb, align 16 %add.i = add <16 x i8> %1, %0 tail call void (...) @sink(<16 x i8> %add.i) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddubm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -45,8 +45,8 @@ %3 = load <16 x i8>, <16 x i8>* @scb, align 16 %add.i22 = add <16 x i8> %3, %2 tail call void (...) @sink(<16 x i8> %add.i22) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddubm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -54,8 +54,8 @@ %5 = load <8 x i16>, <8 x i16>* @usb, align 16 %add.i21 = add <8 x i16> %5, %4 tail call void (...) @sink(<8 x i16> %add.i21) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduhm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -63,8 +63,8 @@ %7 = load <8 x i16>, <8 x i16>* @ssb, align 16 %add.i20 = add <8 x i16> %7, %6 tail call void (...) @sink(<8 x i16> %add.i20) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduhm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -72,8 +72,8 @@ %9 = load <4 x i32>, <4 x i32>* @uib, align 16 %add.i19 = add <4 x i32> %9, %8 tail call void (...) @sink(<4 x i32> %add.i19) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduwm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -81,8 +81,8 @@ %11 = load <4 x i32>, <4 x i32>* @sib, align 16 %add.i18 = add <4 x i32> %11, %10 tail call void (...) @sink(<4 x i32> %add.i18) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduwm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -90,8 +90,8 @@ %13 = load <2 x i64>, <2 x i64>* @ullb, align 16 %add.i17 = add <2 x i64> %13, %12 tail call void (...) @sink(<2 x i64> %add.i17) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddudm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -99,8 +99,8 @@ %15 = load <2 x i64>, <2 x i64>* @sllb, align 16 %add.i16 = add <2 x i64> %15, %14 tail call void (...) @sink(<2 x i64> %add.i16) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddudm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -108,8 +108,8 @@ %17 = load <1 x i128>, <1 x i128>* @uxb, align 16 %add.i15 = add <1 x i128> %17, %16 tail call void (...) @sink(<1 x i128> %add.i15) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduqm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -117,8 +117,8 @@ %19 = load <1 x i128>, <1 x i128>* @sxb, align 16 %add.i14 = add <1 x i128> %19, %18 tail call void (...) @sink(<1 x i128> %add.i14) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduqm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -126,8 +126,8 @@ %21 = load <4 x float>, <4 x float>* @vfb, align 16 %add.i13 = fadd <4 x float> %20, %21 tail call void (...) @sink(<4 x float> %add.i13) -; CHECK: lxvx 0, 0, 3 -; CHECK: lxvx 1, 0, 3 +; CHECK: lxv 0, 0(3) +; CHECK: lxv 1, 0(3) ; CHECK: xvaddsp 34, 0, 1 ; CHECK: stxv 34, ; CHECK: bl sink @@ -135,8 +135,8 @@ %23 = load <2 x double>, <2 x double>* @vdb, align 16 %add.i12 = fadd <2 x double> %22, %23 tail call void (...) @sink(<2 x double> %add.i12) -; CHECK: lxvx 0, 0, 3 -; CHECK: lxvx 1, 0, 3 +; CHECK: lxv 0, 0(3) +; CHECK: lxv 1, 0(3) ; CHECK: xvadddp 0, 0, 1 ; CHECK: stxv 0, ; CHECK: bl sink