Index: llvm/include/llvm/CodeGen/TargetFrameLowering.h =================================================================== --- llvm/include/llvm/CodeGen/TargetFrameLowering.h +++ llvm/include/llvm/CodeGen/TargetFrameLowering.h @@ -14,6 +14,7 @@ #define LLVM_CODEGEN_TARGETFRAMELOWERING_H #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/Support/TypeSize.h" #include namespace llvm { @@ -297,8 +298,8 @@ /// getFrameIndexReference - This method should return the base register /// and offset used to reference a frame index location. The offset is /// returned directly, and the base register is returned via FrameReg. - virtual int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const; + virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const; /// Same as \c getFrameIndexReference, except that the stack pointer (as /// opposed to the frame pointer) will be the preferred value for \p @@ -306,9 +307,10 @@ /// use offsets from RSP. If \p IgnoreSPUpdates is true, the returned /// offset is only guaranteed to be valid with respect to the value of SP at /// the end of the prologue. - virtual int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, - Register &FrameReg, - bool IgnoreSPUpdates) const { + virtual StackOffset + getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, + Register &FrameReg, + bool IgnoreSPUpdates) const { // Always safe to dispatch to getFrameIndexReference. return getFrameIndexReference(MF, FI, FrameReg); } @@ -316,8 +318,8 @@ /// getNonLocalFrameIndexReference - This method returns the offset used to /// reference a frame index location. The offset can be from either FP/BP/SP /// based on which base register is returned by llvm.localaddress. - virtual int getNonLocalFrameIndexReference(const MachineFunction &MF, - int FI) const { + virtual StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, + int FI) const { // By default, dispatch to getFrameIndexReference. Interested targets can // override this. Register FrameReg; Index: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp =================================================================== --- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -877,7 +877,7 @@ // The second operand is only an offset if it's an immediate. bool MemLoc = MI->isIndirectDebugValue(); - int64_t Offset = MemLoc ? MI->getOperand(1).getImm() : 0; + auto Offset = StackOffset::getFixed(MemLoc ? MI->getOperand(1).getImm() : 0); const DIExpression *Expr = MI->getDebugExpression(); if (Expr->getNumElements()) { OS << '['; @@ -941,7 +941,7 @@ } if (MemLoc) - OS << '+' << Offset << ']'; + OS << '+' << Offset.getFixed() << ']'; // NOTE: Want this comment at start of line, don't emit with AddComment. AP.OutStreamer->emitRawComment(OS.str()); Index: llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp =================================================================== --- llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp +++ llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp @@ -1181,12 +1181,15 @@ // Get the frame register used and the offset. Register FrameReg; - int FrameOffset = TFI->getFrameIndexReference(*Asm->MF, VI.Slot, FrameReg); + StackOffset FrameOffset = TFI->getFrameIndexReference(*Asm->MF, VI.Slot, FrameReg); uint16_t CVReg = TRI->getCodeViewRegNum(FrameReg); + assert(!FrameOffset.getScalable() && + "Frame offsets with a scalable component are not supported"); + // Calculate the label ranges. LocalVarDefRange DefRange = - createDefRangeMem(CVReg, FrameOffset + ExprOffset); + createDefRangeMem(CVReg, FrameOffset.getFixed() + ExprOffset); for (const InsnRange &Range : Scope->getRanges()) { const MCSymbol *Begin = getLabelBeforeInsn(Range.first); Index: llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp =================================================================== --- llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -730,10 +730,15 @@ Register FrameReg; const DIExpression *Expr = Fragment.Expr; const TargetFrameLowering *TFI = Asm->MF->getSubtarget().getFrameLowering(); - int Offset = TFI->getFrameIndexReference(*Asm->MF, Fragment.FI, FrameReg); + StackOffset Offset = + TFI->getFrameIndexReference(*Asm->MF, Fragment.FI, FrameReg); DwarfExpr.addFragmentOffset(Expr); + + assert(!Offset.getScalable() && + "Frame offsets with a scalable component are not supported"); + SmallVector Ops; - DIExpression::appendOffset(Ops, Offset); + DIExpression::appendOffset(Ops, Offset.getFixed()); // According to // https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf // cuda-gdb requires DW_AT_address_class for all variables to be able to Index: llvm/lib/CodeGen/AsmPrinter/WinException.cpp =================================================================== --- llvm/lib/CodeGen/AsmPrinter/WinException.cpp +++ llvm/lib/CodeGen/AsmPrinter/WinException.cpp @@ -343,22 +343,24 @@ const TargetFrameLowering &TFI = *Asm->MF->getSubtarget().getFrameLowering(); Register UnusedReg; if (Asm->MAI->usesWindowsCFI()) { - int Offset = + StackOffset Offset = TFI.getFrameIndexReferencePreferSP(*Asm->MF, FrameIndex, UnusedReg, /*IgnoreSPUpdates*/ true); assert(UnusedReg == Asm->MF->getSubtarget() .getTargetLowering() ->getStackPointerRegisterToSaveRestore()); - return Offset; + return Offset.getFixed(); } // For 32-bit, offsets should be relative to the end of the EH registration // node. For 64-bit, it's relative to SP at the end of the prologue. assert(FuncInfo.EHRegNodeEndOffset != INT_MAX); - int Offset = TFI.getFrameIndexReference(*Asm->MF, FrameIndex, UnusedReg); - Offset += FuncInfo.EHRegNodeEndOffset; - return Offset; + StackOffset Offset = TFI.getFrameIndexReference(*Asm->MF, FrameIndex, UnusedReg); + Offset += StackOffset::getFixed(FuncInfo.EHRegNodeEndOffset); + assert(!Offset.getScalable() && + "Frame offsets with a scalable component are not supported"); + return Offset.getFixed(); } namespace { @@ -955,7 +957,7 @@ int FI = FuncInfo.EHRegNodeFrameIndex; if (FI != INT_MAX) { const TargetFrameLowering *TFI = Asm->MF->getSubtarget().getFrameLowering(); - Offset = TFI->getNonLocalFrameIndexReference(*Asm->MF, FI); + Offset = TFI->getNonLocalFrameIndexReference(*Asm->MF, FI).getFixed(); } MCContext &Ctx = Asm->OutContext; @@ -1019,7 +1021,8 @@ Register UnusedReg; const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); int SSPIdx = MFI.getStackProtectorIndex(); - GSCookieOffset = TFI->getFrameIndexReference(*MF, SSPIdx, UnusedReg); + GSCookieOffset = + TFI->getFrameIndexReference(*MF, SSPIdx, UnusedReg).getFixed(); } // Retrieve the EH Guard slot. @@ -1029,7 +1032,8 @@ Register UnusedReg; const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); int EHGuardIdx = FuncInfo.EHGuardFrameIndex; - EHCookieOffset = TFI->getFrameIndexReference(*MF, EHGuardIdx, UnusedReg); + EHCookieOffset = + TFI->getFrameIndexReference(*MF, EHGuardIdx, UnusedReg).getFixed(); } AddComment("GSCookieOffset"); Index: llvm/lib/CodeGen/GCRootLowering.cpp =================================================================== --- llvm/lib/CodeGen/GCRootLowering.cpp +++ llvm/lib/CodeGen/GCRootLowering.cpp @@ -296,7 +296,10 @@ } else { Register FrameReg; // FIXME: surely GCRoot ought to store the // register that the offset is from? - RI->StackOffset = TFI->getFrameIndexReference(MF, RI->Num, FrameReg); + auto FrameOffset = TFI->getFrameIndexReference(MF, RI->Num, FrameReg); + assert(!FrameOffset.getScalable() && + "Frame offsets with a scalable component are not supported"); + RI->StackOffset = FrameOffset.getFixed(); ++RI; } } Index: llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp =================================================================== --- llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -1481,8 +1481,10 @@ int FI = cast(PVal)->getFrameIndex(); const MachineBasicBlock *MBB = MI.getParent(); Register Reg; - int Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg); - return {Reg, Offset}; + StackOffset Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg); + assert(!Offset.getScalable() && + "Frame offsets with a scalable component are not supported"); + return {Reg, Offset.getFixed()}; } /// End all previous ranges related to @MI and start a new range from @MI Index: llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp =================================================================== --- llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp +++ llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp @@ -983,8 +983,10 @@ int FI = cast(PVal)->getFrameIndex(); const MachineBasicBlock *MBB = MI.getParent(); Register Reg; - int Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg); - return {Reg, Offset}; + StackOffset Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg); + assert(!Offset.getScalable() && + "Frame offsets with a scalable component are not supported"); + return {Reg, Offset.getFixed()}; } /// Try to salvage the debug entry value if we encounter a new debug value Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp =================================================================== --- llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1209,8 +1209,10 @@ unsigned FrameIdx = MI.getOperand(0).getIndex(); unsigned Size = MF.getFrameInfo().getObjectSize(FrameIdx); - int64_t Offset = + StackOffset Offset = TFI->getFrameIndexReference(MF, FrameIdx, Reg); + assert(!Offset.getScalable() && + "Frame offsets with a scalable component are not supported"); MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/); MI.getOperand(0).setIsDebug(); @@ -1236,7 +1238,7 @@ // Make the DBG_VALUE direct. MI.getDebugOffset().ChangeToRegister(0, false); } - DIExpr = DIExpression::prepend(DIExpr, PrependFlags, Offset); + DIExpr = DIExpression::prepend(DIExpr, PrependFlags, Offset.getFixed()); MI.getDebugExpressionOp().setMetadata(DIExpr); continue; } @@ -1252,9 +1254,11 @@ "DBG_VALUE machine instruction"); Register Reg; MachineOperand &Offset = MI.getOperand(i + 1); - int refOffset = TFI->getFrameIndexReferencePreferSP( + StackOffset refOffset = TFI->getFrameIndexReferencePreferSP( MF, MI.getOperand(i).getIndex(), Reg, /*IgnoreSPUpdates*/ false); - Offset.setImm(Offset.getImm() + refOffset + SPAdj); + assert(!refOffset.getScalable() && + "Frame offsets with a scalable component are not supported"); + Offset.setImm(Offset.getImm() + refOffset.getFixed() + SPAdj); MI.getOperand(i).ChangeToRegister(Reg, false /*isDef*/); continue; } Index: llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp =================================================================== --- llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -41,9 +41,9 @@ /// frame of the specified index, along with the frame register used /// (in output arg FrameReg). This is the default implementation which /// is overridden for some targets. -int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); @@ -52,8 +52,9 @@ // something different. FrameReg = RI->getFrameRegister(MF); - return MFI.getObjectOffset(FI) + MFI.getStackSize() - - getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); + return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - + getOffsetOfLocalArea() + + MFI.getOffsetAdjustment()); } bool TargetFrameLowering::needsFrameIndexResolution( Index: llvm/lib/Target/AArch64/AArch64FrameLowering.h =================================================================== --- llvm/lib/Target/AArch64/AArch64FrameLowering.h +++ llvm/lib/Target/AArch64/AArch64FrameLowering.h @@ -41,8 +41,8 @@ bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const; @@ -94,11 +94,12 @@ unsigned getWinEHFuncletFrameSize(const MachineFunction &MF) const; - int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, - Register &FrameReg, - bool IgnoreSPUpdates) const override; - int getNonLocalFrameIndexReference(const MachineFunction &MF, - int FI) const override; + StackOffset + getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, + Register &FrameReg, + bool IgnoreSPUpdates) const override; + StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, + int FI) const override; int getSEHFrameIndexOffset(const MachineFunction &MF, int FI) const; bool isSupportedStackID(TargetStackID::Value ID) const override { Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1795,20 +1795,20 @@ /// debug info. It's the same as what we use for resolving the code-gen /// references for now. FIXME: This can go wrong when references are /// SP-relative and simple call frames aren't used. -int AArch64FrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +AArch64FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { return resolveFrameIndexReference( - MF, FI, FrameReg, - /*PreferFP=*/ - MF.getFunction().hasFnAttribute(Attribute::SanitizeHWAddress), - /*ForSimm=*/false) - .getFixed(); + MF, FI, FrameReg, + /*PreferFP=*/ + MF.getFunction().hasFnAttribute(Attribute::SanitizeHWAddress), + /*ForSimm=*/false); } -int AArch64FrameLowering::getNonLocalFrameIndexReference( - const MachineFunction &MF, int FI) const { - return getSEHFrameIndexOffset(MF, FI); +StackOffset +AArch64FrameLowering::getNonLocalFrameIndexReference(const MachineFunction &MF, + int FI) const { + return StackOffset::getFixed(getSEHFrameIndexOffset(MF, FI)); } static StackOffset getFPOffset(const MachineFunction &MF, @@ -1831,6 +1831,7 @@ return StackOffset::getFixed(ObjectOffset + (int64_t)MFI.getStackSize()); } + // TODO: This function currently does not work for scalable vectors. int AArch64FrameLowering::getSEHFrameIndexOffset(const MachineFunction &MF, int FI) const { const auto *RegInfo = static_cast( @@ -3268,7 +3269,7 @@ /// For Win64 AArch64 EH, the offset to the Unwind object is from the SP /// before the update. This is easily retrieved as it is exactly the offset /// that is set in processFunctionBeforeFrameFinalized. -int AArch64FrameLowering::getFrameIndexReferencePreferSP( +StackOffset AArch64FrameLowering::getFrameIndexReferencePreferSP( const MachineFunction &MF, int FI, Register &FrameReg, bool IgnoreSPUpdates) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -3276,7 +3277,7 @@ LLVM_DEBUG(dbgs() << "Offset from the SP for " << FI << " is " << MFI.getObjectOffset(FI) << "\n"); FrameReg = AArch64::SP; - return MFI.getObjectOffset(FI); + return StackOffset::getFixed(MFI.getObjectOffset(FI)); } return getFrameIndexReference(MF, FI, FrameReg); Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -626,8 +626,10 @@ if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) { MachineOperand &FI = MI.getOperand(FIOperandNum); - int Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex); - FI.ChangeToImmediate(Offset); + StackOffset Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex); + assert(!Offset.getScalable() && + "Frame offsets with a scalable component are not supported"); + FI.ChangeToImmediate(Offset.getFixed()); return; } Index: llvm/lib/Target/AMDGPU/R600FrameLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/R600FrameLowering.h +++ llvm/lib/Target/AMDGPU/R600FrameLowering.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_AMDGPU_R600FRAMELOWERING_H #include "AMDGPUFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -24,8 +25,8 @@ MachineBasicBlock &MBB) const override {} void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override {} - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; bool hasFP(const MachineFunction &MF) const override { return false; Index: llvm/lib/Target/AMDGPU/R600FrameLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/R600FrameLowering.cpp +++ llvm/lib/Target/AMDGPU/R600FrameLowering.cpp @@ -18,8 +18,9 @@ R600FrameLowering::~R600FrameLowering() = default; /// \returns The number of registers allocated for \p FI. -int R600FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const { +StackOffset +R600FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const R600RegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); @@ -44,5 +45,5 @@ if (FI != -1) OffsetBytes = alignTo(OffsetBytes, MFI.getObjectAlign(FI)); - return OffsetBytes / (getStackWidth(MF) * 4); + return StackOffset::getFixed(OffsetBytes / (getStackWidth(MF) * 4)); } Index: llvm/lib/Target/AMDGPU/R600ISelLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1550,10 +1550,10 @@ unsigned FrameIndex = FIN->getIndex(); Register IgnoredFrameReg; - unsigned Offset = - TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg); - return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op), - Op.getValueType()); + StackOffset Offset = + TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg); + return DAG.getConstant(Offset.getFixed() * 4 * TFL->getStackWidth(MF), + SDLoc(Op), Op.getValueType()); } CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC, Index: llvm/lib/Target/AMDGPU/R600InstrInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -1225,7 +1225,7 @@ const R600FrameLowering *TFL = ST.getFrameLowering(); Register IgnoredFrameReg; - Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg); + Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg).getFixed(); return getIndirectIndexBegin(MF) + Offset; } Index: llvm/lib/Target/AMDGPU/SIFrameLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/SIFrameLowering.h +++ llvm/lib/Target/AMDGPU/SIFrameLowering.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H #include "AMDGPUFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -31,8 +32,8 @@ MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; Index: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1097,12 +1097,13 @@ } #endif -int SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const { +StackOffset SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, + Register &FrameReg) const { const SIRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); FrameReg = RI->getFrameRegister(MF); - return MF.getFrameInfo().getObjectOffset(FI); + return StackOffset::getFixed(MF.getFrameInfo().getObjectOffset(FI)); } void SIFrameLowering::processFunctionBeforeFrameFinalized( Index: llvm/lib/Target/ARM/ARMFrameLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMFrameLowering.h +++ llvm/lib/Target/ARM/ARMFrameLowering.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -47,8 +48,8 @@ bool hasFP(const MachineFunction &MF) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; int ResolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, int SPAdj) const; Index: llvm/lib/Target/ARM/ARMFrameLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -883,9 +883,10 @@ /// debug info. It's the same as what we use for resolving the code-gen /// references for now. FIXME: This can go wrong when references are /// SP-relative and simple call frames aren't used. -int ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const { - return ResolveFrameIndexReference(MF, FI, FrameReg, 0); +StackOffset ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, + Register &FrameReg) const { + return StackOffset::getFixed(ResolveFrameIndexReference(MF, FI, FrameReg, 0)); } int ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, Index: llvm/lib/Target/Hexagon/HexagonFrameLowering.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonFrameLowering.h +++ llvm/lib/Target/Hexagon/HexagonFrameLowering.h @@ -83,8 +83,8 @@ return true; } - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; bool hasFP(const MachineFunction &MF) const override; const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) Index: llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1104,7 +1104,8 @@ Offset = MFI.getObjectOffset(F->getFrameIdx()); } else { Register FrameReg; - Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg); + Offset = + getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed(); } // Subtract 8 to make room for R30 and R31, which are added above. Offset -= 8; @@ -1256,9 +1257,9 @@ return nullptr; } -int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); @@ -1354,7 +1355,7 @@ int RealOffset = Offset; if (!UseFP && !UseAP) RealOffset = FrameSize+Offset; - return RealOffset; + return StackOffset::getFixed(RealOffset); } bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB, Index: llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -207,7 +207,7 @@ int FI = MI.getOperand(FIOp).getIndex(); // Select the base pointer (BP) and calculate the actual offset from BP // to the beginning of the object at index FI. - int Offset = HFI.getFrameIndexReference(MF, FI, BP); + int Offset = HFI.getFrameIndexReference(MF, FI, BP).getFixed(); // Add the offset from the instruction. int RealOffset = Offset + MI.getOperand(FIOp+1).getImm(); bool IsKill = false; Index: llvm/lib/Target/Mips/MipsSEFrameLowering.h =================================================================== --- llvm/lib/Target/Mips/MipsSEFrameLowering.h +++ llvm/lib/Target/Mips/MipsSEFrameLowering.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_MIPS_MIPSSEFRAMELOWERING_H #include "MipsFrameLowering.h" +#include "llvm/include/TypeSize.h" #include namespace llvm { @@ -27,8 +28,8 @@ void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Index: llvm/lib/Target/Mips/MipsSEFrameLowering.cpp =================================================================== --- llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -774,9 +774,9 @@ .addImm(0); } -int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); MipsABIInfo ABI = STI.getABI(); @@ -785,8 +785,9 @@ else FrameReg = hasBP(MF) ? ABI.GetBasePtr() : ABI.GetStackPtr(); - return MFI.getObjectOffset(FI) + MFI.getStackSize() - - getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); + return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - + getOffsetOfLocalArea() + + MFI.getOffsetAdjustment()); } bool MipsSEFrameLowering::spillCalleeSavedRegisters( Index: llvm/lib/Target/NVPTX/NVPTXFrameLowering.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXFrameLowering.h +++ llvm/lib/Target/NVPTX/NVPTXFrameLowering.h @@ -14,6 +14,7 @@ #define LLVM_LIB_TARGET_NVPTX_NVPTXFRAMELOWERING_H #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -24,8 +25,8 @@ bool hasFP(const MachineFunction &MF) const override; void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, Index: llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp +++ llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp @@ -63,12 +63,13 @@ } } -int NVPTXFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +NVPTXFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); FrameReg = NVPTX::VRDepot; - return MFI.getObjectOffset(FI) - getOffsetOfLocalArea(); + return StackOffset::getFixed(MFI.getObjectOffset(FI) - + getOffsetOfLocalArea()); } void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF, Index: llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp +++ llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp @@ -69,7 +69,8 @@ "operand of a DBG_VALUE machine instruction"); Register Reg; int64_t Offset = - TFI.getFrameIndexReference(MF, MI.getOperand(0).getIndex(), Reg); + TFI.getFrameIndexReference(MF, MI.getOperand(0).getIndex(), Reg) + .getFixed(); MI.getOperand(0).ChangeToRegister(Reg, /*isDef=*/false); MI.getOperand(0).setIsDebug(); auto *DIExpr = DIExpression::prepend( Index: llvm/lib/Target/RISCV/RISCVFrameLowering.h =================================================================== --- llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -14,6 +14,7 @@ #define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { class RISCVSubtarget; @@ -29,8 +30,8 @@ void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override; Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -564,9 +564,9 @@ emitSCSEpilogue(MF, MBB, MBBI, DL); } -int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); const auto *RVFI = MF.getInfo(); @@ -618,7 +618,7 @@ Offset += RVFI->getLibCallStackSize(); } } - return Offset; + return StackOffset::getFixed(Offset); } void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -152,9 +152,10 @@ int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); Register FrameReg; - int Offset = - getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + - MI.getOperand(FIOperandNum + 1).getImm(); + int Offset = getFrameLowering(MF) + ->getFrameIndexReference(MF, FrameIndex, FrameReg) + .getFixed() + + MI.getOperand(FIOperandNum + 1).getImm(); if (!isInt<32>(Offset)) { report_fatal_error( Index: llvm/lib/Target/Sparc/SparcFrameLowering.h =================================================================== --- llvm/lib/Target/Sparc/SparcFrameLowering.h +++ llvm/lib/Target/Sparc/SparcFrameLowering.h @@ -15,6 +15,7 @@ #include "Sparc.h" #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -38,8 +39,8 @@ void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; /// targetHandlesStackFrameRounding - Returns true if the target is /// responsible for rounding up the stack frame (probably at emitPrologue Index: llvm/lib/Target/Sparc/SparcFrameLowering.cpp =================================================================== --- llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -257,9 +257,9 @@ MFI.isFrameAddressTaken(); } -int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const SparcSubtarget &Subtarget = MF.getSubtarget(); const MachineFrameInfo &MFI = MF.getFrameInfo(); const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp =================================================================== --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -175,7 +175,7 @@ Register FrameReg; int Offset; - Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); + Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed(); Offset += MI.getOperand(FIOperandNum + 1).getImm(); Index: llvm/lib/Target/SystemZ/SystemZFrameLowering.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZFrameLowering.h +++ llvm/lib/Target/SystemZ/SystemZFrameLowering.h @@ -11,6 +11,7 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { class SystemZTargetMachine; @@ -47,8 +48,8 @@ MachineBasicBlock &PrologMBB) const override; bool hasFP(const MachineFunction &MF) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override; Index: llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -555,7 +555,8 @@ unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); Register IgnoredFrameReg; int64_t Offset = - getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg); + getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg) + .getFixed(); unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( nullptr, DwarfReg, SPOffsetFromCFA + Offset)); @@ -715,14 +716,14 @@ return true; } -int SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { // Our incoming SP is actually SystemZMC::CallFrameSize below the CFA, so // add that difference here. - int64_t Offset = - TargetFrameLowering::getFrameIndexReference(MF, FI, FrameReg); - return Offset + SystemZMC::CallFrameSize; + Stackoffset Offset = + TargetFrameLowering::getFrameIndexReference(MF, FI, FrameReg); + return Offset + StackOffset::getFixed(SystemZMC::CallFrameSize); } MachineBasicBlock::iterator SystemZFrameLowering:: Index: llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -266,8 +266,9 @@ // Decompose the frame index into a base and offset. int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); Register BasePtr; - int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) + - MI->getOperand(FIOperandNum + 1).getImm()); + int64_t Offset = + (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed() + + MI->getOperand(FIOperandNum + 1).getImm()); // Special handling of dbg_value instructions. if (MI->isDebugValue()) { Index: llvm/lib/Target/VE/VEFrameLowering.h =================================================================== --- llvm/lib/Target/VE/VEFrameLowering.h +++ llvm/lib/Target/VE/VEFrameLowering.h @@ -15,6 +15,7 @@ #include "VE.h" #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -48,8 +49,8 @@ void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override { Index: llvm/lib/Target/VE/VEFrameLowering.cpp =================================================================== --- llvm/lib/Target/VE/VEFrameLowering.cpp +++ llvm/lib/Target/VE/VEFrameLowering.cpp @@ -320,8 +320,9 @@ return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); } -int VEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const { +StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const VERegisterInfo *RegInfo = STI.getRegisterInfo(); const VEMachineFunctionInfo *FuncInfo = MF.getInfo(); @@ -333,7 +334,8 @@ // If there's a leaf proc, all offsets need to be %sp-based, // because we haven't caused %fp to actually point to our frame. FrameReg = VE::SX11; // %sp - return FrameOffset + MF.getFrameInfo().getStackSize(); + return StackOffset::getFixed(FrameOffset + + MF.getFrameInfo().getStackSize()); } if (RegInfo->needsStackRealignment(MF) && !isFixed) { // If there is dynamic stack realignment, all local object @@ -343,11 +345,12 @@ FrameReg = VE::SX17; // %bp else FrameReg = VE::SX11; // %sp - return FrameOffset + MF.getFrameInfo().getStackSize(); + return StackOffset::getFixed(FrameOffset + + MF.getFrameInfo().getStackSize()); } // Finally, default to using %fp. FrameReg = RegInfo->getFrameRegister(MF); - return FrameOffset; + return StackOffset::getFixed(FrameOffset); } bool VEFrameLowering::isLeafProc(MachineFunction &MF) const { Index: llvm/lib/Target/VE/VERegisterInfo.cpp =================================================================== --- llvm/lib/Target/VE/VERegisterInfo.cpp +++ llvm/lib/Target/VE/VERegisterInfo.cpp @@ -116,7 +116,7 @@ Register FrameReg; int Offset; - Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); + Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed(); Offset += MI.getOperand(FIOperandNum + 2).getImm(); Index: llvm/lib/Target/X86/X86FrameLowering.h =================================================================== --- llvm/lib/Target/X86/X86FrameLowering.h +++ llvm/lib/Target/X86/X86FrameLowering.h @@ -14,6 +14,7 @@ #define LLVM_LIB_TARGET_X86_X86FRAMELOWERING_H #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -102,16 +103,17 @@ bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override; bool needsFrameIndexResolution(const MachineFunction &MF) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const; - int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, - Register &SPReg, int Adjustment) const; - int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, - Register &FrameReg, - bool IgnoreSPUpdates) const override; + StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, + Register &SPReg, int Adjustment) const; + StackOffset + getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, + Register &FrameReg, + bool IgnoreSPUpdates) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, Index: llvm/lib/Target/X86/X86FrameLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86FrameLowering.cpp +++ llvm/lib/Target/X86/X86FrameLowering.cpp @@ -1689,7 +1689,7 @@ assert(Personality == EHPersonality::MSVC_CXX); Register FrameReg; int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex; - int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg); + int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg).getFixed(); // ESP is the first field, so no extra displacement is needed. addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg, false, EHRegOffset) @@ -1710,8 +1710,9 @@ if (IsWin64Prologue && IsFunclet) Offset = getWin64EHFrameIndexRef(MF, FI, IgnoredFrameReg); else - Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg) + - SEHFrameOffset; + Offset = + getFrameIndexReference(MF, FI, IgnoredFrameReg).getFixed() + + SEHFrameOffset; HasWinCFI = true; assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data"); @@ -1783,7 +1784,8 @@ unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr; Register UsedReg; int Offset = - getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg); + getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg) + .getFixed(); assert(UsedReg == BasePtr); addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset) .addReg(FramePtr) @@ -1861,7 +1863,8 @@ const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo(); Register SPReg; int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg, - /*IgnoreSPUpdates*/ true); + /*IgnoreSPUpdates*/ true) + .getFixed(); assert(Offset >= 0 && SPReg == TRI->getStackRegister()); return static_cast(Offset); } @@ -2089,8 +2092,9 @@ } } -int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const { +StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); bool IsFixed = MFI.isFixedObjectIndex(FI); @@ -2153,23 +2157,23 @@ assert(HasFP && "VLAs and dynamic stack realign, but no FP?!"); if (FI < 0) { // Skip the saved EBP. - return Offset + SlotSize + FPDelta; + return StackOffset::getFixed(Offset + SlotSize + FPDelta); } else { assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize))); - return Offset + StackSize; + return StackOffset::getFixed(Offset + StackSize); } } else if (TRI->needsStackRealignment(MF)) { if (FI < 0) { // Skip the saved EBP. - return Offset + SlotSize + FPDelta; + return StackOffset::getFixed(Offset + SlotSize + FPDelta); } else { assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize))); - return Offset + StackSize; + return StackOffset::getFixed(Offset + StackSize); } // FIXME: Support tail calls } else { if (!HasFP) - return Offset + StackSize; + return StackOffset::getFixed(Offset + StackSize); // Skip the saved EBP. Offset += SlotSize; @@ -2180,7 +2184,7 @@ Offset -= TailCallReturnAddrDelta; } - return Offset + FPDelta; + return StackOffset::getFixed(Offset + FPDelta); } int X86FrameLowering::getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, @@ -2191,24 +2195,27 @@ const auto it = WinEHXMMSlotInfo.find(FI); if (it == WinEHXMMSlotInfo.end()) - return getFrameIndexReference(MF, FI, FrameReg); + return getFrameIndexReference(MF, FI, FrameReg).getFixed(); FrameReg = TRI->getStackRegister(); return alignDown(MFI.getMaxCallFrameSize(), getStackAlign().value()) + it->second; } -int X86FrameLowering::getFrameIndexReferenceSP(const MachineFunction &MF, - int FI, Register &FrameReg, - int Adjustment) const { +StackOffset +X86FrameLowering::getFrameIndexReferenceSP(const MachineFunction &MF, int FI, + Register &FrameReg, + int Adjustment) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); FrameReg = TRI->getStackRegister(); - return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment; + return StackOffset::getFixed(MFI.getObjectOffset(FI) - + getOffsetOfLocalArea() + Adjustment); } -int X86FrameLowering::getFrameIndexReferencePreferSP( - const MachineFunction &MF, int FI, Register &FrameReg, - bool IgnoreSPUpdates) const { +StackOffset +X86FrameLowering::getFrameIndexReferencePreferSP(const MachineFunction &MF, + int FI, Register &FrameReg, + bool IgnoreSPUpdates) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); // Does not include any dynamic realign. @@ -3294,7 +3301,7 @@ } Register UsedReg; - int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg); + int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg).getFixed(); int EndOffset = -EHRegOffset - EHRegSize; FuncInfo.EHRegNodeEndOffset = EndOffset; @@ -3317,7 +3324,8 @@ // MOV32rm SavedEBPOffset(%esi), %ebp assert(X86FI->getHasSEHFramePtrSave()); int Offset = - getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg); + getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg) + .getFixed(); assert(UsedReg == BasePtr); addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr), UsedReg, true, Offset) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp =================================================================== --- llvm/lib/Target/X86/X86RegisterInfo.cpp +++ llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -732,11 +732,12 @@ assert((!needsStackRealignment(MF) || MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) && "Return instruction can only reference SP relative frame objects"); - FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0); + FIOffset = + TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed(); } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) { FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr); } else { - FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr); + FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed(); } // LOCAL_ESCAPE uses a single offset, with no register. It only works in the