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Sparc: Support PSR, TBR, WIM read/write instructions.

Authored by jyknight on Apr 10 2015, 8:00 AM.

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jyknight updated this revision to Diff 23601.Apr 10 2015, 8:00 AM
jyknight retitled this revision from to Sparc: Support PSR, TBR, WIM read/write instructions..
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venkatra requested changes to this revision.Apr 28 2015, 8:05 PM
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735 ↗(On Diff #23964)

These instructions and the registers %wim, %tbr, %psr do not exist in sparcV9. Predicate them with HasNoV9.

This revision now requires changes to proceed.Apr 28 2015, 8:05 PM
jyknight updated this revision to Diff 24653.Apr 29 2015, 1:10 PM
jyknight edited edge metadata.

Conditionalized sparcv8-only instructions.

Note: I left the registers and asm syntax enabled in both modes; that seems to be what's typically done elsewhere, how gcc's assembler works, and I imagine might be useful for if you wanted to write an asm file which can run in both v8 and v9 processors (with appropriate runtime branches).

735 ↗(On Diff #23964)

Yes thanks, done.

echristo accepted this revision.May 13 2015, 3:13 PM
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LGTM. I'm not sure if we want to lock down the assembler more, but since we haven't up to this point for sparc we can make that decision later.



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