Sparc: Support PSR, TBR, WIM read/write instructions.

[jyknight]

rebase.

[jyknight]

Ping

[venkatra]

lib/Target/Sparc/SparcInstrInfo.td

735 ↗

(On Diff #23964)

These instructions and the registers %wim, %tbr, %psr do not exist in sparcV9. Predicate them with HasNoV9.

[jyknight]

Conditionalized sparcv8-only instructions.

[jyknight]

Note: I left the registers and asm syntax enabled in both modes; that seems to be what's typically done elsewhere, how gcc's assembler works, and I imagine might be useful for if you wanted to write an asm file which can run in both v8 and v9 processors (with appropriate runtime branches).

lib/Target/Sparc/SparcInstrInfo.td

735 ↗

(On Diff #23964)

Yes thanks, done.

[jyknight]

ping

[jyknight]

ping

[echristo]

LGTM. I'm not sure if we want to lock down the assembler more, but since we haven't up to this point for sparc we can make that decision later.

Thanks!

-eric

llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

 class SparcOperand : public MCParsedAsmOperand {
 public:
   enum RegisterKind {
     rk_None,
     rk_IntReg,
     rk_FloatReg,
     rk_DoubleReg,
     rk_QuadReg,
-    rk_CCReg,
-    rk_ASRReg
+    rk_Special,
   };
+
 private:
   enum KindTy {
     k_Token,
     k_Register,
     k_Immediate,
     k_MemoryReg,
     k_MemoryImm
   } Kind;
case AsmToken::Percent:
     if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
       StringRef name = Parser.getTok().getString();
       Parser.Lex(); // Eat the identifier token.
       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
       switch (RegNo) {
       default:
         Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
         break;
-
+      case Sparc::PSR:
+        Op = SparcOperand::CreateToken("%psr", S);
+        break;
+      case Sparc::WIM:
+        Op = SparcOperand::CreateToken("%wim", S);
+        break;
+      case Sparc::TBR:
+        Op = SparcOperand::CreateToken("%tbr", S);
+        break;
       case Sparc::ICC:
         if (name == "xcc")
           Op = SparcOperand::CreateToken("%xcc", S);
         else
           Op = SparcOperand::CreateToken("%icc", S);
         break;
       }
       break;
if (Tok.is(AsmToken::Identifier)) {
     if (name.equals("sp")) {
       RegNo = Sparc::O6;
       RegKind = SparcOperand::rk_IntReg;
       return true;
     }
 
     if (name.equals("y")) {
       RegNo = Sparc::Y;
-      RegKind = SparcOperand::rk_ASRReg;
+      RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     if (name.substr(0, 3).equals_lower("asr")
         && !name.substr(3).getAsInteger(10, intVal)
         && intVal > 0 && intVal < 32) {
       RegNo = ASRRegs[intVal];
-      RegKind = SparcOperand::rk_ASRReg;
+      RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     if (name.equals("icc")) {
       RegNo = Sparc::ICC;
-      RegKind = SparcOperand::rk_CCReg;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+
+    if (name.equals("psr")) {
+      RegNo = Sparc::PSR;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+
+    if (name.equals("wim")) {
+      RegNo = Sparc::WIM;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+
+    if (name.equals("tbr")) {
+      RegNo = Sparc::TBR;
+      RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     if (name.equals("xcc")) {
       // FIXME:: check 64bit.
       RegNo = Sparc::ICC;
-      RegKind = SparcOperand::rk_CCReg;
+      RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     // %fcc0 - %fcc3
     if (name.substr(0, 3).equals_lower("fcc")
         && !name.substr(3).getAsInteger(10, intVal)
         && intVal < 4) {
       // FIXME: check 64bit and  handle %fcc1 - %fcc3
       RegNo = Sparc::FCC0 + intVal;
-      RegKind = SparcOperand::rk_CCReg;
+      RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     // %g0 - %g7
     if (name.substr(0, 1).equals_lower("g")
         && !name.substr(1).getAsInteger(10, intVal)
         && intVal < 8) {
       RegNo = IntRegs[intVal];

llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td

 }
 
 // Section B.28 - Read State Register Instructions
 let rs2 = 0 in
   def RDASR : F3_1<2, 0b101000,
                  (outs IntRegs:$rd), (ins ASRRegs:$rs1),
                  "rd $rs1, $rd", []>;
 
+// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
+let Predicates = [HasNoV9] in {
+  let rs2 = 0, rs1 = 0, Uses=[PSR] in
+    def RDPSR : F3_1<2, 0b101001,
+         (outs IntRegs:$rd), (ins),
+         "rd %psr, $rd", []>;
+
+  let rs2 = 0, rs1 = 0, Uses=[WIM] in
+    def RDWIM : F3_1<2, 0b101010,
+         (outs IntRegs:$rd), (ins),
+         "rd %wim, $rd", []>;
+
+  let rs2 = 0, rs1 = 0, Uses=[TBR] in
+    def RDTBR : F3_1<2, 0b101011,
+         (outs IntRegs:$rd), (ins),
+         "rd %tbr, $rd", []>;
+}
+
 // Section B.29 - Write State Register Instructions
 def WRASRrr : F3_1<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                  "wr $rs1, $rs2, $rd", []>;
 def WRASRri : F3_2<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                  "wr $rs1, $simm13, $rd", []>;
 
+// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
+let Predicates = [HasNoV9] in {
+  let Defs = [PSR], rd=0 in {
+    def WRPSRrr : F3_1<2, 0b110001,
+         (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
+         "wr $rs1, $rs2, %psr", []>;
+    def WRPSRri : F3_2<2, 0b110001,
+         (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
+         "wr $rs1, $simm13, %psr", []>;
+  }
+
+  let Defs = [WIM], rd=0 in {
+    def WRWIMrr : F3_1<2, 0b110010,
+         (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
+         "wr $rs1, $rs2, %wim", []>;
+    def WRWIMri : F3_2<2, 0b110010,
+         (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
+         "wr $rs1, $simm13, %wim", []>;
+  }
+
+  let Defs = [TBR], rd=0 in {
+    def WRTBRrr : F3_1<2, 0b110011,
+         (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
+         "wr $rs1, $rs2, %tbr", []>;
+    def WRTBRri : F3_2<2, 0b110011,
+         (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
+         "wr $rs1, $simm13, %tbr", []>;
+  }
+}
+
 // Convert Integer to Floating-point Instructions, p. 141
 def FITOS : F3_3u<2, 0b110100, 0b011000100,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fitos $rs2, $rd",
                  [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
 def FITOD : F3_3u<2, 0b110100, 0b011001000,
                  (outs DFPRegs:$rd), (ins FPRegs:$rs2),
                  "fitod $rs2, $rd",

llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td

 def ASR25 : SparcCtrlReg<25, "ASR25">;
 def ASR26 : SparcCtrlReg<26, "ASR26">;
 def ASR27 : SparcCtrlReg<27, "ASR27">;
 def ASR28 : SparcCtrlReg<28, "ASR28">;
 def ASR29 : SparcCtrlReg<29, "ASR29">;
 def ASR30 : SparcCtrlReg<30, "ASR30">;
 def ASR31 : SparcCtrlReg<31, "ASR31">;
 
+// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
+def PSR : SparcCtrlReg<0, "PSR">;
+def WIM : SparcCtrlReg<0, "WIM">;
+def TBR : SparcCtrlReg<0, "TBR">;
+
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;

llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt

+# RUN: llvm-mc --disassemble %s -triple=sparc-unknown-linux | FileCheck %s
+
+# CHECK: wr %g1, -2, %y
+0x81 0x80 0x7f 0xfe
+
+# CHECK: rd %y, %i0
+0xb1 0x40 0x00 0x00
+
+# CHECK: rd %asr1, %i0
+0xb1 0x40 0x40 0x00
+
+# CHECK: wr %i0, 5, %y
+0x81 0x86 0x20 0x05
+
+# CHECK: wr %i0, %i1, %asr15
+0x9f 0x86 0x00 0x19
+
+# CHECK: rd %psr, %i0
+0xb1 0x48 0x00 0x00
+
+# CHECK: rd %wim, %i0
+0xb1 0x50 0x00 0x00
+
+# CHECK: rd %tbr, %i0
+0xb1 0x58 0x00 0x00
+
+# CHECK: wr %i0, 5, %psr
+0x81 0x8e 0x20 0x05
+
+# CHECK: wr %i0, 5, %wim
+0x81 0x96 0x20 0x05
+
+# CHECK: wr %i0, 5, %tbr
+0x81 0x9e 0x20 0x05

llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt

 0x84 0x00 0x7f 0xf6
 
 # CHECK: save %sp, -196, %sp
 0x9d 0xe3 0xbf 0x3c
 
 # CHECK: cmp %g1, -2
 0x80 0xa0 0x7f 0xfe
 
-# CHECK: wr %g1, -2, %y
-0x81 0x80 0x7f 0xfe
-
 # CHECK: unimp 12
 0x00 0x00 0x00 0x0c
 
 # CHECK: jmp %g1+12
 0x81,0xc0,0x60,0x0c
 
 # CHECK: retl
 0x81 0xc3 0xe0 0x08
 
 # CHECK: ret
 0x81,0xc7,0xe0,0x08
 
 # CHECK:  rett %i7+8
 0x81 0xcf 0xe0 0x08
 
-# CHECK: rd %y, %i0
-0xb1 0x40 0x00 0x00
-
-# CHECK: rd %asr1, %i0
-0xb1 0x40 0x40 0x00
-
-# CHECK: wr %i0, 5, %y
-0x81 0x86 0x20 0x05
-
-# CHECK: wr %i0, %i1, %asr15
-0x9f 0x86 0x00 0x19
-
 # CHECK: stbar
 0x81 0x43 0xc0 0x00

llvm/trunk/test/MC/Sparc/sparc-special-registers.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
         ! CHECK: wr %i0, 5, %y         ! encoding: [0x81,0x86,0x20,0x05]
         wr %i0, 5, %y
 
         ! CHECK: wr %i0, %i1, %asr15   ! encoding: [0x9f,0x86,0x00,0x19]
         wr %i0, %i1, %asr15
 
         ! CHECK: rd %asr15, %g0        ! encoding: [0x81,0x43,0xc0,0x00]
         rd %asr15, %g0
+
+        ! CHECK: rd %psr, %i0          ! encoding: [0xb1,0x48,0x00,0x00]
+        rd %psr, %i0
+
+        ! CHECK: rd %wim, %i0          ! encoding: [0xb1,0x50,0x00,0x00]
+        rd %wim, %i0
+
+        ! CHECK: rd %tbr, %i0          ! encoding: [0xb1,0x58,0x00,0x00]
+        rd %tbr, %i0
+
+        ! CHECK: wr %i0, 5, %psr          ! encoding: [0x81,0x8e,0x20,0x05]
+        wr %i0, 5, %psr
+
+        ! CHECK: wr %i0, 5, %wim          ! encoding: [0x81,0x96,0x20,0x05]
+        wr %i0, 5, %wim
+
+        ! CHECK: wr %i0, 5, %tbr          ! encoding: [0x81,0x9e,0x20,0x05]
+        wr %i0, 5, %tbr