Index: llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -4585,6 +4585,10 @@
     return true;
   }
 
+  // FIXME: support for integer vectors.
+  if (LHS->getType()->isVectorTy())
+    return false;
+
   switch (computeOverflow(BinaryOp, IsSigned, LHS, RHS, &OrigI)) {
     case OverflowResult::MayOverflow:
       return false;
Index: llvm/test/Transforms/InstCombine/with_overflow.ll
===================================================================
--- llvm/test/Transforms/InstCombine/with_overflow.ll
+++ llvm/test/Transforms/InstCombine/with_overflow.ll
@@ -597,3 +597,49 @@
   %a = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %y, i8 2)
   ret { i8, i1 } %a
 }
+
+; Vector ops between constants, should be folded (but atm they're not).
+; Make sure the overflow vector is not folded into a scalar value.
+
+declare { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+declare { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+declare { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+declare { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+declare { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+declare { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i1> @sadd_const_vector() nounwind {
+  %x = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 1, i32 6, i32 7, i32 8>)
+  %y = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+  ret <4 x i1> %y
+}
+
+define <4 x i1> @uadd_const_vector() nounwind {
+  %x = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 1, i32 6, i32 7, i32 8>)
+  %y = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+  ret <4 x i1> %y
+}
+
+define <4 x i1> @ssub_const_vector() nounwind {
+  %x = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 1, i32 6, i32 7, i32 8>)
+  %y = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+  ret <4 x i1> %y
+}
+
+define <4 x i1> @usub_const_vector() nounwind {
+  %x = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 1, i32 6, i32 7, i32 8>)
+  %y = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+  ret <4 x i1> %y
+}
+
+define <4 x i1> @smul_const_vector() nounwind {
+  %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 1, i32 6, i32 7, i32 8>)
+  %y = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+  ret <4 x i1> %y
+}
+
+define <4 x i1> @umul_const_vector() nounwind {
+  %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 1, i32 6, i32 7, i32 8>)
+  %y = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+  ret <4 x i1> %y
+}