diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -2836,9 +2836,12 @@ return true; Register CSelOpc = selectSelectOpc(I, MRI, RBI); + // Make sure to use an unused vreg instead of wzr, so that the peephole + // optimizations will be able to optimize these. + Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); MachineInstr &TstMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) - .addDef(AArch64::WZR) + .addDef(DeadVReg) .addUse(CondReg) .addImm(AArch64_AM::encodeLogicalImmediate(1, 32)); @@ -3853,17 +3856,17 @@ MachineIRBuilder &MIRBuilder) const { assert(LHS.isReg() && RHS.isReg() && "Expected register operands?"); MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); - unsigned RegSize = MRI.getType(LHS.getReg()).getSizeInBits(); + LLT Ty = MRI.getType(LHS.getReg()); + unsigned RegSize = Ty.getSizeInBits(); bool Is32Bit = (RegSize == 32); const unsigned OpcTable[3][2] = {{AArch64::ANDSXri, AArch64::ANDSWri}, {AArch64::ANDSXrs, AArch64::ANDSWrs}, {AArch64::ANDSXrr, AArch64::ANDSWrr}}; - Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; // ANDS needs a logical immediate for its immediate form. Check if we can // fold one in. if (auto ValAndVReg = getConstantVRegValWithLookThrough(RHS.getReg(), MRI)) { if (AArch64_AM::isLogicalImmediate(ValAndVReg->Value, RegSize)) { - auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {ZReg}, {LHS}); + auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {Ty}, {LHS}); TstMI.addImm( AArch64_AM::encodeLogicalImmediate(ValAndVReg->Value, RegSize)); constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI); @@ -3872,8 +3875,8 @@ } if (auto Fns = selectLogicalShiftedRegister(RHS)) - return emitInstr(OpcTable[1][Is32Bit], {ZReg}, {LHS}, MIRBuilder, Fns); - return emitInstr(OpcTable[2][Is32Bit], {ZReg}, {LHS, RHS}, MIRBuilder); + return emitInstr(OpcTable[1][Is32Bit], {Ty}, {LHS}, MIRBuilder, Fns); + return emitInstr(OpcTable[2][Is32Bit], {Ty}, {LHS, RHS}, MIRBuilder); } std::pair @@ -4391,17 +4394,14 @@ // At this point, we know we can select an immediate form. Go ahead and do // that. - Register ZReg; unsigned Opc; if (Size == 32) { - ZReg = AArch64::WZR; Opc = AArch64::SUBSWri; } else { - ZReg = AArch64::XZR; Opc = AArch64::SUBSXri; } - auto CmpMI = MIB.buildInstr(Opc, {ZReg}, {LHS.getReg()}); + auto CmpMI = MIB.buildInstr(Opc, {Ty}, {LHS.getReg()}); for (auto &RenderFn : *ImmFns) RenderFn(CmpMI); constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI); @@ -4419,7 +4419,6 @@ // Since we will select the G_ICMP to a SUBS, we can potentially fold the // shift into the subtract. static const unsigned OpcTable[2] = {AArch64::SUBSWrs, AArch64::SUBSXrs}; - static const Register ZRegTable[2] = {AArch64::WZR, AArch64::XZR}; auto ImmFns = selectShiftedRegister(RHS); if (!ImmFns) return nullptr; @@ -4428,9 +4427,8 @@ assert(!Ty.isVector() && "Expected scalar or pointer only?"); unsigned Size = Ty.getSizeInBits(); bool Idx = (Size == 64); - Register ZReg = ZRegTable[Idx]; unsigned Opc = OpcTable[Idx]; - auto CmpMI = MIB.buildInstr(Opc, {ZReg}, {LHS.getReg()}); + auto CmpMI = MIB.buildInstr(Opc, {Ty}, {LHS.getReg()}); for (auto &RenderFn : *ImmFns) RenderFn(CmpMI); constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir @@ -31,7 +31,7 @@ ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]] ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] - ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv ; CHECK: $w1 = COPY [[CSINCWr]] ; CHECK: $s0 = COPY [[FCSELSrrr]] @@ -98,7 +98,7 @@ ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0 - ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv ; CHECK: $s0 = COPY [[FCSELSrrr]] ; CHECK: RET_ReallyLR implicit $s0 @@ -165,7 +165,7 @@ ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]] ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]] ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] - ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv ; CHECK: $s0 = COPY [[FCSELSrrr]] ; CHECK: RET_ReallyLR implicit $s0 @@ -201,7 +201,7 @@ ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]] ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]] ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] - ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv ; CHECK: $s0 = COPY [[FCSELSrrr]] ; CHECK: RET_ReallyLR implicit $s0 @@ -297,7 +297,7 @@ ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]] ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]] ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] - ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv ; CHECK: $d0 = COPY [[FCSELDrrr]] ; CHECK: RET_ReallyLR implicit $d0 @@ -333,7 +333,7 @@ ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]] ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]] ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] - ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv ; CHECK: $d0 = COPY [[FCSELDrrr]] ; CHECK: RET_ReallyLR implicit $d0 @@ -394,7 +394,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0 ; CHECK: BL @copy_from_physreg, implicit-def $w0 - ; CHECK: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv ; CHECK: BL @copy_from_physreg, implicit-def $w0 ; CHECK: $s0 = COPY [[FCSELSrrr]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir @@ -22,7 +22,7 @@ ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr - ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -84,7 +84,7 @@ ; CHECK: %copy1:gpr32sp = COPY $w0 ; CHECK: %copy2:gpr32 = COPY $w1 ; CHECK: %cst:gpr32 = MOVi32imm -1 - ; CHECK: $wzr = SUBSWri %copy1, 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy1, 0, 0, implicit-def $nzcv ; CHECK: %select:gpr32 = CSELWr %cst, %copy2, 11, implicit $nzcv ; CHECK: $w0 = COPY %select ; CHECK: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir @@ -142,7 +142,7 @@ ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: TBNZW [[CSINCWr]], 0, %bb.1 ; CHECK: B %bb.0 @@ -175,7 +175,7 @@ ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK: TBNZW [[CSINCWr]], 0, %bb.1 ; CHECK: B %bb.0 @@ -237,7 +237,7 @@ ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064 - ; CHECK: $xzr = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv ; CHECK: Bcc 1, %bb.1, implicit $nzcv ; CHECK: B %bb.0 ; CHECK: bb.1: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir @@ -308,7 +308,7 @@ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK: $wzr = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv + ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -340,7 +340,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 - ; CHECK: $xzr = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv + ; CHECK: [[ANDSXrr:%[0-9]+]]:gpr64 = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY1]], 0, implicit $nzcv ; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: RET_ReallyLR implicit $x0 @@ -372,7 +372,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]] - ; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -404,7 +404,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]] - ; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -433,7 +433,7 @@ ; CHECK-LABEL: name: imm_tst ; CHECK: liveins: $w0, $w1 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: $wzr = ANDSWri [[COPY]], 1, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 1, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -466,7 +466,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1 - ; CHECK: $wzr = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv + ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -529,7 +529,7 @@ ; CHECK: %zero:gpr64 = COPY $xzr ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: %one:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 - ; CHECK: $xzr = ANDSXrs %zero, %copy, 16, implicit-def $nzcv + ; CHECK: [[ANDSXrs:%[0-9]+]]:gpr64 = ANDSXrs %zero, %copy, 16, implicit-def $nzcv ; CHECK: %select:gpr64 = CSELXr %one, %zero, 0, implicit $nzcv ; CHECK: $x0 = COPY %select ; CHECK: RET_ReallyLR implicit $x0 @@ -562,7 +562,7 @@ ; CHECK: %copy:gpr32 = COPY $w1 ; CHECK: %zero:gpr32 = COPY $wzr ; CHECK: %one:gpr32 = MOVi32imm 1 - ; CHECK: $wzr = ANDSWrs %zero, %copy, 16, implicit-def $nzcv + ; CHECK: [[ANDSWrs:%[0-9]+]]:gpr32 = ANDSWrs %zero, %copy, 16, implicit-def $nzcv ; CHECK: %select:gpr32 = CSELWr %one, %zero, 0, implicit $nzcv ; CHECK: $w0 = COPY %select ; CHECK: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir @@ -23,7 +23,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -49,7 +49,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -75,7 +75,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -101,7 +101,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -127,7 +127,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -153,7 +153,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -179,7 +179,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -204,7 +204,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -229,7 +229,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -254,7 +254,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -279,7 +279,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -304,7 +304,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -331,7 +331,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -356,7 +356,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -381,7 +381,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -408,7 +408,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -433,7 +433,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -458,7 +458,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -484,7 +484,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -509,7 +509,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -534,7 +534,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -559,7 +559,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -584,7 +584,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -609,7 +609,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -634,7 +634,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -659,7 +659,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -684,7 +684,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -711,7 +711,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -736,7 +736,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 @@ -761,7 +761,7 @@ ; CHECK: liveins: $w0, $w1 ; CHECK: %copy0:gpr32 = COPY $w0 ; CHECK: %copy1:gpr32 = COPY $w1 - ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv + ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: $w0 = COPY %cmp ; CHECK: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir @@ -21,7 +21,7 @@ ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK: $wzr = ANDSWri [[DEF]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv ; CHECK: bb.2: ; CHECK: successors: %bb.2(0x80000000) @@ -75,7 +75,7 @@ ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK: $wzr = ANDSWri [[DEF]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]] ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir @@ -21,7 +21,7 @@ ; CHECK-LABEL: name: slt_to_sle_s32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: SUBSWri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: $w0 = COPY [[ANDWri]] @@ -56,7 +56,7 @@ ; CHECK-LABEL: name: slt_to_sle_s64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -94,7 +94,7 @@ ; CHECK-LABEL: name: sge_to_sgt_s32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: $w0 = COPY [[ANDWri]] @@ -129,7 +129,7 @@ ; CHECK-LABEL: name: sge_to_sgt_s64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -167,7 +167,7 @@ ; CHECK-LABEL: name: ult_to_ule_s32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: $w0 = COPY [[ANDWri]] @@ -202,7 +202,7 @@ ; CHECK-LABEL: name: ult_to_ule_s64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -240,7 +240,7 @@ ; CHECK-LABEL: name: uge_to_ugt_s32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: $w0 = COPY [[ANDWri]] @@ -275,7 +275,7 @@ ; CHECK-LABEL: name: uge_to_ugt_s64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -315,7 +315,7 @@ ; CHECK-LABEL: name: sle_to_slt_s32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: $w0 = COPY [[ANDWri]] @@ -350,7 +350,7 @@ ; CHECK-LABEL: name: sle_to_slt_s64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -388,7 +388,7 @@ ; CHECK-LABEL: name: sgt_to_sge_s32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: $w0 = COPY [[ANDWri]] @@ -423,7 +423,7 @@ ; CHECK-LABEL: name: sgt_to_sge_s64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -612,7 +612,7 @@ ; CHECK-LABEL: name: no_opt_zero ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 0, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 @@ -648,9 +648,9 @@ ; CHECK: %a:gpr64common = COPY $x0 ; CHECK: %b:gpr64 = COPY $x1 ; CHECK: %c:gpr64 = COPY $x2 - ; CHECK: $xzr = SUBSXri %a, 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %a, 0, 0, implicit-def $nzcv ; CHECK: %select1:gpr64 = CSELXr %a, %b, 11, implicit $nzcv - ; CHECK: $xzr = SUBSXri %a, 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri1:%[0-9]+]]:gpr64 = SUBSXri %a, 0, 0, implicit-def $nzcv ; CHECK: %select2:gpr64 = CSELXr %b, %c, 11, implicit $nzcv ; CHECK: %add:gpr64 = ADDXrr %select1, %select2 ; CHECK: $x0 = COPY %add diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir @@ -158,7 +158,7 @@ ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load 8) - ; CHECK: $xzr = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv ; CHECK: Bcc 0, %bb.2, implicit $nzcv ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x80000000) @@ -191,18 +191,18 @@ regBankSelected: true body: | - ; The G_ICMP here will be optimized into a slt against 0. - ; The branch should inherit this change, so we should have Bcc 11 rather than - ; Bcc 13. - ; CHECK-LABEL: name: update_pred_minus_one ; CHECK: bb.0: ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv ; CHECK: Bcc 11, %bb.1, implicit $nzcv ; CHECK: B %bb.0 ; CHECK: bb.1: + ; The G_ICMP here will be optimized into a slt against 0. + ; The branch should inherit this change, so we should have Bcc 11 rather than + ; Bcc 13. + bb.0: liveins: $w0 successors: %bb.0, %bb.1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir @@ -12,7 +12,7 @@ ; CHECK-LABEL: name: cmp_imm_32 ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -35,7 +35,7 @@ ; CHECK-LABEL: name: cmp_imm_64 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: $xzr = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -82,7 +82,7 @@ ; CHECK-LABEL: name: cmp_imm_lookthrough ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: RET_ReallyLR implicit $w0 @@ -105,7 +105,7 @@ ; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir @@ -26,7 +26,7 @@ ; CHECK: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load 1) ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 - ; CHECK: $xzr = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv ; CHECK: Bcc 8, %bb.3, implicit $nzcv ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) @@ -35,6 +35,7 @@ ; CHECK: BR %6 ; CHECK: bb.2: ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: B %bb.3 ; CHECK: bb.3: ; CHECK: RET_ReallyLR bb.1: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir @@ -60,7 +60,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32 - ; CHECK: $xzr = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv ; CHECK: Bcc 8, %bb.4, implicit $nzcv ; CHECK: bb.1.entry: ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir @@ -20,7 +20,7 @@ ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]] ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]] - ; CHECK: $wzr = ANDSWri [[COPY4]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv ; CHECK: $s0 = COPY [[FCSELSrrr]] ; CHECK: RET_ReallyLR implicit $s0 @@ -52,7 +52,7 @@ ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]] ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]] - ; CHECK: $wzr = ANDSWri [[COPY4]], 0, implicit-def $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv ; CHECK: $d0 = COPY [[FCSELDrrr]] ; CHECK: RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir @@ -284,11 +284,11 @@ - { id: 9, class: gpr } # CHECK: body: -# CHECK: $wzr = ANDSWri %10, 0, implicit-def $nzcv +# CHECK: ANDSWri %10, 0, implicit-def $nzcv # CHECK: %3:gpr32 = CSELWr %1, %2, 1, implicit $nzcv -# CHECK: $wzr = ANDSWri %10, 0, implicit-def $nzcv +# CHECK: ANDSWri %10, 0, implicit-def $nzcv # CHECK: %6:gpr64 = CSELXr %4, %5, 1, implicit $nzcv -# CHECK: $wzr = ANDSWri %10, 0, implicit-def $nzcv +# CHECK: ANDSWri %10, 0, implicit-def $nzcv # CHECK: %9:gpr64 = CSELXr %7, %8, 1, implicit $nzcv body: | bb.0: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir @@ -71,7 +71,7 @@ ; CHECK: bb.0: ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: %copy:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri %copy, 1, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv ; CHECK: Bcc 11, %bb.1, implicit $nzcv ; CHECK: B %bb.0 ; CHECK: bb.1: @@ -99,7 +99,7 @@ ; CHECK: bb.0: ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: %copy:gpr64 = COPY $x0 - ; CHECK: $xzr = ANDSXri %copy, 8000, implicit-def $nzcv + ; CHECK: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: TBNZW %cmp, 0, %bb.1 ; CHECK: B %bb.0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir @@ -71,7 +71,7 @@ ; CHECK: bb.0: ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: %copy:gpr32sp = COPY $w0 - ; CHECK: $wzr = SUBSWri %copy, 1, 0, implicit-def $nzcv + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv ; CHECK: Bcc 12, %bb.1, implicit $nzcv ; CHECK: B %bb.0 ; CHECK: bb.1: @@ -100,7 +100,7 @@ ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %and:gpr64sp = ANDXri %copy, 8000 - ; CHECK: $xzr = SUBSXri %and, 0, 0, implicit-def $nzcv + ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %and, 0, 0, implicit-def $nzcv ; CHECK: Bcc 10, %bb.1, implicit $nzcv ; CHECK: B %bb.0 ; CHECK: bb.1: