diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -414,12 +414,12 @@ memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor)); assert(isUInt<32>(PI.ScratchSize)); - assert(isUInt<32>(PI.ComputePGMRSrc1)); + assert(isUInt<32>(PI.getComputePGMRSrc1())); assert(isUInt<32>(PI.ComputePGMRSrc2)); KernelDescriptor.group_segment_fixed_size = PI.LDSSize; KernelDescriptor.private_segment_fixed_size = PI.ScratchSize; - KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1; + KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(); KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2; KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF); @@ -1135,18 +1135,6 @@ ProgInfo.MemOrdered = 1; } - ProgInfo.ComputePGMRSrc1 = - S_00B848_VGPRS(ProgInfo.VGPRBlocks) | - S_00B848_SGPRS(ProgInfo.SGPRBlocks) | - S_00B848_PRIORITY(ProgInfo.Priority) | - S_00B848_FLOAT_MODE(ProgInfo.FloatMode) | - S_00B848_PRIV(ProgInfo.Priv) | - S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) | - S_00B848_DEBUG_MODE(ProgInfo.DebugMode) | - S_00B848_IEEE_MODE(ProgInfo.IEEEMode) | - S_00B848_WGP_MODE(ProgInfo.WgpMode) | - S_00B848_MEM_ORDERED(ProgInfo.MemOrdered); - // 0 = X, 1 = XY, 2 = XYZ unsigned TIDIGCompCnt = 0; if (MFI->hasWorkItemIDZ()) @@ -1195,7 +1183,7 @@ if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { OutStreamer->emitInt32(R_00B848_COMPUTE_PGM_RSRC1); - OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc1); + OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc1()); OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2); OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc2); @@ -1244,12 +1232,10 @@ MD->setEntryPoint(CC, MF.getFunction().getName()); MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU); MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU); - if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { - MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1); + MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC)); + if (AMDGPU::isCompute(CC)) { MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2); } else { - MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) | - S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks)); if (CurrentProgramInfo.ScratchBlocks > 0) MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1)); } @@ -1293,7 +1279,7 @@ AMDGPU::initDefaultAMDKernelCodeT(Out, &STM); Out.compute_pgm_resource_registers = - CurrentProgramInfo.ComputePGMRSrc1 | + CurrentProgramInfo.getComputePGMRSrc1() | (CurrentProgramInfo.ComputePGMRSrc2 << 32); Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64; diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -131,6 +131,7 @@ SIPeepholeSDWA.cpp SIPostRABundler.cpp SIPreEmitPeephole.cpp + SIProgramInfo.cpp SIRegisterInfo.cpp SIRemoveShortExecBranches.cpp SIShrinkInstructions.cpp diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -688,16 +688,37 @@ } // namespace AMDGPU #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 +#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) +#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) +#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) +#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) +#define C_00B028_MEM_ORDERED 0xFDFFFFFF + #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 +#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) +#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) +#define C_00B128_MEM_ORDERED 0xF7FFFFFF + #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 +#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) +#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) +#define C_00B228_WGP_MODE 0xF7FFFFFF +#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) +#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) +#define C_00B228_MEM_ORDERED 0xFDFFFFFF + #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 +#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) +#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) +#define C_00B428_WGP_MODE 0xFBFFFFFF +#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) +#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) +#define C_00B428_MEM_ORDERED 0xFEFFFFFF + #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 -#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 -#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) -#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.h b/llvm/lib/Target/AMDGPU/SIProgramInfo.h --- a/llvm/lib/Target/AMDGPU/SIProgramInfo.h +++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.h @@ -7,7 +7,8 @@ //===----------------------------------------------------------------------===// // /// \file -/// Defines struct to track resource usage for kernels and entry functions. +/// Defines struct to track resource usage and hardware flags for kernels and +/// entry functions. /// // //===----------------------------------------------------------------------===// @@ -15,6 +16,9 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H #define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H +#include "llvm/IR/CallingConv.h" +#include + namespace llvm { /// Track resource usage for kernels / entry functions. @@ -32,8 +36,6 @@ uint32_t MemOrdered = 0; // GFX10+ uint64_t ScratchSize = 0; - uint64_t ComputePGMRSrc1 = 0; - // Fields set in PGM_RSRC2 pm4 packet. uint32_t LDSBlocks = 0; uint32_t ScratchBlocks = 0; @@ -64,6 +66,10 @@ bool VCCUsed = false; SIProgramInfo() = default; + + /// Compute the value of the ComputePGMRsrc1 register. + uint64_t getComputePGMRSrc1() const; + uint64_t getPGMRSrc1(CallingConv::ID CC) const; }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp @@ -0,0 +1,49 @@ +//===-- SIProgramInfo.cpp ----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +/// \file +/// +/// The SIProgramInfo tracks resource usage and hardware flags for kernels and +/// entry functions. +// +//===----------------------------------------------------------------------===// +// + +#include "SIProgramInfo.h" +#include "SIDefines.h" +#include "Utils/AMDGPUBaseInfo.h" + +using namespace llvm; + +uint64_t SIProgramInfo::getComputePGMRSrc1() const { + return S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | + S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | + S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) | + S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode) | + S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered); +} + +uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC) const { + if (AMDGPU::isCompute(CC)) { + return getComputePGMRSrc1(); + } + uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | + S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | + S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) | + S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode); + if (CC == CallingConv::AMDGPU_PS) { + Reg |= S_00B028_MEM_ORDERED(MemOrdered); + } else if (CC == CallingConv::AMDGPU_VS) { + Reg |= S_00B128_MEM_ORDERED(MemOrdered); + } else if (CC == CallingConv::AMDGPU_GS) { + Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered); + } else if (CC == CallingConv::AMDGPU_HS) { + Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered); + } + return Reg; +} diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll @@ -0,0 +1,83 @@ +; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s + +; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata +; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000 +; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f02c0 +; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000 +define amdgpu_cs half @cs_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata +; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f0000 +; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f02c0 +; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f0000 +define amdgpu_es half @es_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata +; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f0000 +; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f02c0 +; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f0000 +define amdgpu_gs half @gs_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata +; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f0000 +; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f02c0 +; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f0000 +define amdgpu_hs half @hs_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata +; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f0000 +; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f02c0 +; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f0000 +define amdgpu_ls half @ls_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata +; below. +; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f0000 +; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f02c0 +; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f0000 +define amdgpu_ps half @ps_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata +; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f0000 +; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f02c0 +; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f0000 +define amdgpu_vs half @vs_amdpal(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdgpu.pal.metadata.msgpack represents this: +; +; .amdgpu_pal_metadata +; --- +; amdpal.pipelines: +; - .internal_pipeline_hash: +; - 0x123456789abcdef0 +; - 0xfedcba9876543210 +; .registers: +; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; ... +; .end_amdgpu_pal_metadata + +!amdgpu.pal.metadata.msgpack = !{!0} +!0 = !{!"\81\b0\61\6d\64\70\61\6c\2e\70\69\70\65\6c\69\6e\65\73\91\82\b7\2e\69\6e\74\65\72\6e\61\6c\5f\70\69\70\65\6c\69\6e\65\5f\68\61\73\68\92\cf\12\34\56\78\9a\bc\de\f0\cf\fe\dc\ba\98\76\54\32\10\aa\2e\72\65\67\69\73\74\65\72\73\81\cd\2c\0b\ce\42\00\00\00"}; diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll @@ -0,0 +1,85 @@ +; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s + +; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata +; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000 +; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c02c0 +; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000 +define amdgpu_cs half @cs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata +; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0000 +; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c02c0 +; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0000 +define amdgpu_es half @es_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata +; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0000 +; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c02c0 +; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0000 +define amdgpu_gs half @gs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata +; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0000 +; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c02c0 +; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0000 +define amdgpu_hs half @hs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata +; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0000 +; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c02c0 +; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0000 +define amdgpu_ls half @ls_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata +; below. +; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0000 +; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c02c0 +; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0000 +define amdgpu_ps half @ps_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata +; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0000 +; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c02c0 +; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0000 +define amdgpu_vs half @vs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } + +; amdgpu.pal.metadata.msgpack represents this: +; +; .amdgpu_pal_metadata +; --- +; amdpal.pipelines: +; - .internal_pipeline_hash: +; - 0x123456789abcdef0 +; - 0xfedcba9876543210 +; .registers: +; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; ... +; .end_amdgpu_pal_metadata + +!amdgpu.pal.metadata.msgpack = !{!0} +!0 = !{!"\81\b0\61\6d\64\70\61\6c\2e\70\69\70\65\6c\69\6e\65\73\91\82\b7\2e\69\6e\74\65\72\6e\61\6c\5f\70\69\70\65\6c\69\6e\65\5f\68\61\73\68\92\cf\12\34\56\78\9a\bc\de\f0\cf\fe\dc\ba\98\76\54\32\10\aa\2e\72\65\67\69\73\74\65\72\73\81\cd\2c\0b\ce\42\00\00\00"}; diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll @@ -0,0 +1,85 @@ +; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s + +; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata +; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000 +; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf02c0 +; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000 +define amdgpu_cs half @cs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata +; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000 +; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf02c0 +; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000 +define amdgpu_es half @es_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata +; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf0000 +; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf02c0 +; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf0000 +define amdgpu_gs half @gs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata +; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf0000 +; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf02c0 +; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf0000 +define amdgpu_hs half @hs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata +; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000 +; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf02c0 +; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000 +define amdgpu_ls half @ls_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata +; below. +; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf0000 +; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf02c0 +; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf0000 +define amdgpu_ps half @ps_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata +; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf0000 +; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf02c0 +; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf0000 +define amdgpu_vs half @vs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +attributes #0 = { "amdgpu-dx10-clamp"="false" } + +; amdgpu.pal.metadata.msgpack represents this: +; +; .amdgpu_pal_metadata +; --- +; amdpal.pipelines: +; - .internal_pipeline_hash: +; - 0x123456789abcdef0 +; - 0xfedcba9876543210 +; .registers: +; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; ... +; .end_amdgpu_pal_metadata + +!amdgpu.pal.metadata.msgpack = !{!0} +!0 = !{!"\81\b0\61\6d\64\70\61\6c\2e\70\69\70\65\6c\69\6e\65\73\91\82\b7\2e\69\6e\74\65\72\6e\61\6c\5f\70\69\70\65\6c\69\6e\65\5f\68\61\73\68\92\cf\12\34\56\78\9a\bc\de\f0\cf\fe\dc\ba\98\76\54\32\10\aa\2e\72\65\67\69\73\74\65\72\73\81\cd\2c\0b\ce\42\00\00\00"}; diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll @@ -0,0 +1,85 @@ +; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s + +; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata +; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000 +; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf02c0 +; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000 +define amdgpu_cs half @cs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata +; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000 +; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf02c0 +; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000 +define amdgpu_es half @es_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata +; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000 +; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf02c0 +; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000 +define amdgpu_gs half @gs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata +; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000 +; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf02c0 +; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000 +define amdgpu_hs half @hs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata +; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000 +; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf02c0 +; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000 +define amdgpu_ls half @ls_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata +; below. +; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000 +; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf02c0 +; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000 +define amdgpu_ps half @ps_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata +; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000 +; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf02c0 +; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000 +define amdgpu_vs half @vs_amdpal(half %arg0) #0 { + %add = fadd half %arg0, 1.0 + ret half %add +} + +attributes #0 = { "amdgpu-ieee"="true" } + +; amdgpu.pal.metadata.msgpack represents this: +; +; .amdgpu_pal_metadata +; --- +; amdpal.pipelines: +; - .internal_pipeline_hash: +; - 0x123456789abcdef0 +; - 0xfedcba9876543210 +; .registers: +; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; ... +; .end_amdgpu_pal_metadata + +!amdgpu.pal.metadata.msgpack = !{!0} +!0 = !{!"\81\b0\61\6d\64\70\61\6c\2e\70\69\70\65\6c\69\6e\65\73\91\82\b7\2e\69\6e\74\65\72\6e\61\6c\5f\70\69\70\65\6c\69\6e\65\5f\68\61\73\68\92\cf\12\34\56\78\9a\bc\de\f0\cf\fe\dc\ba\98\76\54\32\10\aa\2e\72\65\67\69\73\74\65\72\73\81\cd\2c\0b\ce\42\00\00\00"};