Index: llvm/lib/AsmParser/LLLexer.cpp
===================================================================
--- llvm/lib/AsmParser/LLLexer.cpp
+++ llvm/lib/AsmParser/LLLexer.cpp
@@ -594,7 +594,6 @@
   KEYWORD(arm_aapcscc);
   KEYWORD(arm_aapcs_vfpcc);
   KEYWORD(aarch64_vector_pcs);
-  KEYWORD(aarch64_sve_vector_pcs);
   KEYWORD(msp430_intrcc);
   KEYWORD(avr_intrcc);
   KEYWORD(avr_signalcc);
Index: llvm/lib/AsmParser/LLParser.cpp
===================================================================
--- llvm/lib/AsmParser/LLParser.cpp
+++ llvm/lib/AsmParser/LLParser.cpp
@@ -2004,7 +2004,6 @@
 ///   ::= 'arm_aapcscc'
 ///   ::= 'arm_aapcs_vfpcc'
 ///   ::= 'aarch64_vector_pcs'
-///   ::= 'aarch64_sve_vector_pcs'
 ///   ::= 'msp430_intrcc'
 ///   ::= 'avr_intrcc'
 ///   ::= 'avr_signalcc'
@@ -2051,9 +2050,6 @@
   case lltok::kw_arm_aapcscc:    CC = CallingConv::ARM_AAPCS; break;
   case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
   case lltok::kw_aarch64_vector_pcs:CC = CallingConv::AArch64_VectorCall; break;
-  case lltok::kw_aarch64_sve_vector_pcs:
-    CC = CallingConv::AArch64_SVE_VectorCall;
-    break;
   case lltok::kw_msp430_intrcc:  CC = CallingConv::MSP430_INTR; break;
   case lltok::kw_avr_intrcc:     CC = CallingConv::AVR_INTR; break;
   case lltok::kw_avr_signalcc:   CC = CallingConv::AVR_SIGNAL; break;
Index: llvm/lib/AsmParser/LLToken.h
===================================================================
--- llvm/lib/AsmParser/LLToken.h
+++ llvm/lib/AsmParser/LLToken.h
@@ -142,7 +142,6 @@
   kw_arm_aapcscc,
   kw_arm_aapcs_vfpcc,
   kw_aarch64_vector_pcs,
-  kw_aarch64_sve_vector_pcs,
   kw_msp430_intrcc,
   kw_avr_intrcc,
   kw_avr_signalcc,
Index: llvm/lib/IR/AsmWriter.cpp
===================================================================
--- llvm/lib/IR/AsmWriter.cpp
+++ llvm/lib/IR/AsmWriter.cpp
@@ -364,9 +364,6 @@
   case CallingConv::ARM_AAPCS:     Out << "arm_aapcscc"; break;
   case CallingConv::ARM_AAPCS_VFP: Out << "arm_aapcs_vfpcc"; break;
   case CallingConv::AArch64_VectorCall: Out << "aarch64_vector_pcs"; break;
-  case CallingConv::AArch64_SVE_VectorCall:
-    Out << "aarch64_sve_vector_pcs";
-    break;
   case CallingConv::MSP430_INTR:   Out << "msp430_intrcc"; break;
   case CallingConv::AVR_INTR:      Out << "avr_intrcc "; break;
   case CallingConv::AVR_SIGNAL:    Out << "avr_signalcc "; break;
Index: llvm/test/CodeGen/AArch64/arm64-darwin-cc.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-darwin-cc.ll
+++ llvm/test/CodeGen/AArch64/arm64-darwin-cc.ll
@@ -1,9 +1,7 @@
 ; RUN: sed -e "s,CC,cfguard_checkcc,g" %s | not --crash llc -mtriple=arm64-apple-darwin -o - 2>&1 | FileCheck %s --check-prefix=CFGUARD
-; RUN: sed -e "s,CC,aarch64_sve_vector_pcs,g" %s | not --crash llc -mtriple=arm64-apple-darwin -o - 2>&1 | FileCheck %s --check-prefix=SVE_VECTOR_PCS
 
 define CC void @f0() {
   unreachable
 }
 
 ; CFGUARD: Calling convention CFGuard_Check is unsupported on Darwin.
-; SVE_VECTOR_PCS: Calling convention SVE_VectorCall is unsupported on Darwin.
Index: llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
+++ llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
@@ -2,7 +2,9 @@
 # RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prologepilog %s -o - | FileCheck %s
 
 --- |
-  define aarch64_sve_vector_pcs void @fix_restorepoint_p4() { entry: unreachable }
+  ; Function is defined as returning a scalable vector so the SVE PCS is used,
+  ; but this isn't reflected in the MIR.
+  define <vscale x 4 x i32> @fix_restorepoint_p4() { entry: unreachable }
   ; CHECK-LABEL: fix_restorepoint_p4:
   ; CHECK:       // %bb.0: // %entry
   ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
Index: llvm/test/CodeGen/AArch64/framelayout-sve.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-sve.mir
+++ llvm/test/CodeGen/AArch64/framelayout-sve.mir
@@ -35,11 +35,13 @@
   define void @test_stack_arg_sve() { entry: unreachable }
   define void @test_address_sve_out_of_range() { entry: unreachable }
   define void @test_address_gpr_vla() { entry: unreachable }
-  define aarch64_sve_vector_pcs void @save_restore_pregs_sve() { entry: unreachable }
-  define aarch64_sve_vector_pcs void @save_restore_zregs_sve() { entry: unreachable }
-  define aarch64_sve_vector_pcs void @save_restore_sve() { entry: unreachable }
-  define aarch64_sve_vector_pcs void @save_restore_sve_realign() { entry: unreachable }
-  define aarch64_sve_vector_pcs void @frame_layout() { entry: unreachable }
+  ; Functions are defined as returning a scalable vector so the SVE PCS is
+  ; used, but this isn't reflected in the MIR.
+  define <vscale x 4 x i32> @save_restore_pregs_sve() { entry: unreachable }
+  define <vscale x 4 x i32> @save_restore_zregs_sve() { entry: unreachable }
+  define <vscale x 4 x i32> @save_restore_sve() { entry: unreachable }
+  define <vscale x 4 x i32> @save_restore_sve_realign() { entry: unreachable }
+  define <vscale x 4 x i32> @frame_layout() { entry: unreachable }
   define void @fp_relative_index_with_float_save() { entry: unreachable }
 
 ...
Index: llvm/test/CodeGen/AArch64/spillfill-sve.mir
===================================================================
--- llvm/test/CodeGen/AArch64/spillfill-sve.mir
+++ llvm/test/CodeGen/AArch64/spillfill-sve.mir
@@ -6,11 +6,13 @@
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--linux-gnu"
 
-  define aarch64_sve_vector_pcs void @spills_fills_stack_id_ppr() #0 { entry: unreachable }
-  define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr() #0 { entry: unreachable }
-  define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2() #0 { entry: unreachable }
-  define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr3() #0 { entry: unreachable }
-  define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr4() #0 { entry: unreachable }
+  ; Functions are defined as returning a scalable vector so the SVE PCS is
+  ; used, but this isn't reflected in the MIR.
+  define <vscale x 4 x i32> @spills_fills_stack_id_ppr() #0 { entry: unreachable }
+  define <vscale x 4 x i32> @spills_fills_stack_id_zpr() #0 { entry: unreachable }
+  define <vscale x 4 x i32> @spills_fills_stack_id_zpr2() #0 { entry: unreachable }
+  define <vscale x 4 x i32> @spills_fills_stack_id_zpr3() #0 { entry: unreachable }
+  define <vscale x 4 x i32> @spills_fills_stack_id_zpr4() #0 { entry: unreachable }
 
   attributes #0 = { nounwind "target-features"="+sve" }
 
Index: llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
+++ llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
@@ -10,7 +10,7 @@
 ;      z7 =  %z7
 ;      x0 = &%z8
 ;      x1 = &%z9
-define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 4 x i32> %z8, <vscale x 4 x i32> %z9) {
+define <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 4 x i32> %z8, <vscale x 4 x i32> %z9) {
 ; CHECK: name: callee_with_many_sve_arg
 ; CHECK-DAG: [[BASE:%[0-9]+]]:gpr64common = COPY $x1
 ; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
@@ -21,7 +21,7 @@
 }
 
 ; Test that z8 and z9 are passed by reference.
-define aarch64_sve_vector_pcs <vscale x 4 x i32> @caller_with_many_sve_arg(<vscale x 4 x i32> %z) {
+define <vscale x 4 x i32> @caller_with_many_sve_arg(<vscale x 4 x i32> %z) {
 ; CHECK: name: caller_with_many_sve_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
@@ -37,7 +37,7 @@
 ; CHECK-DAG:  $x1 = COPY [[BASE2]]
 ; CHECK-NEXT: BL @callee_with_many_sve_arg
 ; CHECK:      RET_ReallyLR implicit $z0
-  %ret = call aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z)
+  %ret = call <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z)
   ret <vscale x 4 x i32> %ret
 }
 
@@ -47,7 +47,7 @@
 ;      p3 =  %p3
 ;      x0 = &%p4
 ;      x1 = &%p5
-define aarch64_sve_vector_pcs <vscale x 4 x i1> @callee_with_many_svepred_arg(<vscale x 4 x i1> %p0, <vscale x 4 x i1> %p1, <vscale x 4 x i1> %p2, <vscale x 4 x i1> %p3, <vscale x 4 x i1> %p4, <vscale x 4 x i1> %p5) {
+define <vscale x 4 x i1> @callee_with_many_svepred_arg(<vscale x 4 x i1> %p0, <vscale x 4 x i1> %p1, <vscale x 4 x i1> %p2, <vscale x 4 x i1> %p3, <vscale x 4 x i1> %p4, <vscale x 4 x i1> %p5) {
 ; CHECK: name: callee_with_many_svepred_arg
 ; CHECK-DAG: [[BASE:%[0-9]+]]:gpr64common = COPY $x1
 ; CHECK-DAG: [[RES:%[0-9]+]]:ppr = LDR_PXI [[BASE]], 0
@@ -57,7 +57,7 @@
 }
 
 ; Test that p4 and p5 are passed by reference.
-define aarch64_sve_vector_pcs <vscale x 4 x i1> @caller_with_many_svepred_arg(<vscale x 4 x i1> %p) {
+define <vscale x 4 x i1> @caller_with_many_svepred_arg(<vscale x 4 x i1> %p) {
 ; CHECK: name: caller_with_many_svepred_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 1, alignment: 4,
@@ -72,7 +72,7 @@
 ; CHECK-DAG: $x1 = COPY [[BASE2]]
 ; CHECK-NEXT: BL @callee_with_many_svepred_arg
 ; CHECK:     RET_ReallyLR implicit $p0
-  %ret = call aarch64_sve_vector_pcs <vscale x 4 x i1> @callee_with_many_svepred_arg(<vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p)
+  %ret = call <vscale x 4 x i1> @callee_with_many_svepred_arg(<vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p, <vscale x 4 x i1> %p)
   ret <vscale x 4 x i1> %ret
 }
 
@@ -86,7 +86,7 @@
 ;        [sp] =  &%z8
 ;      [sp+8] =  &%z9
 ;
-define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 2 x i64> %z8, <vscale x 4 x i32> %z9) {
+define <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 2 x i64> %z8, <vscale x 4 x i32> %z9) {
 ; CHECK: name: callee_with_many_gpr_sve_arg
 ; CHECK: fixedStack:
 ; CHECK:      - { id: 0, type: default, offset: 8, size: 8, alignment: 8, stack-id: default,
@@ -99,7 +99,7 @@
 }
 
 ; Test that z8 and z9 are passed by reference, where reference is passed on the stack.
-define aarch64_sve_vector_pcs <vscale x 4 x i32> @caller_with_many_gpr_sve_arg(i64 %x, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2) {
+define <vscale x 4 x i32> @caller_with_many_gpr_sve_arg(i64 %x, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2) {
 ; CHECK: name: caller_with_many_gpr_sve_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
@@ -117,6 +117,6 @@
 ; CHECK-DAG: STRXui killed [[BASE2]], [[SP]], 1
 ; CHECK:     BL @callee_with_many_gpr_sve_arg
 ; CHECK:     RET_ReallyLR implicit $z0
-  %ret = call aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2, <vscale x 4 x i32> %z)
+  %ret = call <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2, <vscale x 4 x i32> %z)
   ret <vscale x 4 x i32> %ret
 }
Index: llvm/test/CodeGen/AArch64/sve-calling-convention.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-calling-convention.ll
+++ llvm/test/CodeGen/AArch64/sve-calling-convention.ll
@@ -126,8 +126,7 @@
 }
 
 ; Test that functions returning or taking SVE arguments use the correct
-; callee-saved set when using the default C calling convention (as opposed
-; to aarch64_sve_vector_pcs)
+; callee-saved set when using the default C calling convention.
 
 ; CHECKCSR-LABEL: name: sve_signature_vec_ret_callee
 ; CHECKCSR: callee-saved-register: '$z8'