Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
===================================================================
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1077,7 +1077,26 @@
     // If the frame pointer is eliminated, all frame offsets will be relative to
     // SP not FP. Align to MaxAlign so this works.
     StackAlign = std::max(StackAlign, MaxAlign);
+    int64_t OffsetBeforeAlignment = Offset;
     Offset = alignTo(Offset, StackAlign, Skew);
+
+    // If we have increased the offset to fulfill the alignment constrants,
+    // then the scavenging spill slots may become harder to reach from the
+    // stack pointer, float them so they stay close.
+    if (OffsetBeforeAlignment != Offset && RS && !EarlyScavengingSlots) {
+      SmallVector<int, 2> SFIs;
+      RS->getScavengingFrameIndices(SFIs);
+      LLVM_DEBUG(if (!SFIs.empty()) llvm::dbgs()
+                     << "Adjusting emergency spill slots!\n";);
+      int64_t Delta = Offset - OffsetBeforeAlignment;
+      for (SmallVectorImpl<int>::iterator I = SFIs.begin(), IE = SFIs.end();
+           I != IE; ++I) {
+        LLVM_DEBUG(llvm::dbgs() << "Adjusting offset of emergency spill slot #"
+                                << *I << " from " << MFI.getObjectOffset(*I););
+        MFI.setObjectOffset(*I, MFI.getObjectOffset(*I) - Delta);
+        LLVM_DEBUG(llvm::dbgs() << " to " << MFI.getObjectOffset(*I) << "\n";);
+      }
+    }
   }
 
   // Update frame info to pretend that this is part of the stack...
Index: llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
+++ llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
@@ -5,10 +5,10 @@
 name: LateScavengingSlotRealignment
 # CHECK-LABEL: name: LateScavengingSlotRealignment
 # CHECK: bb.0:
-# CHECK:      STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 3
+# CHECK:      STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 0
 # CHECK-NEXT: $[[SCRATCH]] = ADDXri $sp, 40, 0
 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 4095
-# CHECK-NEXT: $[[SCRATCH]] = LDRXui $sp, 3
+# CHECK-NEXT: $[[SCRATCH]] = LDRXui $sp, 0
 # CHECK: bb.1:
 tracksRegLiveness: true
 frameInfo:
Index: llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
+++ llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
@@ -7,7 +7,7 @@
 # CHECK:      $sp = frame-setup ADDVL_XXI $sp, -1
 # CHECK-NEXT: $sp = frame-setup SUBXri $sp, 8, 12
 # CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0
-# CHECK:      STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 1
+# CHECK:      STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 0
 # CHECK-NEXT: $[[SCRATCH]] = ADDVL_XXI $fp, -1
 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 0
 # CHECK: bb.1:
Index: llvm/test/CodeGen/AArch64/swiftself-scavenger.ll
===================================================================
--- llvm/test/CodeGen/AArch64/swiftself-scavenger.ll
+++ llvm/test/CodeGen/AArch64/swiftself-scavenger.ll
@@ -2,10 +2,10 @@
 ; Check that we reserve an emergency spill slot, even if we added an extra
 ; CSR spill for the values used by the swiftself parameter.
 ; CHECK-LABEL: func:
-; CHECK: str [[REG:x[0-9]+]], [sp, #8]
+; CHECK: str [[REG:x[0-9]+]], [sp]
 ; CHECK: add [[REG]], sp, #248
 ; CHECK: str xzr, [{{\s*}}[[REG]], #32760]
-; CHECK: ldr [[REG]], [sp, #8]
+; CHECK: ldr [[REG]], [sp]
 target triple = "arm64-apple-ios"
 
 @ptr8 = external global i8*
Index: llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
+++ llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
@@ -29,16 +29,14 @@
     ; GFX8: $sgpr4 = frame-setup S_ADD_U32 $sgpr32, 524224, implicit-def $scc
     ; GFX8: $sgpr33 = frame-setup S_AND_B32 killed $sgpr4, 4294443008, implicit-def $scc
     ; GFX8: $sgpr32 = frame-setup S_ADD_U32 $sgpr32, 1572864, implicit-def $scc
-    ; GFX8: $sgpr4 = S_ADD_U32 $sgpr33, 524544, implicit-def $scc
-    ; GFX8: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.3, addrspace 5)
+    ; GFX8: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 12, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.3, addrspace 5)
     ; GFX8: $vgpr3 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
     ; GFX8: $vcc_lo = S_MOV_B32 8192
     ; GFX8: $vgpr3, dead $vcc = V_ADD_CO_U32_e64 killed $vcc_lo, killed $vgpr3, 0, implicit $exec
     ; GFX8: $vgpr0 = V_OR_B32_e32 killed $vgpr3, $vgpr1, implicit $exec
     ; GFX8: $sgpr32 = frame-destroy S_SUB_U32 $sgpr32, 1572864, implicit-def $scc
     ; GFX8: $sgpr33 = V_READLANE_B32 $vgpr2, 0
-    ; GFX8: $sgpr4 = S_ADD_U32 $sgpr33, 524544, implicit-def $scc
-    ; GFX8: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.3, addrspace 5)
+    ; GFX8: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 12, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.3, addrspace 5)
     ; GFX8: S_ENDPGM 0, csr_amdgpu_allvgprs
     ; GFX9-LABEL: name: pei_scavenge_vgpr_spill
     ; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
@@ -46,15 +44,13 @@
     ; GFX9: $sgpr4 = frame-setup S_ADD_U32 $sgpr32, 524224, implicit-def $scc
     ; GFX9: $sgpr33 = frame-setup S_AND_B32 killed $sgpr4, 4294443008, implicit-def $scc
     ; GFX9: $sgpr32 = frame-setup S_ADD_U32 $sgpr32, 1572864, implicit-def $scc
-    ; GFX9: $sgpr4 = S_ADD_U32 $sgpr33, 524544, implicit-def $scc
-    ; GFX9: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.3, addrspace 5)
+    ; GFX9: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 12, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.3, addrspace 5)
     ; GFX9: $vgpr3 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
     ; GFX9: $vgpr3 = V_ADD_U32_e32 8192, killed $vgpr3, implicit $exec
     ; GFX9: $vgpr0 = V_OR_B32_e32 killed $vgpr3, $vgpr1, implicit $exec
     ; GFX9: $sgpr32 = frame-destroy S_SUB_U32 $sgpr32, 1572864, implicit-def $scc
     ; GFX9: $sgpr33 = V_READLANE_B32 $vgpr2, 0
-    ; GFX9: $sgpr4 = S_ADD_U32 $sgpr33, 524544, implicit-def $scc
-    ; GFX9: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.3, addrspace 5)
+    ; GFX9: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 12, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.3, addrspace 5)
     ; GFX9: S_ENDPGM 0, csr_amdgpu_allvgprs
     ; GFX9-FLATSCR-LABEL: name: pei_scavenge_vgpr_spill
     ; GFX9-FLATSCR: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
Index: llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
@@ -0,0 +1,599 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# REQUIRES: asserts
+# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \
+# RUN:     -verify-machineinstrs %s | FileCheck %s
+#
+# RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \
+# RUN:     -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \
+# RUN:     | FileCheck --check-prefix=DEBUG %s
+#
+# DEBUG: Adjusting emergency spill slots!
+# DEBUG: Adjusting offset of emergency spill slot #15 from -4112 to -8192
+
+--- |
+  ; ModuleID = 'reduced.ll'
+  source_filename = "frame_layout-1253b1.cpp"
+  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+  target triple = "riscv64"
+
+  ; Function Attrs: nounwind
+  define weak_odr dso_local void @foo(i8* %ay) local_unnamed_addr #0 {
+  ; CHECK-LABEL: foo:
+  ; CHECK:       # %bb.0: # %entry
+  ; CHECK-NEXT:    addi sp, sp, -2032
+  ; CHECK-NEXT:    sd ra, 2024(sp)
+  ; CHECK-NEXT:    sd s0, 2016(sp)
+  ; CHECK-NEXT:    sd s1, 2008(sp)
+  ; CHECK-NEXT:    sd s2, 2000(sp)
+  ; CHECK-NEXT:    sd s3, 1992(sp)
+  ; CHECK-NEXT:    sd s4, 1984(sp)
+  ; CHECK-NEXT:    sd s5, 1976(sp)
+  ; CHECK-NEXT:    sd s6, 1968(sp)
+  ; CHECK-NEXT:    sd s7, 1960(sp)
+  ; CHECK-NEXT:    sd s8, 1952(sp)
+  ; CHECK-NEXT:    sd s9, 1944(sp)
+  ; CHECK-NEXT:    sd s10, 1936(sp)
+  ; CHECK-NEXT:    sd s11, 1928(sp)
+  ; CHECK-NEXT:    addi s0, sp, 2032
+  ; CHECK-NEXT:    lui a1, 2
+  ; CHECK-NEXT:    addiw a1, a1, -2032
+  ; CHECK-NEXT:    sub sp, sp, a1
+  ; CHECK-NEXT:    srli a1, sp, 12
+  ; CHECK-NEXT:    slli sp, a1, 12
+  ; CHECK-NEXT:    lbu a0, 0(a0)
+  ; CHECK-NEXT:    addi s5, a0, 5
+  ; CHECK-NEXT:    add s2, s5, a0
+  ; CHECK-NEXT:    addi t2, a0, 20
+  ; CHECK-NEXT:    add t1, t2, a0
+  ; CHECK-NEXT:    slli t5, a0, 2
+  ; CHECK-NEXT:    add t4, t5, a0
+  ; CHECK-NEXT:    slli a3, a0, 1
+  ; CHECK-NEXT:    add s4, a3, a0
+  ; CHECK-NEXT:    divu a1, t4, s4
+  ; CHECK-NEXT:    addi s6, a0, 32
+  ; CHECK-NEXT:    divu a1, a1, s6
+  ; CHECK-NEXT:    addi s7, a0, 29
+  ; CHECK-NEXT:    divu a1, a1, s7
+  ; CHECK-NEXT:    addi a6, a0, 28
+  ; CHECK-NEXT:    divu a1, a1, a6
+  ; CHECK-NEXT:    addi a7, a0, 27
+  ; CHECK-NEXT:    divu a1, a1, a7
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    addi t0, a0, 6
+  ; CHECK-NEXT:    div a1, a1, t0
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    addi t3, a0, 25
+  ; CHECK-NEXT:    div a1, a1, t3
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    addi t6, a0, 24
+  ; CHECK-NEXT:    div a1, a1, t6
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    addi s8, a0, 2
+  ; CHECK-NEXT:    div a1, a1, s8
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t1
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    addi s9, a0, 9
+  ; CHECK-NEXT:    div a1, a1, s9
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a4, a1, 48
+  ; CHECK-NEXT:    addi s10, a0, 8
+  ; CHECK-NEXT:    div a4, a4, s10
+  ; CHECK-NEXT:    slli a4, a4, 48
+  ; CHECK-NEXT:    srai a4, a4, 48
+  ; CHECK-NEXT:    addi ra, a0, 7
+  ; CHECK-NEXT:    div a4, a4, ra
+  ; CHECK-NEXT:    slli a4, a4, 48
+  ; CHECK-NEXT:    srai a4, a4, 48
+  ; CHECK-NEXT:    div a4, a4, s2
+  ; CHECK-NEXT:    slli a4, a4, 56
+  ; CHECK-NEXT:    srai s1, a4, 56
+  ; CHECK-NEXT:    lui a4, 10923
+  ; CHECK-NEXT:    addiw a4, a4, -1365
+  ; CHECK-NEXT:    slli a4, a4, 12
+  ; CHECK-NEXT:    addi a4, a4, -1365
+  ; CHECK-NEXT:    slli a4, a4, 12
+  ; CHECK-NEXT:    addi a4, a4, -1365
+  ; CHECK-NEXT:    slli a4, a4, 12
+  ; CHECK-NEXT:    addi s11, a4, -1365
+  ; CHECK-NEXT:    mulh s1, s1, s11
+  ; CHECK-NEXT:    srli a2, s1, 63
+  ; CHECK-NEXT:    add a2, a2, s1
+  ; CHECK-NEXT:    slli a2, a2, 56
+  ; CHECK-NEXT:    srai a2, a2, 56
+  ; CHECK-NEXT:    addi s3, a0, 4
+  ; CHECK-NEXT:    div a2, a2, s3
+  ; CHECK-NEXT:    slli a2, a2, 56
+  ; CHECK-NEXT:    srai a2, a2, 56
+  ; CHECK-NEXT:    lui a1, 21845
+  ; CHECK-NEXT:    addiw a1, a1, 1365
+  ; CHECK-NEXT:    slli a1, a1, 12
+  ; CHECK-NEXT:    addi a1, a1, 1365
+  ; CHECK-NEXT:    slli a1, a1, 12
+  ; CHECK-NEXT:    addi a1, a1, 1365
+  ; CHECK-NEXT:    slli a1, a1, 12
+  ; CHECK-NEXT:    addi a1, a1, 1366
+  ; CHECK-NEXT:    mulh a2, a2, a1
+  ; CHECK-NEXT:    srli a4, a2, 63
+  ; CHECK-NEXT:    add a2, a2, a4
+  ; CHECK-NEXT:    slli a2, a2, 56
+  ; CHECK-NEXT:    srai a2, a2, 56
+  ; CHECK-NEXT:    slli a4, a0, 3
+  ; CHECK-NEXT:    sub a5, a4, a0
+  ; CHECK-NEXT:    div a2, a2, a5
+  ; CHECK-NEXT:    slli a2, a2, 48
+  ; CHECK-NEXT:    srai a2, a2, 48
+  ; CHECK-NEXT:    addi s1, zero, 6
+  ; CHECK-NEXT:    mul s1, a0, s1
+  ; CHECK-NEXT:    div a2, a2, s1
+  ; CHECK-NEXT:    slli a2, a2, 48
+  ; CHECK-NEXT:    srai a2, a2, 48
+  ; CHECK-NEXT:    div a2, a2, a3
+  ; CHECK-NEXT:    sd a6, 0(sp)
+  ; CHECK-NEXT:    lui a6, 1
+  ; CHECK-NEXT:    addiw a6, a6, -8
+  ; CHECK-NEXT:    add a6, a6, sp
+  ; CHECK-NEXT:    sd a2, 0(a6)
+  ; CHECK-NEXT:    ld a6, 0(sp)
+  ; CHECK-NEXT:    divu a2, a0, a3
+  ; CHECK-NEXT:    divu a2, a2, a3
+  ; CHECK-NEXT:    divu a2, a2, s4
+  ; CHECK-NEXT:    divu a2, a2, t5
+  ; CHECK-NEXT:    divu a2, a2, t4
+  ; CHECK-NEXT:    divu a2, a2, s1
+  ; CHECK-NEXT:    slli a2, a2, 48
+  ; CHECK-NEXT:    srai a2, a2, 48
+  ; CHECK-NEXT:    div a2, a2, a5
+  ; CHECK-NEXT:    slli a2, a2, 48
+  ; CHECK-NEXT:    srai a2, a2, 48
+  ; CHECK-NEXT:    div a2, a2, a4
+  ; CHECK-NEXT:    slli a2, a2, 48
+  ; CHECK-NEXT:    srai a2, a2, 48
+  ; CHECK-NEXT:    mulh a1, a2, a1
+  ; CHECK-NEXT:    srli a2, a1, 63
+  ; CHECK-NEXT:    add a1, a1, a2
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s3
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s5
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s2
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, ra
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s10
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s9
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t2
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t1
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s8
+  ; CHECK-NEXT:    slli a1, a1, 56
+  ; CHECK-NEXT:    srai a1, a1, 56
+  ; CHECK-NEXT:    mulh a1, a1, s11
+  ; CHECK-NEXT:    srli a2, a1, 63
+  ; CHECK-NEXT:    srli a1, a1, 2
+  ; CHECK-NEXT:    add a1, a1, a2
+  ; CHECK-NEXT:    slli a1, a1, 56
+  ; CHECK-NEXT:    srai a1, a1, 56
+  ; CHECK-NEXT:    div a1, a1, t6
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t3
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t0
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, a7
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, a6
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s7
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s7
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s6
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s6
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, s4
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t5
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a1, a1, t4
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    div a0, a1, a0
+  ; CHECK-NEXT:    lui a1, 1
+  ; CHECK-NEXT:    addiw a1, a1, -8
+  ; CHECK-NEXT:    add a1, a1, sp
+  ; CHECK-NEXT:    ld a1, 0(a1)
+  ; CHECK-NEXT:    slli a1, a1, 48
+  ; CHECK-NEXT:    srai a1, a1, 48
+  ; CHECK-NEXT:    slli a0, a0, 48
+  ; CHECK-NEXT:    srai a0, a0, 48
+  ; CHECK-NEXT:    mul a0, a0, a1
+  ; CHECK-NEXT:    sw a0, 0(a0)
+  ; CHECK-NEXT:    lui a0, 2
+  ; CHECK-NEXT:    sub sp, s0, a0
+  ; CHECK-NEXT:    lui a0, 2
+  ; CHECK-NEXT:    addiw a0, a0, -2032
+  ; CHECK-NEXT:    add sp, sp, a0
+  ; CHECK-NEXT:    ld s11, 1928(sp)
+  ; CHECK-NEXT:    ld s10, 1936(sp)
+  ; CHECK-NEXT:    ld s9, 1944(sp)
+  ; CHECK-NEXT:    ld s8, 1952(sp)
+  ; CHECK-NEXT:    ld s7, 1960(sp)
+  ; CHECK-NEXT:    ld s6, 1968(sp)
+  ; CHECK-NEXT:    ld s5, 1976(sp)
+  ; CHECK-NEXT:    ld s4, 1984(sp)
+  ; CHECK-NEXT:    ld s3, 1992(sp)
+  ; CHECK-NEXT:    ld s2, 2000(sp)
+  ; CHECK-NEXT:    ld s1, 2008(sp)
+  ; CHECK-NEXT:    ld s0, 2016(sp)
+  ; CHECK-NEXT:    ld ra, 2024(sp)
+  ; CHECK-NEXT:    addi sp, sp, 2032
+  ; CHECK-NEXT:    ret
+  entry:
+    %ba = alloca double, align 4096
+    %0 = load i8, i8* %ay, align 1, !tbaa !0
+    %conv = zext i8 %0 to i32
+    %add30.i = add nuw nsw i32 %conv, 5
+    %add33.i = add nuw nsw i32 %add30.i, %conv
+    %add41.i = add nuw nsw i32 %conv, 20
+    %add44.i = add nuw nsw i32 %add41.i, %conv
+    %1 = zext i8 %0 to i16
+    %div.i.lhs.trunc = mul nuw nsw i16 %1, 5
+    %2 = zext i8 %0 to i16
+    %div.i.rhs.trunc = mul nuw nsw i16 %2, 3
+    %div.i171 = udiv i16 %div.i.lhs.trunc, %div.i.rhs.trunc
+    %3 = zext i8 %0 to i16
+    %div2.i.rhs.trunc = add nuw nsw i16 %3, 32
+    %div2.i172 = udiv i16 %div.i171, %div2.i.rhs.trunc
+    %4 = zext i8 %0 to i16
+    %div3.i.rhs.trunc = add nuw nsw i16 %4, 29
+    %div3.i173 = udiv i16 %div2.i172, %div3.i.rhs.trunc
+    %5 = zext i8 %0 to i16
+    %div4.i.rhs.trunc = add nuw nsw i16 %5, 28
+    %div4.i174 = udiv i16 %div3.i173, %div4.i.rhs.trunc
+    %6 = zext i8 %0 to i16
+    %div5.i.rhs.trunc = add nuw nsw i16 %6, 27
+    %div5.i175 = udiv i16 %div4.i174, %div5.i.rhs.trunc
+    %7 = zext i8 %0 to i16
+    %div6.i.rhs.trunc = add nuw nsw i16 %7, 6
+    %div6.i176 = sdiv i16 %div5.i175, %div6.i.rhs.trunc
+    %8 = zext i8 %0 to i16
+    %div7.i.rhs.trunc = add nuw nsw i16 %8, 25
+    %div7.i177 = sdiv i16 %div6.i176, %div7.i.rhs.trunc
+    %9 = zext i8 %0 to i16
+    %div8.i.rhs.trunc = add nuw nsw i16 %9, 24
+    %div8.i178 = sdiv i16 %div7.i177, %div8.i.rhs.trunc
+    %10 = zext i8 %0 to i16
+    %div9.i.rhs.trunc = add nuw nsw i16 %10, 2
+    %div9.i179 = sdiv i16 %div8.i178, %div9.i.rhs.trunc
+    %div10.i.rhs.trunc = trunc i32 %add44.i to i16
+    %div10.i180 = sdiv i16 %div9.i179, %div10.i.rhs.trunc
+    %11 = zext i8 %0 to i16
+    %div11.i.rhs.trunc = add nuw nsw i16 %11, 9
+    %div11.i181 = sdiv i16 %div10.i180, %div11.i.rhs.trunc
+    %12 = zext i8 %0 to i16
+    %div12.i.rhs.trunc = add nuw nsw i16 %12, 8
+    %div12.i182 = sdiv i16 %div11.i181, %div12.i.rhs.trunc
+    %13 = zext i8 %0 to i16
+    %div13.i.rhs.trunc = add nuw nsw i16 %13, 7
+    %div13.i183 = sdiv i16 %div12.i182, %div13.i.rhs.trunc
+    %div14.i.rhs.trunc = trunc i32 %add33.i to i16
+    %div14.i184 = sdiv i16 %div13.i183, %div14.i.rhs.trunc
+    %div15.i.lhs.trunc = trunc i16 %div14.i184 to i8
+    %div15.i185 = sdiv i8 %div15.i.lhs.trunc, 6
+    %div16.i.lhs.trunc = sext i8 %div15.i185 to i16
+    %14 = zext i8 %0 to i16
+    %div16.i.rhs.trunc = add nuw nsw i16 %14, 4
+    %div16.i186 = sdiv i16 %div16.i.lhs.trunc, %div16.i.rhs.trunc
+    %div17.i.lhs.trunc = trunc i16 %div16.i186 to i8
+    %div17.i187 = sdiv i8 %div17.i.lhs.trunc, 3
+    %div18.i.lhs.trunc = sext i8 %div17.i187 to i16
+    %15 = zext i8 %0 to i16
+    %div18.i.rhs.trunc = mul nuw nsw i16 %15, 7
+    %div18.i188 = sdiv i16 %div18.i.lhs.trunc, %div18.i.rhs.trunc
+    %16 = zext i8 %0 to i16
+    %div19.i.rhs.trunc = mul nuw nsw i16 %16, 6
+    %div19.i189 = sdiv i16 %div18.i188, %div19.i.rhs.trunc
+    %conv.tr = zext i8 %0 to i16
+    %div20.i.rhs.trunc = shl nuw nsw i16 %conv.tr, 1
+    %div20.i190 = sdiv i16 %div19.i189, %div20.i.rhs.trunc
+    %div20.i.sext = sext i16 %div20.i190 to i32
+    %div.i65.lhs.trunc = zext i8 %0 to i16
+    %div.i65191 = udiv i16 %div.i65.lhs.trunc, %div20.i.rhs.trunc
+    %div2.i67192 = udiv i16 %div.i65191, %div20.i.rhs.trunc
+    %div3.i69193 = udiv i16 %div2.i67192, %div.i.rhs.trunc
+    %conv.tr223 = zext i8 %0 to i16
+    %div4.i71.rhs.trunc = shl nuw nsw i16 %conv.tr223, 2
+    %div4.i71194 = udiv i16 %div3.i69193, %div4.i71.rhs.trunc
+    %div5.i73195 = udiv i16 %div4.i71194, %div.i.lhs.trunc
+    %div6.i75196 = udiv i16 %div5.i73195, %div19.i.rhs.trunc
+    %div7.i77197 = sdiv i16 %div6.i75196, %div18.i.rhs.trunc
+    %div8.i79.rhs.trunc = shl nuw nsw i16 %div.i65.lhs.trunc, 3
+    %div8.i79198 = sdiv i16 %div7.i77197, %div8.i79.rhs.trunc
+    %div9.i81199 = sdiv i16 %div8.i79198, 3
+    %div10.i83200 = sdiv i16 %div9.i81199, %div16.i.rhs.trunc
+    %div11.i85.rhs.trunc = trunc i32 %add30.i to i16
+    %div11.i85201 = sdiv i16 %div10.i83200, %div11.i85.rhs.trunc
+    %div12.i87202 = sdiv i16 %div11.i85201, %div14.i.rhs.trunc
+    %div13.i89203 = sdiv i16 %div12.i87202, %div13.i.rhs.trunc
+    %div14.i91204 = sdiv i16 %div13.i89203, %div12.i.rhs.trunc
+    %div15.i93205 = sdiv i16 %div14.i91204, %div11.i.rhs.trunc
+    %div16.i95.rhs.trunc = trunc i32 %add41.i to i16
+    %div16.i95206 = sdiv i16 %div15.i93205, %div16.i95.rhs.trunc
+    %div17.i97207 = sdiv i16 %div16.i95206, %div10.i.rhs.trunc
+    %div18.i99208 = sdiv i16 %div17.i97207, %div9.i.rhs.trunc
+    %div19.i100.lhs.trunc = trunc i16 %div18.i99208 to i8
+    %div19.i100209 = sdiv i8 %div19.i100.lhs.trunc, 24
+    %div20.i102.lhs.trunc = sext i8 %div19.i100209 to i16
+    %div20.i102210 = sdiv i16 %div20.i102.lhs.trunc, %div8.i.rhs.trunc
+    %div21.i211 = sdiv i16 %div20.i102210, %div7.i.rhs.trunc
+    %div22.i212 = sdiv i16 %div21.i211, %div6.i.rhs.trunc
+    %div23.i213 = sdiv i16 %div22.i212, %div5.i.rhs.trunc
+    %div24.i214 = sdiv i16 %div23.i213, %div4.i.rhs.trunc
+    %div25.i215 = sdiv i16 %div24.i214, %div3.i.rhs.trunc
+    %div26.i216 = sdiv i16 %div25.i215, %div3.i.rhs.trunc
+    %div27.i217 = sdiv i16 %div26.i216, %div2.i.rhs.trunc
+    %div28.i218 = sdiv i16 %div27.i217, %div2.i.rhs.trunc
+    %div29.i219 = sdiv i16 %div28.i218, %div.i.rhs.trunc
+    %div30.i220 = sdiv i16 %div29.i219, %div4.i71.rhs.trunc
+    %div31.i221 = sdiv i16 %div30.i220, %div.i.lhs.trunc
+    %div32.i222 = sdiv i16 %div31.i221, %div.i65.lhs.trunc
+    %div32.i.sext = sext i16 %div32.i222 to i32
+    %mul.i = mul nuw nsw i32 %div32.i.sext, %div20.i.sext
+    store i32 %mul.i, i32* undef, align 8, !tbaa !3
+    ret void
+  }
+
+  attributes #0 = { nounwind "target-features"="+a,+c,+d,+f,+m,+relax,-save-restore" }
+
+  !0 = !{!1, !1, i64 0}
+  !1 = !{!"omnipotent char", !2, i64 0}
+  !2 = !{!"Simple C++ TBAA"}
+  !3 = !{!4, !6, i64 8}
+  !4 = !{!"_ZTS2au", !5, i64 0, !6, i64 8}
+  !5 = !{!"any pointer", !1, i64 0}
+  !6 = !{!"int", !1, i64 0}
+
+...
+---
+name:            foo
+alignment:       2
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x10' }
+frameInfo:
+  maxAlignment:    4096
+stack:
+  - { id: 0, name: ba, size: 8, alignment: 4096 }
+  - { id: 1, type: spill-slot, size: 8, alignment: 8 }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x10
+
+    renamable $x10 = LBU killed renamable $x10, 0 :: (load 1 from %ir.ay, !tbaa !0)
+    renamable $x21 = ADDI renamable $x10, 5
+    renamable $x18 = ADD renamable $x21, renamable $x10
+    renamable $x7 = ADDI renamable $x10, 20
+    renamable $x6 = ADD renamable $x7, renamable $x10
+    renamable $x30 = SLLI renamable $x10, 2
+    renamable $x29 = ADD renamable $x30, renamable $x10
+    renamable $x13 = SLLI renamable $x10, 1
+    renamable $x20 = ADD renamable $x13, renamable $x10
+    renamable $x11 = DIVU renamable $x29, renamable $x20
+    renamable $x22 = nuw nsw ADDI renamable $x10, 32
+    renamable $x11 = DIVU killed renamable $x11, renamable $x22
+    renamable $x23 = nuw nsw ADDI renamable $x10, 29
+    renamable $x11 = DIVU killed renamable $x11, renamable $x23
+    renamable $x16 = nuw nsw ADDI renamable $x10, 28
+    renamable $x11 = DIVU killed renamable $x11, renamable $x16
+    renamable $x17 = nuw nsw ADDI renamable $x10, 27
+    renamable $x11 = DIVU killed renamable $x11, renamable $x17
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x5 = nuw nsw ADDI renamable $x10, 6
+    renamable $x11 = DIV killed renamable $x11, renamable $x5
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x28 = nuw nsw ADDI renamable $x10, 25
+    renamable $x11 = DIV killed renamable $x11, renamable $x28
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x31 = nuw nsw ADDI renamable $x10, 24
+    renamable $x11 = DIV killed renamable $x11, renamable $x31
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x24 = nuw nsw ADDI renamable $x10, 2
+    renamable $x11 = DIV killed renamable $x11, renamable $x24
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, renamable $x6
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x25 = nuw nsw ADDI renamable $x10, 9
+    renamable $x11 = DIV killed renamable $x11, renamable $x25
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x14 = SRAI killed renamable $x11, 48
+    renamable $x26 = nuw nsw ADDI renamable $x10, 8
+    renamable $x14 = DIV killed renamable $x14, renamable $x26
+    renamable $x14 = SLLI killed renamable $x14, 48
+    renamable $x14 = SRAI killed renamable $x14, 48
+    renamable $x1 = nuw nsw ADDI renamable $x10, 7
+    renamable $x14 = DIV killed renamable $x14, renamable $x1
+    renamable $x14 = SLLI killed renamable $x14, 48
+    renamable $x14 = SRAI killed renamable $x14, 48
+    renamable $x14 = DIV killed renamable $x14, renamable $x18
+    renamable $x14 = SLLI killed renamable $x14, 56
+    renamable $x9 = SRAI killed renamable $x14, 56
+    renamable $x14 = LUI 10923
+    renamable $x14 = ADDIW killed renamable $x14, -1365
+    renamable $x14 = SLLI killed renamable $x14, 12
+    renamable $x14 = ADDI killed renamable $x14, -1365
+    renamable $x14 = SLLI killed renamable $x14, 12
+    renamable $x14 = ADDI killed renamable $x14, -1365
+    renamable $x14 = SLLI killed renamable $x14, 12
+    renamable $x27 = ADDI killed renamable $x14, -1365
+    renamable $x9 = MULH killed renamable $x9, renamable $x27
+    renamable $x12 = SRLI renamable $x9, 63
+    renamable $x12 = ADD killed renamable $x9, killed renamable $x12
+    renamable $x12 = SLLI killed renamable $x12, 56
+    renamable $x12 = SRAI killed renamable $x12, 56
+    renamable $x19 = nuw nsw ADDI renamable $x10, 4
+    renamable $x12 = DIV killed renamable $x12, renamable $x19
+    renamable $x12 = SLLI killed renamable $x12, 56
+    renamable $x12 = SRAI killed renamable $x12, 56
+    renamable $x11 = LUI 21845
+    renamable $x11 = ADDIW killed renamable $x11, 1365
+    renamable $x11 = SLLI killed renamable $x11, 12
+    renamable $x11 = ADDI killed renamable $x11, 1365
+    renamable $x11 = SLLI killed renamable $x11, 12
+    renamable $x11 = ADDI killed renamable $x11, 1365
+    renamable $x11 = SLLI killed renamable $x11, 12
+    renamable $x11 = ADDI killed renamable $x11, 1366
+    renamable $x12 = MULH killed renamable $x12, renamable $x11
+    renamable $x14 = SRLI renamable $x12, 63
+    renamable $x12 = ADD killed renamable $x12, killed renamable $x14
+    renamable $x12 = SLLI killed renamable $x12, 56
+    renamable $x12 = SRAI killed renamable $x12, 56
+    renamable $x14 = SLLI renamable $x10, 3
+    renamable $x15 = SUB renamable $x14, renamable $x10
+    renamable $x12 = DIV killed renamable $x12, renamable $x15
+    renamable $x12 = SLLI killed renamable $x12, 48
+    renamable $x12 = SRAI killed renamable $x12, 48
+    renamable $x9 = ADDI $x0, 6
+    renamable $x9 = nuw nsw MUL renamable $x10, killed renamable $x9
+    renamable $x12 = DIV killed renamable $x12, renamable $x9
+    renamable $x12 = SLLI killed renamable $x12, 48
+    renamable $x12 = SRAI killed renamable $x12, 48
+    renamable $x12 = DIV killed renamable $x12, renamable $x13
+    SD killed renamable $x12, %stack.1, 0
+    renamable $x12 = DIVU renamable $x10, renamable $x13
+    renamable $x12 = DIVU killed renamable $x12, killed renamable $x13
+    renamable $x12 = DIVU killed renamable $x12, renamable $x20
+    renamable $x12 = DIVU killed renamable $x12, renamable $x30
+    renamable $x12 = DIVU killed renamable $x12, renamable $x29
+    renamable $x12 = DIVU killed renamable $x12, killed renamable $x9
+    renamable $x12 = SLLI killed renamable $x12, 48
+    renamable $x12 = SRAI killed renamable $x12, 48
+    renamable $x12 = DIV killed renamable $x12, killed renamable $x15
+    renamable $x12 = SLLI killed renamable $x12, 48
+    renamable $x12 = SRAI killed renamable $x12, 48
+    renamable $x12 = DIV killed renamable $x12, killed renamable $x14
+    renamable $x12 = SLLI killed renamable $x12, 48
+    renamable $x12 = SRAI killed renamable $x12, 48
+    renamable $x11 = MULH killed renamable $x12, killed renamable $x11
+    renamable $x12 = SRLI renamable $x11, 63
+    renamable $x11 = ADD killed renamable $x11, killed renamable $x12
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x19
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x21
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x18
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x1
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x26
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x25
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x7
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x6
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x24
+    renamable $x11 = SLLI killed renamable $x11, 56
+    renamable $x11 = SRAI killed renamable $x11, 56
+    renamable $x11 = MULH killed renamable $x11, killed renamable $x27
+    renamable $x12 = SRLI renamable $x11, 63
+    renamable $x11 = SRLI killed renamable $x11, 2
+    renamable $x11 = ADD killed renamable $x11, killed renamable $x12
+    renamable $x11 = SLLI killed renamable $x11, 56
+    renamable $x11 = SRAI killed renamable $x11, 56
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x31
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x28
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x5
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x17
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x16
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, renamable $x23
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x23
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, renamable $x22
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x22
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x20
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x30
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x11 = DIV killed renamable $x11, killed renamable $x29
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x10 = DIV killed renamable $x11, killed renamable $x10
+    renamable $x11 = LD %stack.1, 0
+    renamable $x11 = SLLI killed renamable $x11, 48
+    renamable $x11 = SRAI killed renamable $x11, 48
+    renamable $x10 = SLLI killed renamable $x10, 48
+    renamable $x10 = SRAI killed renamable $x10, 48
+    renamable $x10 = MUL killed renamable $x10, killed renamable $x11
+    SW killed renamable $x10, undef renamable $x10, 0 :: (store 4 into `i32* undef`, align 8, !tbaa !3)
+    PseudoRET
+
+...
Index: llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
===================================================================
--- llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
+++ llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
@@ -253,10 +253,10 @@
 ; CHECK-NEXT:    adds r1, #1
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    str r0, [sp, #12]
+; CHECK-NEXT:    str r0, [sp]
 ; CHECK-NEXT:    ldr r0, .LCPI5_0
 ; CHECK-NEXT:    str r5, [r0, r7]
-; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp]
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    subs r4, r7, #7