diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -553,8 +553,7 @@
 G_VECREDUCE_SEQ_FADD, G_VECREDUCE_SEQ_FMUL
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-The SEQ variants perform reductions in sequential order. The first operand is
-an initial scalar accumulator value, and the second operand is the vector to reduce.
+The SEQ variants perform reductions in sequential order.
 
 G_VECREDUCE_FADD, G_VECREDUCE_FMUL
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1265,36 +1265,17 @@
 // Vector reductions
 //------------------------------------------------------------------------------
 
-def G_VECREDUCE_SEQ_FADD : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
-  let hasSideEffects = 0;
-}
-
-def G_VECREDUCE_SEQ_FMUL : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
-  let hasSideEffects = 0;
-}
-
-def G_VECREDUCE_FADD : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
-  let hasSideEffects = 0;
-}
-
-def G_VECREDUCE_FMUL : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
-  let hasSideEffects = 0;
-}
-
 class VectorReduction : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$v);
   let hasSideEffects = 0;
 }
 
+def G_VECREDUCE_SEQ_FADD : VectorReduction;
+def G_VECREDUCE_SEQ_FMUL : VectorReduction;
+def G_VECREDUCE_FADD : VectorReduction;
+def G_VECREDUCE_FMUL : VectorReduction;
+
 def G_VECREDUCE_FMAX : VectorReduction;
 def G_VECREDUCE_FMIN : VectorReduction;
 
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1491,18 +1491,7 @@
   case TargetOpcode::G_VECREDUCE_SEQ_FADD:
   case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
   case TargetOpcode::G_VECREDUCE_FADD:
-  case TargetOpcode::G_VECREDUCE_FMUL: {
-    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
-    LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
-    LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
-    if (!DstTy.isScalar())
-      report("Vector reduction requires a scalar destination type", MI);
-    if (!Src1Ty.isScalar())
-      report("FADD/FMUL vector reduction requires a scalar 1st operand", MI);
-    if (!Src2Ty.isVector())
-      report("FADD/FMUL vector reduction must have a vector 2nd operand", MI);
-    break;
-  }
+  case TargetOpcode::G_VECREDUCE_FMUL:
   case TargetOpcode::G_VECREDUCE_FMAX:
   case TargetOpcode::G_VECREDUCE_FMIN:
   case TargetOpcode::G_VECREDUCE_ADD:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -613,16 +613,16 @@
 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_VECREDUCE_SEQ_FADD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_SEQ_FADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_SEQ_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_SEQ_FMUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_VECREDUCE_FMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
diff --git a/llvm/test/MachineVerifier/test_vector_reductions.mir b/llvm/test/MachineVerifier/test_vector_reductions.mir
--- a/llvm/test/MachineVerifier/test_vector_reductions.mir
+++ b/llvm/test/MachineVerifier/test_vector_reductions.mir
@@ -21,15 +21,9 @@
     %vec_v2s64:_(<2 x s64>) = IMPLICIT_DEF
     %scalar_s64:_(s64) = IMPLICIT_DEF
 
-    %seq_fadd:_(<2 x s64>) = G_VECREDUCE_SEQ_FADD %scalar_s64, %vec_v2s64
+    %seq_fadd:_(<2 x s64>) = G_VECREDUCE_SEQ_FADD %vec_v2s64
     ; CHECK: Bad machine code: Vector reduction requires a scalar destination type
 
-    %dst:_(s64) = G_VECREDUCE_SEQ_FADD %vec_v2s64, %vec_v2s64
-    ; CHECK: Bad machine code: FADD/FMUL vector reduction requires a scalar 1st operand
-
-    %dst:_(s64) = G_VECREDUCE_SEQ_FADD %scalar_s64, %scalar_s64
-    ; CHECK: Bad machine code: FADD/FMUL vector reduction must have a vector 2nd operand
-
     %dst2:_(s64) = G_VECREDUCE_MUL %scalar_s64
     ; CHECK: Bad machine code: Vector reduction requires vector source
 ...